coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Subrata Banik (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Julius Werner, Kapil Porwal, Paul Menzel. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 11: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/85326/comment/1c478dcc_c0a32ce4?us… : PS9, Line 286: printk > > I was thinking we could keep a data structure that maps EC host commands to timestamps. That way, we'd always know which timestamp belongs to which EC host command. > > So you would basically be creating hundreds of new timestamps... I don't think this is worth it. I really don't think timestamps are the right tool for this level of debugging anyway. Proposal is to add a timestamp to each host command. It's a good start, and we can always grow the list if we want. However, this is more about adding a timestamp around each host cmd. If we have better ways to append the host cmd number into the timestamp string, then we can avoid making several entries. > > > We already have a similar feature for FSP. When we build FSP with a specific flag, it adds more timestamps that aren't needed during regular boot. > > Okay, but that's a bit of a different situation. The FSP only runs in one specific part of the boot flow and (I think?) there's already a timestamp right before and after it to mark that part. So if you turn on FSP debugging timestamps it's not that surprising that the time between start and end of the FSP is broken up by additional timestamps. I think the proposed change is also valid for EC. There are timestamps before and after certain coreboot APIs that may call into other EC host commands. Therefore, when EC started populating more timestamps, it would only be in between those two outer layer timestamps. Of course, we would need to sync the EC and AP timestamps. > > But EC commands happen all over the place, and will change the values for all sorts of timestamps that have nothing to do with the EC. Not sure if i'm able to follow why would the existing time will change ? it will bring more granularity in timestamp which being elapse while performing EC host cmd. -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 11 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 06:47:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Subrata Banik (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Kapil Porwal. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email ) Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/85449/comment/f455523c_568cfacc?us… : PS4, Line 152: 0x380 > @subratabanik@google.com, please do let me know if this is a concern. if this is not generic then better we get this from a Kconfig (platform can decide rather this is more generic place) ? default value should be zero and we skip programming if value is 0 WDYT ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 06:42:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Add SD card configurations
by Jarried Lin (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85565?usp=email ) Change subject: mb/google/rauru: Add SD card configurations ...................................................................... mb/google/rauru: Add SD card configurations Rauru reference design has SD card interfaces, so we configure it in mainboard_init() in ramstage. TEST=Build pass. BUG=b:317009620 Change-Id: Ia9f12df85c5f9f9d134990edcf82bf0df9ea995d Signed-off-by: Andy-ld Lu <andy-ld.lu(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/mainboard.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85565/1 diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index a85f303..18a1699 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -30,6 +30,8 @@ select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT select TPM_GOOGLE_TI50 if VBOOT + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC config MAINBOARD_DIR string diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index 9c238c7..94f52e8 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -11,6 +11,7 @@ #include <soc/i2c.h> #include <soc/pcie.h> #include <soc/usb.h> +#include <soc/msdc.h> #include "gpio.h" @@ -55,6 +56,9 @@ power_on_fpmcu(); configure_audio(); + if (CONFIG(RAURU_SDCARD_INIT)) + mtk_msdc_configure_sdcard(); + if (dpm_init()) printk(BIOS_ERR, "dpm init failed, DVFS may not work\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9f12df85c5f9f9d134990edcf82bf0df9ea995d Gerrit-Change-Number: 85565 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add SD card configurations
by Jarried Lin (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85564?usp=email ) Change subject: soc/mediatek/mt8196: Add SD card configurations ...................................................................... soc/mediatek/mt8196: Add SD card configurations Rauru reference design has SD card interfaces, so we have to configure it in ramstage. Implement msdc.c (memory and SD Card controller) to place the SD card drivers. This implementation is based on chapter 10.3 in MT8196 Functional Specification. TEST=Build pass BUG=b:317009620 Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765 Signed-off-by: Andy-ld Lu <andy-ld.lu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/msdc.c 2 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85564/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index bc8fe04..14dc348 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -47,6 +47,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += msdc.c ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c diff --git a/src/soc/mediatek/mt8196/msdc.c b/src/soc/mediatek/mt8196/msdc.c new file mode 100644 index 0000000..9d4d7fd --- /dev/null +++ b/src/soc/mediatek/mt8196/msdc.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 10.3 + */ + +#include <device/mmio.h> +#include <gpio.h> +#include <soc/addressmap.h> +#include <soc/regulator.h> +#include <soc/msdc.h> + +DEFINE_BITFIELD(MSDC1_DRV, 17, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_2, 22, 20) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 10, 8) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 2, 0) + +#define MSDC1_DRV_OFFSET_0 0x0 + +#define MSDC1_DRV_VALUE_0 0x12492 +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x1002D3F0, + MSDC1_GPIO_MODE1_BASE = 0x1002D400, +}; + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_BM3_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + unsigned int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set SD card cmd/dat/clk pins driving to 6mA */ + SET32_BITFIELDS(gpio_base + MSDC1_DRV_OFFSET_0, MSDC1_DRV, MSDC1_DRV_VALUE_0); + + /* set SD card dat0/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_2, MSDC1_GPIO_MODE0_VALUE); + + /* set SD card dat3/dat2/dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE); + + /* enable SD card power */ + mainboard_enable_regulator(MTK_REGULATOR_VMCH, true); + mainboard_enable_regulator(MTK_REGULATOR_VMC, true); + mainboard_set_regulator_voltage(MTK_REGULATOR_VMCH, 3000000); + mainboard_set_regulator_voltage(MTK_REGULATOR_VMC, 3000000); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765 Gerrit-Change-Number: 85564 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Implement regulator interface
by Jarried Lin (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hope Wang. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85563?usp=email to review the following change. Change subject: mb/google/rauru: Implement regulator interface ...................................................................... mb/google/rauru: Implement regulator interface Control regulator more easily with regulator interface. TEST=build pass BUG=b:317009620 Change-Id: I3cad68dbb2c5873c4e00066da18b1593b88ff499 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/regulator.c 2 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/85563/1 diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk index d5eb8af..d383629 100644 --- a/src/mainboard/google/rauru/Makefile.mk +++ b/src/mainboard/google/rauru/Makefile.mk @@ -9,3 +9,4 @@ romstage-y += romstage.c ramstage-y += mainboard.c +ramstage-y += regulator.c diff --git a/src/mainboard/google/rauru/regulator.c b/src/mainboard/google/rauru/regulator.c new file mode 100644 index 0000000..6e190f7 --- /dev/null +++ b/src/mainboard/google/rauru/regulator.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <soc/mt6373.h> +#include <soc/regulator.h> + +#define MTK_REGULATOR_INVALID -1 + +static int get_mt6373_regulator_id(enum mtk_regulator regulator) +{ + switch (regulator) { + case MTK_REGULATOR_VMCH: + return MT6373_VMCH; + case MTK_REGULATOR_VMC: + return MT6373_VMC; + default: + return MTK_REGULATOR_INVALID; + } +} + +void mainboard_set_regulator_voltage(enum mtk_regulator regulator, uint32_t voltage_uv) +{ + int id; + + id = get_mt6373_regulator_id(regulator); + if (id < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return; + } + + if (id == MT6373_VMCH) + mt6373_set_vmch_voltage(voltage_uv); + else if (id == MT6373_VMC) + mt6373_set_vmc_voltage(voltage_uv); + else + printk(BIOS_WARNING, "Regulator ID %d: not supported\n", regulator); +} + +uint32_t mainboard_get_regulator_voltage(enum mtk_regulator regulator) +{ + int id; + + id = get_mt6373_regulator_id(regulator); + if (id < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return 0; + } + + if (id == MT6373_VMCH) + return mt6373_get_vmch_voltage(); + else if (id == MT6373_VMC) + return mt6373_get_vmc_voltage(); + else + printk(BIOS_WARNING, "Regulator ID %d: not supported\n", regulator); + + return 0; +} + +int mainboard_enable_regulator(enum mtk_regulator regulator, bool enable) +{ + int id; + + id = get_mt6373_regulator_id(regulator); + if (id < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return -1; + } + + if (id == MT6373_VMCH) + mt6373_enable_vmch(enable); + else if (id == MT6373_VMC) + mt6373_enable_vmc(enable); + else + printk(BIOS_WARNING, "Regulator ID %d: not supported\n", regulator); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cad68dbb2c5873c4e00066da18b1593b88ff499 Gerrit-Change-Number: 85563 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85547?usp=email ) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85547/comment/53991dd4_32f7343b?us… : PS1, Line 11: # EC memory map range is 0x900-0x9ff > Updated Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 3 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 12 Dec 2024 06:33:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Jayvik Desai (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email ) Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/85449/comment/2ba1a8d1_d1b13070?us… : PS4, Line 152: 0x380 > I don't think it's generic, but this is the address used by ENE for indexed access. @subratabanik@google.com, please do let me know if this is a concern. -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 06:33:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/google/brya/var/uldrenite: update gpio settings
by Dtrain Hsu (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85522?usp=email ) Change subject: mb/google/brya/var/uldrenite: update gpio settings ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/uldrenite/gpio.c: https://review.coreboot.org/c/coreboot/+/85522/comment/7557f13a_b6b360be?us… : PS3, Line 153: PAD_CFG_GPI_LOCK Would you help to check the ts int should set to PAD_CFG_GPI_APIC? -- To view, visit https://review.coreboot.org/c/coreboot/+/85522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c5cb298fd0a4108af8f65abd9eeddbfe5b7afc4 Gerrit-Change-Number: 85522 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 12 Dec 2024 06:14:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yu-Ping Wu (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 21 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 05:47:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21
by Alok Agarwal (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Kapil Porwal, Ronak Kanabar, Subrata Banik, Vikrant L Jadeja, srinivas.kulkarni(a)intel.com. Alok Agarwal has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/84656?usp=email ) Change subject: vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21 ...................................................................... Patch Set 7: (1 comment) This change is ready for review. File src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/MemInfoHob.h: https://review.coreboot.org/c/coreboot/+/84656/comment/77b84e3a_f7f7522d?us… : PS2, Line 1: /** @file : This file contains definitions required for creation of : Memory S3 Save data, Memory Info data and Memory Platform : data hobs. : : @copyright : Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved. : This program and the accompanying materials are licensed and made available under : the terms and conditions of the BSD License that accompanies this distribution. : The full text of the license may be found at : http://opensource.org/licenses/bsd-license.php. : THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, : : WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. : : @par Specification Reference: : **/ : #ifndef _MEM_INFO_HOB_H_ : #define _MEM_INFO_HOB_H_ : : : #pragma pack (push, 1) : : extern EFI_GUID gSiMemoryS3DataGuid; : extern EFI_GUID gSiMemoryS3Data2Guid; : extern EFI_GUID gSiMemoryInfoDataGuid; : extern EFI_GUID gSiMemoryPlatformDataGuid; : : #define MAX_NODE 2 : #define MAX_CH 4 : #define MAX_DDR5_CH 2 : #define MAX_DIMM 2 : // Must match definitions in : // Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h : #define HOB_MAX_SAGV_POINTS 4 : : /// : /// Host reset states from MRC. : /// : #define WARM_BOOT 2 : : #define R_MC_CHNL_RANK_PRESENT 0x7C : #define B_RANK0_PRS BIT0 : #define B_RANK1_PRS BIT1 : #define B_RANK2_PRS BIT4 : #define B_RANK3_PRS BIT5 : : // @todo remove and use the MdePkg\Include\Pi\PiHob.h : #if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) : #ifndef __HOB__H__ : typedef struct _EFI_HOB_GENERIC_HEADER { : UINT16 HobType; : UINT16 HobLength; : UINT32 Reserved; : } EFI_HOB_GENERIC_HEADER; : : typedef struct _EFI_HOB_GUID_TYPE { : EFI_HOB_GENERIC_HEADER Header; : EFI_GUID Name; : /// : /// Guid specific data goes here : /// : } EFI_HOB_GUID_TYPE; : #endif : #endif : : /// : /// Defines taken from MRC so avoid having to include MrcInterface.h : /// : : // : // Matches MAX_SPD_SAVE define in MRC : // : #ifndef MAX_SPD_SAVE : #define MAX_SPD_SAVE 29 : #endif : : // : // MRC version description. : // : typedef struct { : UINT8 Major; ///< Major version number : UINT8 Minor; ///< Minor version number : UINT8 Rev; ///< Revision number : UINT8 Build; ///< Build number : } SiMrcVersion; : : // : // Matches MrcChannelSts enum in MRC : // : #ifndef CHANNEL_NOT_PRESENT : #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. : #endif : #ifndef CHANNEL_DISABLED : #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. : #endif : #ifndef CHANNEL_PRESENT : #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. : #endif : : // : // Matches MrcDimmSts enum in MRC : // : #ifndef DIMM_ENABLED : #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. : #endif : #ifndef DIMM_DISABLED : #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. : #endif : #ifndef DIMM_PRESENT : #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. : #endif : #ifndef DIMM_NOT_PRESENT : #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. : #endif : : // : // Matches MrcBootMode enum in MRC : // : #ifndef __MRC_BOOT_MODE__ : #define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h : #ifndef INT32_MAX : #define INT32_MAX (0x7FFFFFFF) : #endif //INT32_MAX : typedef enum { : bmCold, ///< Cold boot : bmWarm, ///< Warm boot : bmS3, ///< S3 resume : bmFast, ///< Fast boot : MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. : MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. : } MRC_BOOT_MODE; : #endif //__MRC_BOOT_MODE__ : : // : // Matches MrcDdrType enum in MRC : // : #ifndef MRC_DDR_TYPE_DDR5 : #define MRC_DDR_TYPE_DDR5 1 : #endif : #ifndef MRC_DDR_TYPE_LPDDR5 : #define MRC_DDR_TYPE_LPDDR5 2 : #endif : #ifndef MRC_DDR_TYPE_LPDDR4 : #define MRC_DDR_TYPE_LPDDR4 3 : #endif : #ifndef MRC_DDR_TYPE_UNKNOWN : #define MRC_DDR_TYPE_UNKNOWN 4 : #endif : : #define MAX_PROFILE_NUM 7 // number of memory profiles supported : #define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported : : #ifndef MAX_RCOMP_TARGETS : #define MAX_RCOMP_TARGETS 5 : #endif : : #ifndef MAX_ODT_ENTRIES : #define MAX_ODT_ENTRIES 11 : #endif : : #define MAX_TRACE_REGION 5 : #define MAX_TRACE_CACHE_TYPE 2 : : // : // DIMM timings : // : typedef struct { : UINT32 tCK; ///< Memory cycle time, in femtoseconds. : UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. : UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. : UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. : UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. : UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. : UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. : UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. : UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. : UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. : UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. : UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. : UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. : UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. : UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. : UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. : UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. : UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. : UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. : UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. : UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. : UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. : UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. : } MRC_CH_TIMING; : : typedef struct { : UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay : } MRC_IP_TIMING; : : /// : /// Memory SMBIOS & OC Memory Data Hob : /// : typedef struct { : UINT8 Status; ///< See MrcDimmStatus for the definition of this field. : UINT8 DimmId; : UINT32 DimmCapacity; ///< DIMM size in MBytes. : UINT16 MfgId; : UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes : UINT8 RankInDimm; ///< The number of ranks in this DIMM. : UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. : UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. : UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. : UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. : UINT16 Speed; ///< The maximum capable speed of the device, in MHz : UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. : } DIMM_INFO; : : typedef struct { : UINT8 Status; ///< Indicates whether this channel should be used. : UINT8 ChannelId; : UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. : MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. : DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. : } CHANNEL_INFO; : : typedef struct { : UINT8 Status; ///< Indicates whether this controller should be used. : UINT16 DeviceId; ///< The PCI device id of this memory controller. : UINT8 RevisionId; ///< The PCI revision id of this memory controller. : UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. : CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. : } CONTROLLER_INFO; : : typedef struct { : UINT64 BaseAddress; ///< Trace Base Address : UINT64 TotalSize; ///< Total Trace Region of Same Cache type : UINT8 CacheType; ///< Trace Cache Type : UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code : UINT8 Rsvd[2]; : } PSMI_MEM_INFO; : : /// This data structure contains per-SaGv timing values that are considered output by the MRC. : typedef struct { : UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s : MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec : MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific : } HOB_SAGV_TIMING_OUT; : : /// This data structure contains SAGV config values that are considered output by the MRC. : typedef struct { : UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. : UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. : HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; : } HOB_SAGV_INFO; : : typedef struct { : UINT8 Revision; : UINT16 DataWidth; ///< Data width, in bits, of this memory device : /** As defined in SMBIOS 3.0 spec : Section 7.18.2 and Table 75 : **/ : UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 : UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) : UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) : /** As defined in SMBIOS 3.0 spec : Section 7.17.3 and Table 72 : **/ : UINT8 ErrorCorrectionType; : : SiMrcVersion Version; : BOOLEAN EccSupport; : UINT8 MemoryProfile; : UINT32 TotalPhysicalMemorySize; : UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. : UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. : UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed : BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. : UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 : UINT8 RefClk; : UINT32 VddVoltage[MAX_PROFILE_NUM]; : UINT32 VddqVoltage[MAX_PROFILE_NUM]; : UINT32 VppVoltage[MAX_PROFILE_NUM]; : UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; : UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; : CONTROLLER_INFO Controller[MAX_NODE]; : UINT32 NumPopulatedChannels; ///< Total number of memory channels populated : HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. : BOOLEAN IsIbeccEnabled; : UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels : UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows : UINT16 PprRepairFails; ///< PPR: Counts of repair failure : UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status : } MEMORY_INFO_DATA_HOB; : : /** : Memory Platform Data Hob : : Revision 1: : - Initial version. : Revision 2: : - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields : **/ : typedef struct { : UINT8 Revision; : UINT8 Reserved[3]; : UINT32 BootMode; : UINT32 TsegSize; : UINT32 TsegBase; : UINT32 PrmrrSize; : UINT64 PrmrrBase; : UINT32 GttBase; : UINT32 MmioSize; : UINT32 PciEBaseAddress; : PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; : PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; : BOOLEAN MrcBasicMemoryTestPass; : } MEMORY_PLATFORM_DATA; : : typedef struct { : EFI_HOB_GUID_TYPE EfiHobGuidType; : MEMORY_PLATFORM_DATA Data; : UINT8 *Buffer; : } MEMORY_PLATFORM_DATA_HOB; : : #pragma pack (pop) : : #endif // _MEM_INFO_HOB_H_ > Fix End of line issue Fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/84656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a1164060f7e91f8fa4ada60421bf87fb17ad541 Gerrit-Change-Number: 84656 Gerrit-PatchSet: 7 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Thu, 12 Dec 2024 05:40:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com>

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