coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0
by Ashish Kumar Mishra (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Subrata Banik. Ashish Kumar Mishra has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/85567?usp=email ) Change subject: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Brya already FSI'ed and we won't be able to update the RO image therefore, no way we can enable this […] As per this bug 323474612 issue seen only in mainline. This patch is applicable only for mainline. Not for the FSI. -- To view, visit https://review.coreboot.org/c/coreboot/+/85567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b543b3c9e5c462208c36aba4b47e66362e49ae Gerrit-Change-Number: 85567 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:31:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE
by Patrick Rudolph (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85569?usp=email ) Change subject: soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE ...................................................................... soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE Make use of exception handling in every stage. Additionally this enables breakpoints in all stages, making NULL dereferences and stack overflows easier to detect. TEST: Stack canary exceptions are seen in romstage on ibm/sbp1. Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/85569/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index e1a4ac5..f61de56 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -46,6 +46,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select IDT_IN_EVERY_STAGE if XEON_SP_COMMON_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/85569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e Gerrit-Change-Number: 85569 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Patrick Rudolph (Code Review) 12 Dec '24

12 Dec '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... cpu/intel/car/romstage: Fix false-positive stack corruption Fix regression introduced in commit 03518727313119a8c7a273eb745663c99f8e4d22 ("arch/x86: Add breakpoint to stack canary"). romstage_main writes to the stack-canary, but since that's expected temporarily disable the breakpoint. This only caused a warning on platforms that do select IDT_IN_EVERY_STAGE, since those install the stack canary breakpoint. TEST: No more exceptions are printed in romstage when IDT_IN_EVERY_STAGE is enabled. Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85568/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 7df512d..9607a3a 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -3,6 +3,7 @@ #include <adainit.h> #include <arch/romstage.h> #include <arch/symbols.h> +#include <arch/stack_canary_breakpoint.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -35,9 +36,14 @@ stack_base = (u32 *)(_ecar_stack - size); + /* Disable breakpoint since stack is intentionally corrupted */ + stack_canary_breakpoint_remove(); + for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + stack_canary_breakpoint_init(); + if (CONFIG(VBOOT_EARLY_EC_SYNC)) vboot_sync_ec(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Kapil Porwal (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jamie Chen, Jayvik Desai, Jeremy Soller, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85529/comment/90347c03_3ba83568?us… : PS3, Line 7: a > Articles can be omitted in the summary/title. Acknowledged https://review.coreboot.org/c/coreboot/+/85529/comment/ac602333_aaff25ce?us… : PS3, Line 8: > Maybe mention the motivation of incorrect DMI information. DMI is only a way to ensure that the intended channels were disabled. The motivation is to disable certain channels on demand. File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/21336358_8cb6297d?us… : PS1, Line 252: if (ch_disable_mask == 0) { > Per intel PDG doc "LPDDR5 x32 memory down placement and block diagram", MC0CH0/MC0CH1 enabled or MC0 […] Is this rule applicable to memory down topology only? -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:20:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0
by Subrata Banik (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro. Subrata Banik has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/85567?usp=email ) Change subject: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0 ...................................................................... Patch Set 2: Code-Review-2 (1 comment) Patchset: PS2: Brya already FSI'ed and we won't be able to update the RO image therefore, no way we can enable this feature for infield device -- To view, visit https://review.coreboot.org/c/coreboot/+/85567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b543b3c9e5c462208c36aba4b47e66362e49ae Gerrit-Change-Number: 85567 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:19:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0
by Name of user not set (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Subrata Banik. srinivas.kulkarni(a)intel.com has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/85567?usp=email ) Change subject: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b543b3c9e5c462208c36aba4b47e66362e49ae Gerrit-Change-Number: 85567 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:10:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0
by Ashish Kumar Mishra (Code Review) 12 Dec '24

12 Dec '24

Ashish Kumar Mishra has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/85567?usp=email ) Change subject: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b543b3c9e5c462208c36aba4b47e66362e49ae Gerrit-Change-Number: 85567 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:03:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
by Rui Zhou (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85566?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown ...................................................................... mb/google/nissa/var/rull: For probe, change unprovisioned to unknown The nissa project fw branch is more suitable for compatibility with unknown, so the compatible methods of wifi and ssd are replaced. BUG=b:383675207 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 2 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85566/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Gerrit-Change-Number: 85566 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
by Rui Zhou (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85566?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown ...................................................................... mb/google/nissa/var/rull: For probe, change unprovisioned to unknown The nissa project fw branch is more suitable for compatibility with UNknown, so the compatible methods of wifi and ssd are replaced. BUG=b:383675207 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 2 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85566/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Gerrit-Change-Number: 85566 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: For fw_config probe, change unprovisioned t...
by Rui Zhou (Code Review) 12 Dec '24

12 Dec '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85566?usp=email ) Change subject: mb/google/nissa/var/rull: For fw_config probe, change unprovisioned to unknown ...................................................................... mb/google/nissa/var/rull: For fw_config probe, change unprovisioned to unknown The nissa project fw branch is more suitable for compatibility with UNknown, so the compatible methods of wifi and ssd are replaced. BUG=b:383675207 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 2 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85566/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 92bc5d4..633d5bc 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -6,6 +6,7 @@ field WIFI 8 9 option WIFI_CNVI_WIFI6E 0 option WIFI_PCIE_WIFI7 1 + option WIFI_UNKNOWN 2 end end @@ -393,8 +394,8 @@ register "add_acpi_dma_property" = "true" device generic 0 on end end - probe WIFI WIFI_CNVI_WIFI6E - probe unprovisioned + probe WIFI WIFI_CNVI_WIFI6E + probe WIFI WIFI_UNKNOWN end device ref pcie_rp4 on # PCIe 4 WLAN @@ -416,7 +417,7 @@ device generic 0 on end end probe WIFI WIFI_PCIE_WIFI7 - probe unprovisioned + probe WIFI WIFI_UNKNOWN end device ref pch_espi on chip ec/google/chromeec @@ -518,7 +519,10 @@ register "desc" = ""PCIe Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI WIFI_PCIE_WIFI7 + probe WIFI WIFI_UNKNOWN + end end chip drivers/usb/acpi register "desc" = ""CNVi Bluetooth"" @@ -526,6 +530,7 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port10 on probe WIFI WIFI_CNVI_WIFI6E + probe WIFI WIFI_UNKNOWN end end chip drivers/usb/acpi @@ -569,15 +574,14 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "srcclk_pin" = "1" - device generic 0 on - probe STORAGE STORAGE_NVME - probe unprovisioned - end + device generic 0 on end end + probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN end device ref emmc on probe STORAGE STORAGE_EMMC - probe unprovisioned + probe STORAGE STORAGE_UNKNOWN end device ref hda on chip drivers/sof diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index e1a95e6..4f8fd47 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -18,7 +18,7 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))) { + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) { printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); config->cnvi_bt_core = true; config->cnvi_bt_audio_offload = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/85566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Gerrit-Change-Number: 85566 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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coreboot-gerrit December 2024