coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/rauru: Implement regulator interface
by Jarried Lin (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85563?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Implement regulator interface ...................................................................... mb/google/rauru: Implement regulator interface Control regulator more easily with regulator interface. TEST=build pass BUG=b:317009620 Change-Id: I3cad68dbb2c5873c4e00066da18b1593b88ff499 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/regulator.c 2 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/85563/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cad68dbb2c5873c4e00066da18b1593b88ff499 Gerrit-Change-Number: 85563 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) ( 17 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... soc/mediatek/mt8196: Initialize SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable it. It takes 20 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314 mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes) TEST=can see the sspm logs. BUG=b:372173976 Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85516 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/include/soc/sspm.h M src/soc/mediatek/common/sspm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/sspm_sram.c 7 files changed, 39 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/sspm.h b/src/soc/mediatek/common/include/soc/sspm.h index ff405ce..81f9a62 100644 --- a/src/soc/mediatek/common/include/soc/sspm.h +++ b/src/soc/mediatek/common/include/soc/sspm.h @@ -10,5 +10,8 @@ u32 sw_rstn; }; static struct sspm_regs *const sspm_reg = (void *)SSPM_CFG_BASE; + +void sspm_enable_sram(void); void sspm_init(void); + #endif /* SOC_MEDIATEK_COMMON_SSPM_H */ diff --git a/src/soc/mediatek/common/sspm.c b/src/soc/mediatek/common/sspm.c index 0a4d5b0..d1031f5 100644 --- a/src/soc/mediatek/common/sspm.c +++ b/src/soc/mediatek/common/sspm.c @@ -16,8 +16,15 @@ .reset = reset_sspm, }; +__weak void sspm_enable_sram(void) +{ + /* do nothing. */ +} + void sspm_init(void) { + sspm_enable_sram(); + sspm.load_buffer = _dram_dma; sspm.buffer_size = REGION_SIZE(dram_dma); diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 984e379..2133dbb 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -38,4 +38,11 @@ default "dpm.pm" help The file name of the MediaTek DPM PM firmware. + +config SSPM_FIRMWARE + string + default "sspm.bin" + help + The file name of the MediaTek SSPM firmware. + endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 2a01ee5..f48f380 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -47,6 +47,7 @@ ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += soc.c +ramstage-y += ../common/sspm.c sspm_sram.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c ramstage-y += pmif_spmi.c @@ -61,7 +62,8 @@ mcu-firmware-files := \ $(CONFIG_DPM_DM_FIRMWARE) \ - $(CONFIG_DPM_PM_FIRMWARE) + $(CONFIG_DPM_PM_FIRMWARE) \ + $(CONFIG_SSPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index b252eec..cc57292 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -153,6 +153,8 @@ SPMI_MST_BASE = IO_PHYS + 0x0C01C000, SPMI_MST_P_BASE = IO_PHYS + 0x0C01C800, VLP_AO_DEBUG_BASE = IO_PHYS + 0x0C031000, + SSPM_SRAM_BASE = IO_PHYS + 0x0C300000, + SSPM_CFG_BASE = IO_PHYS + 0x0C340000, SYSTIMER_BASE = IO_PHYS + 0x0C400000, VLP_TRACKER_BASE = IO_PHYS + 0x0C4E0000, MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 8aca5d6..0fe6909 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -6,6 +6,7 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/pcie.h> +#include <soc/sspm.h> #include <soc/symbols.h> #include <symbols.h> @@ -26,6 +27,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + sspm_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8196/sspm_sram.c b/src/soc/mediatek/mt8196/sspm_sram.c new file mode 100644 index 0000000..5c9a80e --- /dev/null +++ b/src/soc/mediatek/mt8196/sspm_sram.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/sspm.h> + +#define SSPM_SRAM_CON (SPM_BASE + 0xEE4) +#define SPM_PRJ_CODE 0xB160001 +#define SSPM_SRAM_SLEEP_B 0x10 +#define SSPM_SRAM_ISOINT_B 0x2 + +void sspm_enable_sram(void) +{ + write32p(SPM_BASE, SPM_PRJ_CODE); + write32p(SSPM_SRAM_CON, SSPM_SRAM_SLEEP_B | SSPM_SRAM_ISOINT_B); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 19 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso2: Create a quandiso2 variant
by Shon Wang (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kyle Lin, Nick Vaccaro, Shon Wang, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kyle Lin, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85570?usp=email to look at the new patch set (#5). Change subject: mb/google/nissa/var/quandiso2: Create a quandiso2 variant ...................................................................... mb/google/nissa/var/quandiso2: Create a quandiso2 variant This patch creates a new quandiso2 variant which is a Twin Lake platform. This variant uses Quandiso board mounted with the Twin Lake SOC and hence the plan is to reuse the existing quandiso code. BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85570/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c Gerrit-Change-Number: 85570 Gerrit-PatchSet: 5 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0
by Subrata Banik (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro. Subrata Banik has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/85567?usp=email ) Change subject: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > As per this bug 323474612 issue seen only in mainline. This patch is applicable only for mainline. Not for the FSI. > > are you aware that VBOOT_CBFS_INTEGRATION depends on Ti50 and Ti50 only started post Brya. No way we can enable this for Brya device. https://chromium-review.googlesource.com/c/chromiumos/overlays/chromiumos-o… -- To view, visit https://review.coreboot.org/c/coreboot/+/85567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b543b3c9e5c462208c36aba4b47e66362e49ae Gerrit-Change-Number: 85567 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
by Kun Liu (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Kun Liu has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85566?usp=email ) Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Gerrit-Change-Number: 85566 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:47:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0
by Subrata Banik (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro. Subrata Banik has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/85567?usp=email ) Change subject: mb/google/brya: Enable VBOOT_CBFS_INTEGRATION for brya0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > As per this bug 323474612 issue seen only in mainline. This patch is applicable only for mainline. Not for the FSI. are you aware that VBOOT_CBFS_INTEGRATION depends on Ti50 and Ti50 only started post Brya. No way we can enable this for Brya device. -- To view, visit https://review.coreboot.org/c/coreboot/+/85567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b543b3c9e5c462208c36aba4b47e66362e49ae Gerrit-Change-Number: 85567 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:46:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso2: Create a quandiso2 variant
by Shon Wang (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kyle Lin, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kyle Lin, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85570?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/quandiso2: Create a quandiso2 variant ...................................................................... mb/google/nissa/var/quandiso2: Create a quandiso2 variant This patch creates a new quandiso2 variant which is a Twin Lake platform. This variant uses Quandiso board mounted with the Twin Lake SOC and hence the plan is to reuse the existing quandiso code. BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85570/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c Gerrit-Change-Number: 85570 Gerrit-PatchSet: 2 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Christian Walter (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Patrick Rudolph. Christian Walter has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:38:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso2: Create a quandiso2 variant
by Shon Wang (Code Review) 12 Dec '24

12 Dec '24

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85570?usp=email ) Change subject: mb/google/nissa/var/quandiso2: Create a quandiso2 variant ...................................................................... mb/google/nissa/var/quandiso2: Create a quandiso2 variant This patch creates a new quandiso2 variant which is a Twin Lake platform. This variant uses Quandiso board mounted with the Twin Lake SOC and hence the plan is to reuse the existing quandiso code. BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85570/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b54b0db..c853692 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -452,6 +452,16 @@ select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_QUANDISO2 + select BOARD_GOOGLE_BASEBOARD_NISSA + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_SX9324 + select HAVE_WWAN_POWER_SEQUENCE + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_REDRIX select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9755 @@ -713,6 +723,7 @@ default 0x1 if BOARD_GOOGLE_PRIMUS default 0x0 if BOARD_GOOGLE_PUJJO default 0x0 if BOARD_GOOGLE_QUANDISO + default 0x0 if BOARD_GOOGLE_QUANDISO2 default 0x1 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX4ES default 0x0 if BOARD_GOOGLE_RIVEN @@ -787,6 +798,7 @@ default 13 if BOARD_GOOGLE_PRIMUS default 13 if BOARD_GOOGLE_PUJJO default 13 if BOARD_GOOGLE_QUANDISO + default 13 if BOARD_GOOGLE_QUANDISO2 default 13 if BOARD_GOOGLE_REDRIX default 13 if BOARD_GOOGLE_REDRIX4ES default 13 if BOARD_GOOGLE_RIVEN @@ -865,6 +877,7 @@ default "Primus" if BOARD_GOOGLE_PRIMUS default "Pujjo" if BOARD_GOOGLE_PUJJO default "Quandiso" if BOARD_GOOGLE_QUANDISO + default "Quandiso2" if BOARD_GOOGLE_QUANDISO2 default "Redrix" if BOARD_GOOGLE_REDRIX default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES default "Riven" if BOARD_GOOGLE_RIVEN @@ -934,6 +947,7 @@ default "primus" if BOARD_GOOGLE_PRIMUS default "pujjo" if BOARD_GOOGLE_PUJJO default "quandiso" if BOARD_GOOGLE_QUANDISO + default "quandiso" if BOARD_GOOGLE_QUANDISO2 default "redrix" if BOARD_GOOGLE_REDRIX default "redrix4es" if BOARD_GOOGLE_REDRIX4ES default "riven" if BOARD_GOOGLE_RIVEN diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 6167976..f8f6b32 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -119,6 +119,9 @@ config BOARD_GOOGLE_QUANDISO bool "-> Quandiso" +config BOARD_GOOGLE_QUANDISO2 + bool "-> Quandiso2" + config BOARD_GOOGLE_REDRIX bool "-> Redrix" -- To view, visit https://review.coreboot.org/c/coreboot/+/85570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c Gerrit-Change-Number: 85570 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: arch/x86: Add breakpoint to stack canary
by Patrick Rudolph (Code Review) 12 Dec '24

12 Dec '24

Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84833?usp=email ) Change subject: arch/x86: Add breakpoint to stack canary ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: > I'm also seeing stack corruption detected on a CML chromebook at the start of romstage (haven't test […] Thanks for testing. I made a fix here: https://review.coreboot.org/c/coreboot/+/85568 It was not seen on Xeon-SP as it didn't select `IDT_IN_EVERY_STAGE` -- To view, visit https://review.coreboot.org/c/coreboot/+/84833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Gerrit-Change-Number: 84833 Gerrit-PatchSet: 20 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 10:33:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Uwe Poeche <uwe.poeche(a)siemens.com>

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coreboot-gerrit December 2024