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[M] Change in coreboot[main]: util/cbmem: Add a new option to parse self test report
by Kapil Porwal (Code Review) 12 Dec '24

12 Dec '24

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85573?usp=email ) Change subject: util/cbmem: Add a new option to parse self test report ...................................................................... util/cbmem: Add a new option to parse self test report This patch adds a new option 'cbmem -s' to parse and print the self test report to the cbmem command. The format of self test report is as below - +---------------|--------------+ | Self Test ID | Status | | < 32bit > | < 32bit > | -------------------------------- | xx | 0 (pass) | -------------------------------- | yy | 3 (fail) | -------------------------------- | | | -------------------------------- | | | | | | | | | | | | | | | -------------------------------- | 0 | 0 | +---------------|--------------+ BUG=b:233012780 TEST=Run the 'cbmem -s' command and verify the output Sample output: ``` $ cbmem -h usage: cbmem [-cCltTsLxVvh?] -c | --console: print cbmem console -1 | --oneboot: print cbmem console for last boot only -2 | --2ndtolast: print cbmem console for the boot that came before the last one only -B | --loglevel: maximum loglevel to print; prefix `+` (e.g. -B +INFO) to also print lines that have no level -C | --coverage: dump coverage information -l | --list: print cbmem table of contents -x | --hexdump: print hexdump of cbmem area -r | --rawdump ID: print rawdump of specific ID (in hex) of cbtable -t | --timestamps: print timestamp information -T | --parseable-timestamps: print parseable timestamps -S | --stacked-timestamps: print stacked timestamps (e.g. for flame graph tools) -s | --self-test-report: print self test report -a | --add-timestamp ID: append timestamp with ID -L | --tcpa-log print TPM log -V | --verbose: verbose (debugging) output -v | --version: print the version -h | --help: print this help $ cbmem -s ID Name Result 1 Intel_microcode_patch_loaded PASSED ``` Change-Id: I5f7233996cfb0b59f035811cc866475e26214739 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M util/cbmem/cbmem.c 1 file changed, 70 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85573/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 15b6770..7e711c8 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -22,6 +22,7 @@ #include <commonlib/bsd/ipchksum.h> #include <commonlib/bsd/tpm_log_defs.h> #include <commonlib/loglevel.h> +#include <commonlib/self_test.h> #include <commonlib/timestamp_serialized.h> #include <commonlib/tpm_log_serialized.h> #include <commonlib/coreboot_tables.h> @@ -1436,6 +1437,63 @@ } } +/* Function to get Test name from Test ID */ +static const char *st_get_name(uint32_t id) +{ + for (size_t i = 0; i < ARRAY_SIZE(st_ids); i++) { + if (st_ids[i].id == id) + return st_ids[i].name; + } + return NULL; +} + +static void dump_self_test_report(void) +{ + const uint8_t *table; + size_t offset; + + table = mapping_virt(&lbtable_mapping); + + if (table == NULL) + return; + + offset = 0; + + while (offset < mapping_size(&lbtable_mapping)) { + const struct lb_record *lbr; + struct lb_cbmem_entry lbe; + struct mapping st_mapping; + struct self_test_log *logs; + + lbr = (const void *)(table + offset); + offset += lbr->size; + + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; + + aligned_memcpy(&lbe, lbr, sizeof(lbe)); + + if (lbe.id != CBMEM_ID_SELF_TEST) + continue; + + logs = (struct self_test_log *)map_memory(&st_mapping, lbe.address, + lbe.entry_size); + if (logs == NULL) { + printf("Self test report not found!\n"); + return; + } + + printf("%-8s %-50s %-10s\n", "ID", "Name", "Result"); + while (logs->id != ST_INVALID_ID) { + printf("%-8x %-50s %-10s\n", logs->id, st_get_name(logs->id), + st_status_str[logs->status]); + logs++; + } + + unmap_memory(&st_mapping); + } +} + #define COVERAGE_MAGIC 0x584d4153 struct file { uint32_t magic; @@ -1536,7 +1594,7 @@ static void print_usage(const char *name, int exit_code) { - printf("usage: %s [-cCltTLxVvh?]\n", name); + printf("usage: %s [-cCltTsLxVvh?]\n", name); printf("\n" " -c | --console: print cbmem console\n" " -1 | --oneboot: print cbmem console for last boot only\n" @@ -1549,6 +1607,7 @@ " -t | --timestamps: print timestamp information\n" " -T | --parseable-timestamps: print parseable timestamps\n" " -S | --stacked-timestamps: print stacked timestamps (e.g. for flame graph tools)\n" + " -s | --self-test-report: print self test report\n" " -a | --add-timestamp ID: append timestamp with ID\n" " -L | --tcpa-log print TPM log\n" " -V | --verbose: verbose (debugging) output\n" @@ -1682,6 +1741,7 @@ int print_hexdump = 0; int print_rawdump = 0; int print_tcpa_log = 0; + int print_self_test_report = 0; enum timestamps_print_type timestamp_type = TIMESTAMPS_PRINT_NONE; enum console_print_type console_type = CONSOLE_PRINT_FULL; unsigned int rawdump_id = 0; @@ -1701,6 +1761,7 @@ {"timestamps", 0, 0, 't'}, {"parseable-timestamps", 0, 0, 'T'}, {"stacked-timestamps", 0, 0, 'S'}, + {"self-test-report", 0, 0, 's'}, {"add-timestamp", required_argument, 0, 'a'}, {"hexdump", 0, 0, 'x'}, {"rawdump", required_argument, 0, 'r'}, @@ -1709,7 +1770,7 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c12B:CltTSa:LxVvh?r:", + while ((opt = getopt_long(argc, argv, "c12B:CltTSsa:LxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': @@ -1762,6 +1823,10 @@ timestamp_type = TIMESTAMPS_PRINT_STACKED; print_defaults = 0; break; + case 's': + print_self_test_report = 1; + print_defaults = 0; + break; case 'a': print_defaults = 0; timestamp_id = timestamp_enum_name_to_id(optarg); @@ -1890,6 +1955,9 @@ if (print_tcpa_log) dump_tpm_log(); + if (print_self_test_report) + dump_self_test_report(); + unmap_memory(&lbtable_mapping); close(mem_fd); -- To view, visit https://review.coreboot.org/c/coreboot/+/85573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7233996cfb0b59f035811cc866475e26214739 Gerrit-Change-Number: 85573 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Implement regulator interface
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85563?usp=email ) Change subject: mb/google/rauru: Implement regulator interface ...................................................................... Patch Set 4: Code-Review+2 (2 comments) File src/mainboard/google/rauru/regulator.c: https://review.coreboot.org/c/coreboot/+/85563/comment/66318d66_a2fc7578?us… : PS2, Line 31: if (id == MT6373_VMCH) : mt6373_set_vmch_voltage(voltage_uv); : else if (id == MT6373_VMC) : mt6373_set_vmc_voltage(voltage_uv); > Use switch. Done https://review.coreboot.org/c/coreboot/+/85563/comment/e428aebd_15a53504?us… : PS2, Line 36: BIOS_WARNING > This should be an error, right? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cad68dbb2c5873c4e00066da18b1593b88ff499 Gerrit-Change-Number: 85563 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 16:41:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Matt DeVillier (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Patrick Rudolph. Matt DeVillier has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I haven't taken a look yet, I just cherry-picked the patch on top of my repo (which I synced yesterd […] must have been a transient error, as I reflashed with the patch and cbmem log is clean this time -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 16:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Matt DeVillier (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Patrick Rudolph. Matt DeVillier has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > That seems unrelated since the checksum is done on CMOS contents. […] I haven't taken a look yet, I just cherry-picked the patch on top of my repo (which I synced yesterday to test the stack issue). I flashed back to yesterday's build to confirm the error wasn't present there before reporting. -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 16:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Patrick Rudolph (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Matt DeVillier. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > with this patch, I now get the error: `ramtop_table invalid signature` which I didn't previously. […] That seems unrelated since the checksum is done on CMOS contents. I don't see how my patch could influence your CMOS. Do you have any idea? -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 15:56:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Matt DeVillier (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Patrick Rudolph. Matt DeVillier has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: with this patch, I now get the error: `ramtop_table invalid signature` which I didn't previously. Cometlake platform -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 15:02:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify devicetree for ALC712 codec
by Paul Menzel (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Pranava Y N, Subrata Banik, Weimin Wu. Paul Menzel has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85572?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify devicetree for ALC712 codec ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85572/comment/36448507_40dadf55?us… : PS2, Line 7: Modify devicetree for ALC712 codec Maybe: > Add ALC712 codec to devicetree https://review.coreboot.org/c/coreboot/+/85572/comment/1b0aacbd_c723c95d?us… : PS2, Line 10: Please add, where you got the devicetree values, like `bus_frequency_configs`, from. -- To view, visit https://review.coreboot.org/c/coreboot/+/85572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Gerrit-Change-Number: 85572 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 14:20:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify devicetree for ALC712 codec
by Weimin Wu (Code Review) 12 Dec '24

12 Dec '24

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85572?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify devicetree for ALC712 codec ...................................................................... mb/google/fatcat/var/felino: Modify devicetree for ALC712 codec Update device tree to support Realtek ALC712 codec. BUG=b:378629979 TEST=emerge-fatcat coreboot Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/felino/overridetree.cb 1 file changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85572/1 diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 2b34f03..ca3bfa1 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -193,10 +193,49 @@ chip drivers/intel/soundwire device generic 0 on chip drivers/soundwire/alc711 - # SoundWire Link 3 ID 1 + register "multilane.lane_mapping" = "{ + { + .lane = 1, + .direction = MASTER_LANE, + .connection.master_lane = 1 + }, + { + .lane = 2, + .direction = MASTER_LANE, + .connection.master_lane = 2 + }, + }" + register "audio_mode" = "{ + { + .bus_frequency_configs_count = 9, + .bus_frequency_configs = { + 9600 * KHz, + 4800 * KHz, + 2400 * KHz, + 12000 * KHz, + 6000 * KHz, + 3000 * KHz, + 12288 * KHz, + 6144 * KHz, + 3072 * KHz, + }, + /* Support 16 KHz to 192 KHz sampling frequency */ + .sampling_frequency_configs_count = 6, + .sampling_frequency_configs = { + 16 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 96 * KHz, + 192 * KHz + }, + }, + }" register "desc" = ""Headset Codec"" - device generic 3.1 on - end + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" + register "alc711_address.class" = "MIPI_CLASS_SDCA" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC712" + device generic 3.0 on end # SoundWire Link 3 ID 0 end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Gerrit-Change-Number: 85572 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Weimin Wu (Code Review) 12 Dec '24

12 Dec '24

Weimin Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... drivers/soundwire: Support Realtek ALC712 codec Update SoundWire driver to support ALC712 audio codec. reference datasheet: Realtek ALC712-VB-CG Rev. 0.24 BUG=b:378629979 TEST=emerge-fatcat coreboot Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/alc711/chip.h M src/include/mipi/ids.h 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85571/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Weimin Wu (Code Review) 12 Dec '24

12 Dec '24

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... drivers/soundwire: Support Realtek ALC712 codec Update SoundWire driver to support ALC712 audio codec. reference datasheet: Realtek ALC712-VB-CG Rev. 0.24 BUG=b:378629979 TEST=TBD Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/alc711/chip.h M src/include/mipi/ids.h 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85571/1 diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c index 83552c4..67941b9 100644 --- a/src/drivers/soundwire/alc711/alc711.c +++ b/src/drivers/soundwire/alc711/alc711.c @@ -10,6 +10,9 @@ #include "chip.h" +static struct soundwire_multilane alc711_multilane = { +}; + static struct soundwire_slave alc711_slave = { .wake_up_unavailable = false, .test_mode_supported = false, @@ -87,7 +90,8 @@ .port = 2, .source = &alc711_dp } - } + }, + .multilane = &alc711_multilane }; @@ -96,6 +100,7 @@ struct drivers_soundwire_alc711_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); struct acpi_dp *dsd; + size_t lane_mapping_count, audio_mode_count; if (!scope) return; @@ -112,6 +117,21 @@ acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); + /* Overlay multilane config, if provided. */ + lane_mapping_count = MIN(ARRAY_SIZE(config->multilane.lane_mapping), SOUNDWIRE_MAX_LANE); + if (lane_mapping_count > 0) { + alc711_multilane.lane_mapping_count = lane_mapping_count; + memcpy(&alc711_multilane.lane_mapping, &config->multilane.lane_mapping, + sizeof(struct soundwire_multilane_map) * lane_mapping_count); + } + + /* Overlay Audio Mode config, if provided. */ + audio_mode_count = MIN(ARRAY_SIZE(config->audio_mode), SOUNDWIRE_MAX_MODE); + if (audio_mode_count > 0) { + /* Currently only 1 audio mode is supported. */ + memcpy(&alc711_audio_mode, &config->audio_mode, sizeof(struct soundwire_audio_mode)); + } + dsd = acpi_dp_new_table("_DSD"); soundwire_gen_codec(dsd, &alc711_codec, NULL); acpi_dp_write(dsd); diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h index c628209..8b0230e 100644 --- a/src/drivers/soundwire/alc711/chip.h +++ b/src/drivers/soundwire/alc711/chip.h @@ -10,6 +10,8 @@ const char *name; const char *desc; struct soundwire_address alc711_address; + struct soundwire_audio_mode audio_mode[SOUNDWIRE_MAX_MODE]; + struct soundwire_multilane multilane; }; #endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */ diff --git a/src/include/mipi/ids.h b/src/include/mipi/ids.h index a194de1..fdd2d6a 100644 --- a/src/include/mipi/ids.h +++ b/src/include/mipi/ids.h @@ -21,6 +21,7 @@ #define MIPI_MFG_ID_REALTEK 0x025d #define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 #define MIPI_DEV_ID_REALTEK_ALC711 0x0711 +#define MIPI_DEV_ID_REALTEK_ALC712 0x0712 #define MIPI_DEV_ID_REALTEK_ALC721 0x0721 #define MIPI_DEV_ID_REALTEK_ALC722 0x0722 #define MIPI_DEV_ID_REALTEK_ALC1308 0x1308 -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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coreboot-gerrit December 2024