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Change subject: mb/google/brox/var/jubilant: Disable Tccold Handshake
......................................................................
Patch Set 3: Code-Review+2
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Change subject: arch/x86: Add breakpoint to stack canary
......................................................................
Patch Set 20:
(1 comment)
Patchset:
PS20:
> Tested on Xeon-SP skylake. […]
I'm also seeing stack corruption detected on a CML chromebook at the start of romstage (haven't tested others yet)
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Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85562/comment/b46f7b2d_b8a4355e?us… :
PS3, Line 7: Fix regression
> Maybe: […]
It does fix a regression
https://review.coreboot.org/c/coreboot/+/85562/comment/2a839d5e_fbb95f42?us… :
PS3, Line 11:
> Please paste the Linux log error.
There are too many.
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Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85562/comment/072cbf4f_3c73fc88?us… :
PS3, Line 7: Fix regression
Maybe:
> Sync domain ACPI names in DSDT and SSDT
https://review.coreboot.org/c/coreboot/+/85562/comment/d24b0fd1_7768dd6d?us… :
PS3, Line 11:
Please paste the Linux log error.
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Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85537/comment/89bc0511_f8f05713?us… :
PS5, Line 9: The boot time is estimated to increase by 50ms.
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/85537/comment/361e760f_a3eef1f3?us… :
PS5, Line 9: Uldrenite supports the WWAN 5G device and uses variant.c to handle the power-on sequence according to the Rolling Wireless_RW350R-GL_Hardware Guide_Generic_V1.1. The boot time is estimated to increase by 50ms.
:
: At this stage, we do not yet have the board or key parts for verification. However, I still need to merge the CL to ensure that the WWAN functionality works. Once the motherboard is available, I will make adjustments to optimize and reduce the boot time.
> Please re-flow for 72 characters per line.
Done
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Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression
......................................................................
soc/intel/xeon_sp/spr/acpi: Fix regression
Fix regression introduced in commit t177bb5e9b9789cc830f504815e711973190def4e
("soc/intel/xeon_sp: Revise IIO domain ACPI name encoding").
Ensure domain ACPI names in the DSDT are in sync with SSDT ACPI names.
Fixes PCI devices not discovered on socket 1-3.
TEST: Booted in ibm/sbp1 and found all PCI devices working, no errors
in dmesg are shown.
Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/uncore.asl
3 files changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85562/3
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Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
......................................................................
mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
Uldrenite supports the WWAN 5G device and uses variant.c to handle the
power-on sequence according to the Rolling Wireless_RW350R-GL_Hardware
Guide_Generic_V1.1. Due to no hardware access, the boot time is
estimated to increase by 50 ms.
At this stage, we do not yet have the board or key parts for
verification. However, I still need to merge the CL to ensure that the
WWAN functionality works. Once the motherboard is available, I will make
adjustments to optimize and reduce the boot time.
BUG=b:381393809, b:383212261
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/uldrenite/Makefile.mk
A src/mainboard/google/brya/variants/uldrenite/variant.c
2 files changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85537/6
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Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression
......................................................................
soc/intel/xeon_sp/spr/acpi: Fix regression
Fix regression introduced in 177bb5e9b9789cc830f504815e711973190def4e
"soc/intel/xeon_sp: Revise IIO domain ACPI name encoding".
Ensure domain ACPI names in the DSDT are in sync with SSDT ACPI names.
Fixes PCI devices not discovered on socket 1-3.
TEST: Booted in ibm/sbp1 and found all PCI devices working, no errors
in dmesg are shown.
Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/uncore.asl
3 files changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85562/2
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Change subject: arch/x86: Add breakpoint to stack canary
......................................................................
Patch Set 20:
(1 comment)
Patchset:
PS20:
did you verify that this won't break option ROM execution in real mode, SoC support using FSP 1.1, and SoC support using the two binaryPI cases?
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