coreboot-gerrit December 2024

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[S] Change in coreboot[main]: drivers/usb/intel_bluetooth: Add GBTR Method
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84992?usp=email ) Change subject: drivers/usb/intel_bluetooth: Add GBTR Method ...................................................................... drivers/usb/intel_bluetooth: Add GBTR Method Add GBTR Method, which gets the state of the RF Kill pin. Unlike the VGPIO, this can be used for both CNVi and full PCI wireless cards. Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84992 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/drivers/usb/acpi/intel_bluetooth.c M src/soc/intel/common/block/cnvi/cnvi.c 2 files changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Sudsgaard: Looks good to me, approved diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c index 56f31ae..4cefcf2 100644 --- a/src/drivers/usb/acpi/intel_bluetooth.c +++ b/src/drivers/usb/acpi/intel_bluetooth.c @@ -335,5 +335,22 @@ } acpigen_pop_len(); +/* + * Method (GBTR, 0, NotSerialized) + * { + * Return (GTXS (reset_gpio)) + * } + */ + acpigen_write_method("GBTR", 0); + { + if (reset_gpio) { + acpigen_soc_get_tx_gpio(reset_gpio); + acpigen_write_return_op(LOCAL0_OP); + } else { + acpigen_write_return_op(0); + } + } + acpigen_pop_len(); + acpigen_pop_len(); } diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index d50913f..93f0cae 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -129,7 +129,7 @@ * If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero)) * { * Local2 = Zero - * If ((\_SB.PCI0.GBTE() == One)) + * If ((\_SB.PCI0.GBTR() == One)) * { * \_SB.PCI0.BTRK (Zero) * Sleep (105) @@ -209,7 +209,7 @@ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); { acpigen_write_store_int_to_op(0, LOCAL2_OP); - acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTE", 1); + acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTR", 1); { acpigen_emit_namestring("\\_SB.PCI0.BTRK"); acpigen_emit_byte(0); -- To view, visit https://review.coreboot.org/c/coreboot/+/84992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c Gerrit-Change-Number: 84992 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/common/cnvi: Fix GBTE path in comment
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84991?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/common/cnvi: Fix GBTE path in comment ...................................................................... soc/intel/common/cnvi: Fix GBTE path in comment Change-Id: If1e5d70a23c2a139ef3ee4970db2e5d528c2661e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84991 Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nicholas Sudsgaard: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index b995ef3..d50913f 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -129,7 +129,7 @@ * If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero)) * { * Local2 = Zero - * If ((GBTE() == One)) + * If ((\_SB.PCI0.GBTE() == One)) * { * \_SB.PCI0.BTRK (Zero) * Sleep (105) -- To view, visit https://review.coreboot.org/c/coreboot/+/84991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e5d70a23c2a139ef3ee4970db2e5d528c2661e Gerrit-Change-Number: 84991 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84990?usp=email ) Change subject: drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0 ...................................................................... drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0 Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly access it. Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990 Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/intel_bluetooth.c M src/drivers/usb/acpi/usb_acpi.c M src/soc/intel/common/block/cnvi/cnvi.c 4 files changed, 38 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Sudsgaard: Looks good to me, approved diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index a27ce44..f5edba4 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -91,6 +91,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, bool audio_offload); -void acpi_device_intel_bt_common(unsigned int enable_gpio); +void acpi_device_intel_bt_common(unsigned int enable_gpio, + unsigned int reset_gpio); #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c index 978d6ee..56f31ae 100644 --- a/src/drivers/usb/acpi/intel_bluetooth.c +++ b/src/drivers/usb/acpi/intel_bluetooth.c @@ -117,9 +117,9 @@ * Local0 = Acquire (\_SB.PCI0.CNMT, 1000) * If ((Local0 == Zero)) * { - * BTRK (Zero) + * \_SB.PCI0.BTRK (Zero) * Sleep (RDLY) - * BTRK (One) + * \_SB.PCI0.BTRK (One) * Sleep (RDLY) * Release (\_SB.PCI0.CNMT) } @@ -169,13 +169,13 @@ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); { - acpigen_emit_namestring("BTRK"); + acpigen_emit_namestring("\\_SB.PCI0.BTRK"); acpigen_emit_byte(0); acpigen_emit_ext_op(SLEEP_OP); acpigen_emit_namestring("RDLY"); - acpigen_emit_namestring("BTRK"); + acpigen_emit_namestring("\\_SB.PCI0.BTRK"); acpigen_emit_byte(1); acpigen_emit_ext_op(SLEEP_OP); @@ -191,31 +191,6 @@ acpigen_write_power_res_end(); /* - * Method (BTRK, 1, Serialized) - * { - * If (Arg0 == 1) - * { - * STXS (reset_gpio) - * } Else { - * CTXS (reset_gpio) - * } - * } - */ - acpigen_write_method_serialized("BTRK", 1); - { - acpigen_write_if_lequal_op_int(ARG0_OP, 1); - { - acpigen_soc_set_tx_gpio(reset_gpio); - } - acpigen_write_else(); - { - acpigen_soc_clear_tx_gpio(reset_gpio); - } - acpigen_pop_len(); - } - acpigen_pop_len(); - -/* * Name (_PRR, Package (0x01) * { * BTRT @@ -283,7 +258,7 @@ acpigen_pop_len(); } -void acpi_device_intel_bt_common(unsigned int enable_gpio) +void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gpio) { acpigen_write_scope("\\_SB.PCI0"); /* @@ -335,5 +310,30 @@ } acpigen_pop_len(); +/* + * Method (BTRK, 1, Serialized) + * { + * If (Arg0 == 1) + * { + * STXS (reset_gpio) + * } Else { + * CTXS (reset_gpio) + * } + * } + */ + acpigen_write_method_serialized("BTRK", 1); + { + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + { + acpigen_soc_set_tx_gpio(reset_gpio); + } + acpigen_write_else(); + { + acpigen_soc_clear_tx_gpio(reset_gpio); + } + acpigen_pop_len(); + } + acpigen_pop_len(); + acpigen_pop_len(); } diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 8960e3d..6408a88 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -119,7 +119,8 @@ * other code to access it i.e. CNVi driver. */ if (config->is_intel_bluetooth) - acpi_device_intel_bt_common(config->enable_gpio.pins[0]); + acpi_device_intel_bt_common(config->enable_gpio.pins[0], + config->reset_gpio.pins[0]); printk(BIOS_INFO, "%s: %s at %s\n", path, config->desc ? : dev->chip_ops->name, dev_path(dev)); diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 591dfd8..b995ef3 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -131,7 +131,7 @@ * Local2 = Zero * If ((GBTE() == One)) * { - * BTRK (Zero) + * \_SB.PCI0.BTRK (Zero) * Sleep (105) * Local2 = One * } @@ -143,7 +143,7 @@ * PRRS = CNVI_PLDR_COMPLETE * If ((Local2 == One)) * { - * BTRK (One) + * \_SB.PCI0.BTRK (One) * Sleep (105) * } * } @@ -211,7 +211,7 @@ acpigen_write_store_int_to_op(0, LOCAL2_OP); acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTE", 1); { - acpigen_emit_namestring("BTRK"); + acpigen_emit_namestring("\\_SB.PCI0.BTRK"); acpigen_emit_byte(0); acpigen_write_sleep(105); @@ -251,7 +251,7 @@ acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); { - acpigen_emit_namestring("BTRK"); + acpigen_emit_namestring("\\_SB.PCI0.BTRK"); acpigen_emit_byte(1); acpigen_write_sleep(105); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce Gerrit-Change-Number: 84990 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: drivers/usb/intel_bluetooth: Fix GBTE to return Local0
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84989?usp=email ) Change subject: drivers/usb/intel_bluetooth: Fix GBTE to return Local0 ...................................................................... drivers/usb/intel_bluetooth: Fix GBTE to return Local0 `acpigen_soc_get_tx_gpio` will put the result into Local0, rather than emitting it as a byte so adjust the function accordingly. Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84989 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/drivers/usb/acpi/intel_bluetooth.c 1 file changed, 5 insertions(+), 4 deletions(-) Approvals: Nicholas Sudsgaard: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c index aa3b794..978d6ee 100644 --- a/src/drivers/usb/acpi/intel_bluetooth.c +++ b/src/drivers/usb/acpi/intel_bluetooth.c @@ -326,11 +326,12 @@ */ acpigen_write_method("GBTE", 0); { - acpigen_emit_byte(RETURN_OP); - if (enable_gpio) + if (enable_gpio) { acpigen_soc_get_tx_gpio(enable_gpio); - else - acpigen_emit_byte(0); + acpigen_write_return_op(LOCAL0_OP); + } else { + acpigen_write_return_integer(0); + } } acpigen_pop_len(); -- To view, visit https://review.coreboot.org/c/coreboot/+/84989?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9 Gerrit-Change-Number: 84989 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: drivers/usb/intel_bluetooth: Change the Power Resource to S0
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84988?usp=email ) Change subject: drivers/usb/intel_bluetooth: Change the Power Resource to S0 ...................................................................... drivers/usb/intel_bluetooth: Change the Power Resource to S0 This resource is applicable to S0, as it can be used to reset the wireless and for RTD3, so change it from S5. Change-Id: I9ae710ef452c717ec414324d2847bf3218fd62d3 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/drivers/usb/acpi/intel_bluetooth.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Sudsgaard: Looks good to me, approved diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c index 90f1636..aa3b794 100644 --- a/src/drivers/usb/acpi/intel_bluetooth.c +++ b/src/drivers/usb/acpi/intel_bluetooth.c @@ -98,7 +98,7 @@ acpigen_write_dsm_uuid_arr(uuid_callbacks, ARRAY_SIZE(uuid_callbacks)); /* - * PowerResource (BTRT, 0x05, 0x0000) + * PowerResource (BTRT, 0, 0) * { * Method (_STA, 0, NotSerialized) * { @@ -126,7 +126,7 @@ * } * } */ - acpigen_write_power_res("BTRT", 5, 0, NULL, 0); + acpigen_write_power_res("BTRT", 0, 0, NULL, 0); { acpigen_write_method("_STA", 0); { -- To view, visit https://review.coreboot.org/c/coreboot/+/84988?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae710ef452c717ec414324d2847bf3218fd62d3 Gerrit-Change-Number: 84988 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Merge SKX and CPX
by Patrick Rudolph (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85557?usp=email to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Merge SKX and CPX ...................................................................... soc/intel/xeon_sp: Merge SKX and CPX Start merging SKX and CPX into one codebase: - Create a new 14nm folder - Add new Kconfig: SOC_INTEL_XEON_SP_14NM - Add shared Kconfig settings - Add combined CPU driver - Add combined ACPI and romstage code TODO: Merge additional code from skx/cpx folders. TEST: Still boots on ocp/tiogapass. Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/intel/cedarisland_crb/dsdt.asl M src/mainboard/ocp/deltalake/dsdt.asl M src/mainboard/ocp/tiogapass/dsdt.asl A src/soc/intel/xeon_sp/14nm/Kconfig A src/soc/intel/xeon_sp/14nm/Makefile.mk R src/soc/intel/xeon_sp/14nm/acpi/gpio.asl R src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl R src/soc/intel/xeon_sp/14nm/acpi/pch.asl R src/soc/intel/xeon_sp/14nm/acpi/pch_irq.asl R src/soc/intel/xeon_sp/14nm/acpi/pci_irqs.asl R src/soc/intel/xeon_sp/14nm/acpi/southcluster.asl R src/soc/intel/xeon_sp/14nm/acpi/uncore.asl R src/soc/intel/xeon_sp/14nm/acpi/uncore_irq.asl R src/soc/intel/xeon_sp/14nm/cpu.c R src/soc/intel/xeon_sp/14nm/iio_ioapic.c A src/soc/intel/xeon_sp/14nm/romstage.c R src/soc/intel/xeon_sp/14nm/soc_acpi.c M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.mk D src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/skx/romstage.c D src/soc/intel/xeon_sp/skx/soc_acpi.c 26 files changed, 179 insertions(+), 534 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85557/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Gerrit-Change-Number: 85557 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Use \_SB.POSC on all platforms
by Patrick Rudolph (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85559?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Use \_SB.POSC on all platforms ...................................................................... soc/intel/xeon_sp: Use \_SB.POSC on all platforms Reduce ACPI code size by using the existing \_SB.POSC instead of duplicating the method in every PCI/CXL host bridge. TEST: On ocp/tiogapass the OS still gets granted the PCIe capabilities as previously through _OSC. Reduces DSDT size by 1366 bytes. Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl 4 files changed, 9 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85559/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Gerrit-Change-Number: 85559 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp/acpi: Whitespace fixes
by Paul Menzel (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85558?usp=email ) Change subject: soc/intel/xeon_sp/acpi: Whitespace fixes ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85558/comment/8afc807d_ddd5558d?us… : PS2, Line 7: Whitespace fixes Use a statement: > Convert spaces to tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/85558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0361b93bea44bb85477a3323198da612234397e8 Gerrit-Change-Number: 85558 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 13:27:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by Paul Menzel (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85537/comment/6c7635ba_db5d3b32?us… : PS3, Line 11: > b/381393809#comment1 Rolling Wireless_RW350R-GL_Hardware Guide_Generic_V1.1. […] Please add it. https://review.coreboot.org/c/coreboot/+/85537/comment/a6b917d4_67b2bb29?us… : PS3, Line 14: TEST=emerge-nissa coreboot > The boot time is estimated to increase by 50ms. […] Thank you for the confirmation. Maybe add your answer to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 13:21:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Patrick Rudolph (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Morgan Jang, Paul Menzel, Shuo Liu, yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email ) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85492/comment/4726171a_f381bb65?us… : PS5, Line 17: Once GPP_F4 is low IPMI communication over the KCS is also : working on ocp/tiogapass. : > Paste the new log message with the elapsed time? Done File src/mainboard/ocp/tiogapass/romstage.c: https://review.coreboot.org/c/coreboot/+/85492/comment/e86a0760_42825db5?us… : PS5, Line 61: timeout > Add the unit to the name? Done https://review.coreboot.org/c/coreboot/+/85492/comment/0c46ce6b_a9fb54a7?us… : PS5, Line 70: %ldms > Add a space before the unit? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 13:17:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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