coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Disable Tccold Handshake
by Ren Kuo (Code Review) 11 Dec '24

11 Dec '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85555?usp=email ) Change subject: mb/google/brox/var/jubilant: Disable Tccold Handshake ...................................................................... mb/google/brox/var/jubilant: Disable Tccold Handshake The patch disables Tccold Handshake to prevent possible display flicker issue for jubilant board. Please refer to Intel doc#723158 for more information. BUG=b: BRANCH=firmware-brox-16080.B TEST=Boot to OS on jubilant, verify the display is without flicker. Change-Id: I4f22067b81fa1b1b9addd7d1f49de59136d221c0 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85555/1 diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 4e554ab..afcfc7a 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -21,6 +21,10 @@ chip soc/intel/alderlake register "platform_pmax" = "208" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "disable_dynamic_tccold_handshake" = "true" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f22067b81fa1b1b9addd7d1f49de59136d221c0 Gerrit-Change-Number: 85555 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED
by Keith Hui (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Bill XIE, Paul Menzel. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82556?usp=email ) Change subject: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED ...................................................................... Patch Set 2: (1 comment) File src/mainboard/asus/p8x7x-series/Kconfig: https://review.coreboot.org/c/coreboot/+/82556/comment/197d6c0b_09a11bb9?us… : PS2, Line 66: If power LED doesn't blink when entering S3 suspend, try setting this. > It’d be great if you elaborate and added the information from the commit message regarding the GPIOs […] I really am not sure if this info can be deduced from running system or ACPI. I checked the entire family of boards, at least those I can get a boardview for, and the power LED only goes to either GPIO 8 or 27 - I haven't seen a third GPIO used. And the only consequence of getting this wrong is that the power LED doesn't blink on suspend, so I'm content with "if it doesn't work, try this." Honestly though, after seeing what went down with Malibal, I also think coreboot's documentation needs a major revamp, to the point that a CS undergrad who knows where to look can get started with working on coreboot. However that is a much larger undertaking than one patch for one board family. -- To view, visit https://review.coreboot.org/c/coreboot/+/82556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30 Gerrit-Change-Number: 82556 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 05:04:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 15: (4 comments) File src/soc/mediatek/mt8196/include/soc/mt8196_sspm.h: https://review.coreboot.org/c/coreboot/+/85516/comment/bf1adafe_77cd4214?us… : PS11, Line 6: #include <soc/addressmap.h> : : #define SSPM_SRAM_CON (SPM_BASE + 0xEE4) : #define SPM_PRJ_CODE 0xB160001 : #define SSPM_SRAM_SLEEP_B 0x10 : #define SSPM_SRAM_ISOINT_B 0x2 > Move to `mt8196/sspm_sram.c`. Done https://review.coreboot.org/c/coreboot/+/85516/comment/ca5e3265_3b912522?us… : PS11, Line 13: void sspm_enable_sram(void); > 1. Move to `common/soc/include/sspm.h` […] Done File src/soc/mediatek/mt8196/sspm.c: PS11: > rename to sspm_sram. […] Done https://review.coreboot.org/c/coreboot/+/85516/comment/b7babe93_0797c428?us… : PS11, Line 4: mt8196_sspm > sspm. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 04:58:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6373 driver
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85129?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6373 driver ...................................................................... Patch Set 33: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85129/comment/05678293_210a31cf?us… : PS30, Line 9: mt6373 > MT6373 Done https://review.coreboot.org/c/coreboot/+/85129/comment/2b31bde8_096efdcb?us… : PS30, Line 9: add > Add Done https://review.coreboot.org/c/coreboot/+/85129/comment/8b85c6c7_096f9408?us… : PS30, Line 10: api > API Done https://review.coreboot.org/c/coreboot/+/85129/comment/8e6ac096_caea7cc2?us… : PS30, Line 10: SD power > powering on SD card Done https://review.coreboot.org/c/coreboot/+/85129/comment/661e61d1_2df8cf14?us… : PS30, Line 11: add implement interface for vcn33_3 > Can we just say `Add regulator API for VCN33_3` ? Done https://review.coreboot.org/c/coreboot/+/85129/comment/bbc6b796_8bda7852?us… : PS30, Line 12: enable > Enable Done https://review.coreboot.org/c/coreboot/+/85129/comment/4a4c2a38_d024aea6?us… : PS30, Line 13: api > API Done https://review.coreboot.org/c/coreboot/+/85129/comment/8c5f3aa8_86450cb4?us… : PS30, Line 13: 5. add MT6373 LDO enable api > Add Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 33 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 04:56:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yu-Ping Wu. Hello Hung-Te Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85516?usp=email to look at the new patch set (#15). Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... soc/mediatek/mt8196: Initialize SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 20 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314 mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes) TEST=can see the sspm logs. BUG=b:372173976 Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/sspm.h M src/soc/mediatek/common/sspm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/sspm_sram.c 7 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85516/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yu-Ping Wu. Hello Hung-Te Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85516?usp=email to look at the new patch set (#14). Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... soc/mediatek/mt8196: Initialize SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 20 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314 mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes) TEST=can see the sspm logs. BUG=b:372173976 Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/sspm.h M src/soc/mediatek/common/sspm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/soc.c 6 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85516/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6373 driver
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85129?usp=email to look at the new patch set (#31). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIC MT6373 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6373 driver 1. Add MT6373 driver in soc folder 2 Add regulator API for powering on SD card 3. Add regulator API for VCN33_3 4. Enable vcn33_3 & set vcn33_3 3.3v 5. Add MT6373 LDO enable API TEST=build pass, check boot log with: [INFO ] mt6373_init_setting done [INFO ] pmic_protect_key_setting done BUG=b:317009620 Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6373.h A src/soc/mediatek/common/mt6373.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6373.c 4 files changed, 714 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85129/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 31 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yu-Ping Wu. Hello Hung-Te Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85516?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... soc/mediatek/mt8196: Initialize SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 20 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314 mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes) TEST=can see the sspm logs. BUG=b:372173976 Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/sspm.h M src/soc/mediatek/common/sspm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/soc.c 6 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85516/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: nb/intel/i440bx: Drop self-specific debugging macros
by Keith Hui (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Felix Singer. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/78786?usp=email ) Change subject: nb/intel/i440bx: Drop self-specific debugging macros ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78786/comment/8c71adef_d50f6b61?us… : PS3, Line 10: for raminit debug messages. > Even if it looks reasonable, I'm missing the "why" here. I was kinda late to the party on printram(). Now that I know about it, there' no reason not to use it. Both macros, as mentioned in the patch title, are i440bx exclusive. If there is an alternative, I'd rather rid myself of them. -- To view, visit https://review.coreboot.org/c/coreboot/+/78786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I685a2f1f38c1afab6a08ff9de4bf82c9061aebec Gerrit-Change-Number: 78786 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Wed, 11 Dec 2024 04:50:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: mb/google/brya/var/uldrenite: Add HDA verb tables
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85448?usp=email ) Change subject: mb/google/brya/var/uldrenite: Add HDA verb tables ...................................................................... mb/google/brya/var/uldrenite: Add HDA verb tables We use ALC3204 as HDA codec on uldrenite, add the verb table by Realtek. BUG=b:374203133 TEST=emerge-nissa coreboot Change-Id: Ie9d0e17e1ab13adc8aea0d5bcbbe44785a137d7b Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85448 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- A src/mainboard/google/brya/variants/uldrenite/hda_verb.c 1 file changed, 155 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/hda_verb.c b/src/mainboard/google/brya/variants/uldrenite/hda_verb.c new file mode 100644 index 0000000..08e1fb8 --- /dev/null +++ b/src/mainboard/google/brya/variants/uldrenite/hda_verb.c @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0236, //Codec Vendor / Device ID: Realtek ALC3204 + 0x10280D76, // Subsystem ID + 0x00000021, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10280D76), + + /* Pin Widget Verb Table */ + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x02a11030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), + + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + /* ALC3204 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* ALC3204 default-2 (Tco) */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + /* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain) + * + Combo Jack TRS setting */ + 0x02050038, + 0x02043901, + 0x02050045, + 0x02045089, + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + /* ALC3204 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* ALC3204 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A4C, + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* JD2 */ + 0x0205000B, + 0x02047778, + 0x0205000B, + 0x02047778, + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, +}; + +const u32 pc_beep_verbs[] = { + //=== PCBeep pass through to NID14 for ePSA test-1 + 0x02050036, + 0x02047717, + 0x02050036, + 0x02047717, + //=== PCBeep pass through to NID14 for ePSA test-2 + 0x01470740, + 0x0143B000, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/85448?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9d0e17e1ab13adc8aea0d5bcbbe44785a137d7b Gerrit-Change-Number: 85448 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit December 2024