coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve IRQ routing for Gen6
by Shuo Liu (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve IRQ routing for Gen6 ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/xeon_sp/lpc_gen6.c: https://review.coreboot.org/c/coreboot/+/85153/comment/772c7f8b_c54babb8?us… : PS10, Line 50: uint8_t int_line = (pirq_rout & 0x80) ? pirq - PIRQ_A + PCH_IRQ16 : pirq_rout & 0xf; > You can use `pirq_idx()` here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 12:41:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve IRQ routing for Gen6
by Shuo Liu (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85153?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Lean Sheng Tan, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Improve IRQ routing for Gen6 ...................................................................... soc/intel/xeon_sp: Improve IRQ routing for Gen6 1. Route IRQ for on-chip end-points only. 2. Route IRQ based on FSP programmed end-point device ID <-> PIRQ mapping. TESTED=Build and boot on intel/avenuecity CRB Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/irq.h M src/soc/intel/xeon_sp/lpc_gen6.c 2 files changed, 52 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/85153/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Jérémy Compostella. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Program the right power_limits_config entry ...................................................................... Patch Set 12: -Code-Review (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c: https://review.coreboot.org/c/coreboot/+/85244/comment/4a8e7473_87143626?us… : PS12, Line 2: please add `#include <chip.h>` -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 12 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 12:16:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Kapil Porwal. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email ) Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/85449/comment/3f0af732_283ae69c?us… : PS4, Line 152: 0x380 how generic is this address ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 12:11:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO.
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85547?usp=email ) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO. ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85547/comment/c0ef8767_07588574?us… : PS1, Line 11: # EC memory map range is 0x900-0x9ff this comment is stale now -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 12:10:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Xiwen Shao, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+1 by Xiwen Shao, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=Build pass, When we encounter a bus hang and HW watchdog triggers a reset to the platform, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 4 files changed, 175 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85516?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... soc/mediatek/mt8196: Initialize SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 20 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314 mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes) TEST=can see the sspm logs. BUG=b:372173976 Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mt8196_sspm.h M src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/sspm.c 6 files changed, 41 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85516/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Elyes Haouas, Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Guangjie Song, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84497?usp=email to look at the new patch set (#40). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... soc/mediatek/mt8196: Add mtcmos init support Add mtcmos init code and APIs for controlling power domain. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h A src/soc/mediatek/mt8196/mtcmos.c 5 files changed, 839 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84497/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 40 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 12: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84929/comment/f48f9b9f_d72bd783?us… : PS12, Line 10: hen bus move to previous line https://review.coreboot.org/c/coreboot/+/84929/comment/813c4ee7_ffb50772?us… : PS12, Line 13: hw HW or hwardware https://review.coreboot.org/c/coreboot/+/84929/comment/c5a476b7_56115df2?us… : PS12, Line 13: build Build https://review.coreboot.org/c/coreboot/+/84929/comment/33843053_79a68a70?us… : PS12, Line 14: causes the platform to restart triggers a reset to the platform, https://review.coreboot.org/c/coreboot/+/84929/comment/3891cc71_4f1ac844?us… : PS12, Line 19: has a bus timeout. move to previous line. File src/soc/mediatek/mt8196/bootblock.c: https://review.coreboot.org/c/coreboot/+/84929/comment/668331ba_93b398a9?us… : PS12, Line 8: tracker_common tracker.h File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/84929/comment/dc777770_fe69439b?us… : PS12, Line 49: 78K) The change is probably no longer needed. File src/soc/mediatek/mt8196/include/soc/tracker.h: https://review.coreboot.org/c/coreboot/+/84929/comment/0fed6093_a6edb771?us… : PS12, Line 5: #include <soc/tracker_common.h> File src/soc/mediatek/mt8196/tracker.c: https://review.coreboot.org/c/coreboot/+/84929/comment/c89a143d_961c0e44?us… : PS12, Line 8: #include <soc/tracker_common.h> remove https://review.coreboot.org/c/coreboot/+/84929/comment/786993ee_03d51afc?us… : PS12, Line 71: ( parentheses is not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 11:27:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Ren Kuo. Paul Menzel has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85533/comment/310f798b_e929ea71?us… : PS6, Line 9: Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s. > Please reflow for 72 characters per line. Too late. (If you use the Gerrit editor some checks are not run by the build bots.) -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 11:22:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit December 2024