coreboot-gerrit December 2024

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... Patch Set 18: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85126/comment/6be493f7_baca6d33?us… : PS17, Line 13: TEST=build pass > Done sorry, not done -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 09:43:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... Patch Set 18: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85126/comment/7207dc4f_a27dc841?us… : PS17, Line 13: TEST=build pass > Were you able to run-time test it? Maybe print the new log messages. Done File src/soc/mediatek/mt8196/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/85126/comment/84f610df_92f5e823?us… : PS17, Line 190: int > size_t Done https://review.coreboot.org/c/coreboot/+/85126/comment/f14786de_a50d48bc?us… : PS17, Line 345: spmi > SPMI Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 09:43:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85128?usp=email to look at the new patch set (#24). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6363 ADC driver Add MT6363 AUXADC driver support, which is essential for handling the Analog-to-Digital Conversion (ADC) functionalities in the MT8196 SoC. TEST=build pass BUG=b:317009620 Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6363_sdmadc.h A src/soc/mediatek/common/mt6363_sdmadc.c M src/soc/mediatek/mt8196/Makefile.mk 3 files changed, 203 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85128/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 24 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC mt6373 driver
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85129?usp=email to look at the new patch set (#25). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIC mt6373 driver ...................................................................... soc/mediatek/mt8196: Add PMIC mt6373 driver 1. add mt6373 driver in soc folder 2. add regulator api for SD power 3. add implement interface for vcn33_3 4. enable vcn33_3 & set vcn33_3 3.3v 5. add MT6373 LDO enable api TEST=build pass BUG=b:317009620 Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6373.h A src/soc/mediatek/common/mt6373.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6373.c 4 files changed, 714 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85129/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 25 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85126?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF. TEST=build pass BUG=b:317009620 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,729 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: haswell NRI: Post-process selected timings
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64185?usp=email ) Change subject: haswell NRI: Post-process selected timings ...................................................................... haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate the values for tREFI and tXP. Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64185 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk A src/northbridge/intel/haswell/native_raminit/lookup_timings.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c 5 files changed, 172 insertions(+), 0 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index c125d84..2769e0b 100644 --- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk +++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later +romstage-y += lookup_timings.c romstage-y += init_mpll.c romstage-y += io_comp_control.c romstage-y += raminit_main.c diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c new file mode 100644 index 0000000..8b81c7c --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <commonlib/bsd/clamp.h> +#include <types.h> + +#include "raminit_native.h" + +struct timing_lookup { + uint32_t clock; + uint32_t value; +}; + +static uint32_t lookup_timing( + const uint32_t mem_clock_mhz, + const struct timing_lookup *const lookup, + const size_t length) +{ + /* Fall back to the last index */ + size_t i; + for (i = 0; i < length - 1; i++) { + /* Account for imprecise frequency values */ + if ((mem_clock_mhz - 5) <= lookup[i].clock) + break; + } + return lookup[i].value; +} + +static const uint32_t fmax = UINT32_MAX; + +uint8_t get_tCWL(const uint32_t mem_clock_mhz) +{ + const struct timing_lookup lut[] = { + { 400, 5 }, + { 533, 6 }, + { 666, 7 }, + { 800, 8 }, + { 933, 9 }, + { 1066, 10 }, + { 1200, 11 }, + { fmax, 12 }, + }; + return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut)); +} + +/* tREFI = 7800 ns * DDR MHz */ +uint32_t get_tREFI(const uint32_t mem_clock_mhz) +{ + return (mem_clock_mhz * 7800) / 1000; +} + +uint32_t get_tXP(const uint32_t mem_clock_mhz) +{ + const struct timing_lookup lut[] = { + { 400, 3 }, + { 666, 4 }, + { 800, 5 }, + { 933, 6 }, + { 1066, 7 }, + { fmax, 8 }, + }; + return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut)); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index ab462e0..28a7895 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -22,6 +22,7 @@ static const struct task_entry cold_boot[] = { { collect_spd_info, true, "PROCSPD", }, { initialise_mpll, true, "INITMPLL", }, + { convert_timings, true, "CONVTIM", }, }; /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index 15a1550..e0ebd3a 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -79,6 +79,9 @@ uint32_t tCWL; uint32_t tCMD; + uint32_t tREFI; + uint32_t tXP; + uint8_t lanes; /* 8 or 9 */ uint8_t chanmap; uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */ @@ -97,7 +100,12 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl); enum raminit_status initialise_mpll(struct sysinfo *ctrl); +enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status wait_for_first_rcomp(void); +uint8_t get_tCWL(uint32_t mem_clock_mhz); +uint32_t get_tREFI(uint32_t mem_clock_mhz); +uint32_t get_tXP(uint32_t mem_clock_mhz); + #endif diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c index a422591..556f566 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -207,3 +207,103 @@ get_spd_data(ctrl); return find_common_spd_parameters(ctrl); } + +#define MIN_CWL 5 +#define MAX_CWL 12 + +/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */ +enum raminit_status convert_timings(struct sysinfo *ctrl) +{ + /* + * Obtain all required timing values, in DCLKs. + */ + + /* Convert primary timings from nanoseconds to DCLKs */ + ctrl->tAA = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); + ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); + ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); + ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); + ctrl->tRC = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK); + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); + ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); + ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); + ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); + ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); + ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK); + + /* Constrain primary timings to hardware limits */ + /** TODO: complain when clamping? **/ + ctrl->tAA = clamp_u32(4, ctrl->tAA, 24); + ctrl->tWR = clamp_u32(5, ctrl->tWR, 16); + ctrl->tRCD = clamp_u32(4, ctrl->tRCD, 20); + ctrl->tRRD = clamp_u32(4, ctrl->tRRD, 65535); + ctrl->tRP = clamp_u32(4, ctrl->tRP, 15); + ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40); + ctrl->tRC = clamp_u32(1, ctrl->tRC, 4095); + ctrl->tRFC = clamp_u32(1, ctrl->tRFC, 511); + ctrl->tWTR = clamp_u32(4, ctrl->tWTR, 10); + ctrl->tRTP = clamp_u32(4, ctrl->tRTP, 15); + ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54); + + /** TODO: Honor tREFI from XMP **/ + ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz); + ctrl->tXP = get_tXP(ctrl->mem_clock_mhz); + + /* + * Check some values, and adjust them if necessary. + */ + + /* If tWR cannot be written into DDR3 MR0, adjust it */ + switch (ctrl->tWR) { + case 9: + case 11: + case 13: + case 15: + ctrl->tWR++; + } + + /* If tCWL is not supported or unspecified, look up a reasonable default */ + if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL) + ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz); + + /* This is needed to support ODT properly on 2DPC */ + if (ctrl->tAA - ctrl->tCWL > 4) + ctrl->tCWL = ctrl->tAA - 4; + + /* If tCMD is invalid, use a guesstimate default */ + if (!ctrl->tCMD) { + ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]); + printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n"); + } + ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3); + + /* + * Print final timings. + */ + + /* tCK is special */ + printk(BIOS_DEBUG, "Selected tCK : %u ps\n", ctrl->tCK * 1000 / 256); + + /* Primary timings */ + printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA); + printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); + printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); + printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); + printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); + printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); + printk(BIOS_DEBUG, "Selected tRC : %uT\n", ctrl->tRC); + printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); + printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); + printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); + printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); + printk(BIOS_DEBUG, "Selected tCWL : %uT\n", ctrl->tCWL); + printk(BIOS_DEBUG, "Selected tCMD : %uT\n", ctrl->tCMD); + + /* Derived timings */ + printk(BIOS_DEBUG, "Selected tREFI : %uT\n", ctrl->tREFI); + printk(BIOS_DEBUG, "Selected tXP : %uT\n", ctrl->tXP); + + return RAMINIT_STATUS_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/64185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Gerrit-Change-Number: 64185 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com>

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[L] Change in coreboot[main]: haswell NRI: Initialise MPLL
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64184?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: haswell NRI: Initialise MPLL ...................................................................... haswell NRI: Initialise MPLL Add code to initialise the MPLL (Memory PLL). The procedure is similar to the one for Sandy/Ivy Bridge, but it is not worth factoring out. Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64184 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk A src/northbridge/intel/haswell/native_raminit/init_mpll.c A src/northbridge/intel/haswell/native_raminit/io_comp_control.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/haswell/registers/mchbar.h 6 files changed, 259 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index ebf7abc..c125d84 100644 --- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk +++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later +romstage-y += init_mpll.c +romstage-y += io_comp_control.c romstage-y += raminit_main.c romstage-y += raminit_native.c romstage-y += spd_bitmunching.c diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c new file mode 100644 index 0000000..4b3005d --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci_ops.h> +#include <northbridge/intel/haswell/haswell.h> +#include <types.h> + +#include "raminit_native.h" + +static uint32_t get_mem_multiplier(const struct sysinfo *ctrl) +{ + const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq); + + if (ctrl->base_freq == 100) + return clamp_u32(7, mult, 12); + + if (ctrl->base_freq == 133) + return clamp_u32(3, mult, 10); + + die("Unsupported base frequency\n"); +} + +static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100) +{ + /** TODO: Haswell supports up to DDR3-2600 **/ + if (ctrl->tCK <= TCK_1200MHZ) { + ctrl->tCK = TCK_1200MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 1200; + + } else if (ctrl->tCK <= TCK_1100MHZ) { + ctrl->tCK = TCK_1100MHZ; + ctrl->base_freq = 100; + ctrl->mem_clock_mhz = 1100; + + } else if (ctrl->tCK <= TCK_1066MHZ) { + ctrl->tCK = TCK_1066MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 1066; + + } else if (ctrl->tCK <= TCK_1000MHZ) { + ctrl->tCK = TCK_1000MHZ; + ctrl->base_freq = 100; + ctrl->mem_clock_mhz = 1000; + + } else if (ctrl->tCK <= TCK_933MHZ) { + ctrl->tCK = TCK_933MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 933; + + } else if (ctrl->tCK <= TCK_900MHZ) { + ctrl->tCK = TCK_900MHZ; + ctrl->base_freq = 100; + ctrl->mem_clock_mhz = 900; + + } else if (ctrl->tCK <= TCK_800MHZ) { + ctrl->tCK = TCK_800MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 800; + + } else if (ctrl->tCK <= TCK_700MHZ) { + ctrl->tCK = TCK_700MHZ; + ctrl->base_freq = 100; + ctrl->mem_clock_mhz = 700; + + } else if (ctrl->tCK <= TCK_666MHZ) { + ctrl->tCK = TCK_666MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 666; + + } else if (ctrl->tCK <= TCK_533MHZ) { + ctrl->tCK = TCK_533MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 533; + + } else if (ctrl->tCK <= TCK_400MHZ) { + ctrl->tCK = TCK_400MHZ; + ctrl->base_freq = 133; + ctrl->mem_clock_mhz = 400; + + } else { + ctrl->tCK = 0; + ctrl->base_freq = 1; + ctrl->mem_clock_mhz = 0; + return; + } + if (!pll_ref100 && ctrl->base_freq == 100) { + /* Skip unsupported frequency */ + ctrl->tCK++; + normalize_tck(ctrl, pll_ref100); + } +} + +#define MIN_CAS 4 +#define MAX_CAS 24 + +static uint8_t find_compatible_cas(struct sysinfo *ctrl) +{ + printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK); + const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK)); + const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */ + + if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) { + printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower); + ctrl->tCK++; + return 0; + } + for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) { + printk(RAM_DEBUG, "%u ", cas); + if (ctrl->cas_supported & BIT(cas - MIN_CAS)) { + printk(RAM_DEBUG, "OK\n"); + return cas; + } + } + return 0; +} + +static enum raminit_status find_cas_tck(struct sysinfo *ctrl) +{ + /** TODO: Honor all possible PLL_REF100_CFG values **/ + uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7; + printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100); + printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no"); + + uint8_t selected_cas; + while (true) { + /* Round tCK up so that it is a multiple of either 133 or 100 MHz */ + normalize_tck(ctrl, pll_ref100); + if (!ctrl->tCK) { + printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n"); + return RAMINIT_STATUS_MPLL_INIT_FAILURE; + } + selected_cas = find_compatible_cas(ctrl); + if (selected_cas) + break; + + ctrl->tCK++; + } + printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n"); + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); + printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", selected_cas); + ctrl->multiplier = get_mem_multiplier(ctrl); + return RAMINIT_STATUS_SUCCESS; +} + +enum raminit_status initialise_mpll(struct sysinfo *ctrl) +{ + if (ctrl->tCK > TCK_400MHZ) { + printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n"); + ctrl->tCK = TCK_400MHZ; + } + while (true) { + /* + * On fast and S3 flows, MPLL frequency is already decided and + * has to match training data. So, skip finding the frequency. + * + * Also skip this when the MPLL is already locked. This can be + * the case if retrying raminit for some reason e.g. fast flow + * failed or the margins post power training are below minima. + */ + /** FIXME: This terribleness ignores failure modes in fast / S3 flows **/ + if (!ctrl->qclkps) { + const enum raminit_status status = find_cas_tck(ctrl); + if (status) + return status; + } + + /* + * Unlike previous generations, Haswell's MPLL won't shut down if the + * requested frequency isn't supported. But we cannot reinitialize it. + * Another different thing: MPLL registers are 4-bit instead of 8-bit. + */ + + /** FIXME: Obtain current clock frequency if we want to skip this **/ + //if (mchbar_read32(MC_BIOS_DATA) != 0) + // break; + + uint32_t mc_bios_req = ctrl->multiplier; + if (ctrl->base_freq == 100) { + /* Use 100 MHz reference clock */ + mc_bios_req |= BIT(4); + } + mc_bios_req |= BIT(31); + printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req); + printk(BIOS_DEBUG, "MPLL busy... "); + mchbar_write32(MC_BIOS_REQ, mc_bios_req); + + for (unsigned int i = 0; i <= 5000; i++) { + if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) { + printk(BIOS_DEBUG, "done in %u us\n", i); + break; + } + udelay(1); + } + if (mchbar_read32(MC_BIOS_REQ) & BIT(31)) + printk(BIOS_DEBUG, "did not lock\n"); + + /* Verify locked frequency */ + const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA); + printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data); + if ((mc_bios_data & 0xf) >= ctrl->multiplier) + break; + + printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n"); + ctrl->tCK++; + } + if (!ctrl->mem_clock_mhz) { + printk(BIOS_ERR, "Could not program MPLL frequency\n"); + return RAMINIT_STATUS_MPLL_INIT_FAILURE; + } + printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz); + ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz; + printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs); + ctrl->qclkps = ctrl->mem_clock_fs / 2000; + printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps); + return wait_for_first_rcomp(); +} diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c new file mode 100644 index 0000000..d45b608 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <northbridge/intel/haswell/haswell.h> +#include <timer.h> +#include <types.h> + +#include "raminit_native.h" + +enum raminit_status wait_for_first_rcomp(void) +{ + struct stopwatch timer; + stopwatch_init_msecs_expire(&timer, 2000); + do { + if (mchbar_read32(RCOMP_TIMER) & BIT(16)) + return RAMINIT_STATUS_SUCCESS; + + } while (!stopwatch_expired(&timer)); + printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n"); + return RAMINIT_STATUS_POLL_TIMEOUT; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index 2271705..ab462e0 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -20,7 +20,8 @@ }; static const struct task_entry cold_boot[] = { - { collect_spd_info, true, "PROCSPD", }, + { collect_spd_info, true, "PROCSPD", }, + { initialise_mpll, true, "INITMPLL", }, }; /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index 8078c9c..15a1550 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -24,6 +24,8 @@ RAMINIT_STATUS_SUCCESS = 0, RAMINIT_STATUS_NO_MEMORY_INSTALLED, RAMINIT_STATUS_UNSUPPORTED_MEMORY, + RAMINIT_STATUS_MPLL_INIT_FAILURE, + RAMINIT_STATUS_POLL_TIMEOUT, RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; @@ -83,10 +85,19 @@ uint8_t rankmap[NUM_CHANNELS]; uint8_t rank_mirrored[NUM_CHANNELS]; uint32_t channel_size_mb[NUM_CHANNELS]; + + uint8_t base_freq; /* Memory base frequency, either 100 or 133 MHz */ + uint32_t multiplier; + uint32_t mem_clock_mhz; + uint32_t mem_clock_fs; /* Memory clock period in femtoseconds */ + uint32_t qclkps; /* Quadrature clock period in picoseconds */ }; void raminit_main(enum raminit_boot_mode bootmode); enum raminit_status collect_spd_info(struct sysinfo *ctrl); +enum raminit_status initialise_mpll(struct sysinfo *ctrl); + +enum raminit_status wait_for_first_rcomp(void); #endif diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 5610e70..45f8174 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -13,6 +13,8 @@ #define MC_INIT_STATE_G 0x5030 #define MRC_REVISION 0x5034 /* MRC Revision */ +#define RCOMP_TIMER 0x5084 + #define MC_LOCK 0x50fc /* Memory Controller Lock register */ #define GFXVTBAR 0x5400 /* Base address for IGD */ @@ -61,6 +63,7 @@ #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ +#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ #define SAPMCTL 0x5f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/64184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6 Gerrit-Change-Number: 64184 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add PCU PCI drivers
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85316?usp=email ) Change subject: soc/intel/xeon_sp: Add PCU PCI drivers ...................................................................... soc/intel/xeon_sp: Add PCU PCI drivers Move PCU specific code into separate files: - PCUs registers are now locked by the PCI driver final call - set_bios_init_completion() is not part of PCU1 driver - Integrate config_reset_cpl3_csrs() into PCU driver TEST: Still boots on ocp/tiogapass. Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85316 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcu.h M src/soc/intel/xeon_sp/include/soc/util.h A src/soc/intel/xeon_sp/pcu0.c A src/soc/intel/xeon_sp/pcu1.c A src/soc/intel/xeon_sp/pcu2.c A src/soc/intel/xeon_sp/pcu3.c A src/soc/intel/xeon_sp/pcu6.c M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/util.c 21 files changed, 457 insertions(+), 581 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index b54b0ef..c6639a2 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -13,7 +13,10 @@ ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c - +ramstage-y += ../pcu0.c +ramstage-y += ../pcu1.c +ramstage-y += ../pcu2.c +ramstage-y += ../pcu3.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index afa5357..80cd029 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -94,42 +94,6 @@ iio_dmi_en_masks(); } -static void set_pcu_locks(void) -{ - struct device *dev = NULL; - - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, - PKG_PWR_LIM_LOCK_UPR); - pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, - TURBO_ACTIVATION_RATIO_LOCK); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, - PP_PWR_LIM_LOCK); - pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, - DRAM_POWER_INFO_LOCK_UPR); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); - pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK); - } -} - static void set_imc_locks(void) { struct device *dev = 0; @@ -152,13 +116,11 @@ /* LOCK PAM */ pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); - set_pcu_locks(); set_imc_locks(); set_upi_locks(); p2sb_hide(); iio_enable_masks(); - set_bios_init_completion(); } static void chip_init(void *data) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 0fc473e..808a0db 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -15,73 +15,11 @@ #define SAD_ALL_PAM456_CSR 0x44 #define SAD_ALL_DEVID 0x344f -#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - #define PCU_IIO_STACK 1 -#define PCU_DEV 30 - -#define PCU_CR0_FUN 0 #define PCU_CR0_DEVID 0x2080 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) -#define PCU_CR0_PLATFORM_INFO 0xa8 -#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 -#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) -#define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK BIT(31) -#define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 -#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) -#define PKG_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR0_PMAX 0xf0 -#define PMAX_LOCK BIT(31) - -#define PCU_CR1_FUN 1 #define PCU_CR1_DEVID 0x2081 -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 - -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) - -#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) - -#define PCU_CR1_SAPMCTL 0xb0 -#define SAPMCTL_LOCK_MASK BIT(31) - -#define PCU_CR2_FUN 2 #define PCU_CR2_DEVID 0x2082 -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) -#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 -#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) -#define DRAM_POWER_INFO_LOCK_UPR BIT(31) -#define PCU_CR2_DRAM_PLANE_POWER_LIMIT 0xf0 -#define PP_PWR_LIM_LOCK BIT(31) - -#define PCU_CR3_FUN 3 #define PCU_CR3_DEVID 0x2083 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) -#define PCU_CR3_CONFIG_TDP_CONTROL 0x60 -#define TDP_LOCK BIT(31) -#define PCU_CR3_FLEX_RATIO 0xa0 -#define OC_LOCK BIT(20) #if !defined(__SIMPLE_DEVICE__) #define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h index fab090a..bddca8a 100644 --- a/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h @@ -41,95 +41,17 @@ #define SAD_ALL_PAM456_CSR 0x84 #define SAD_ALL_DEVID 0x344f -#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - -/* PCU [B:31, D:30, F:0->F:6] */ -#define PCU_IIO_STACK UNCORE_BUS_1 -#define PCU_DEV 30 - -#define PCU_CR0_FUN 0 +/* PCU [B:31, D:30, F:0] */ +#define PCU_IIO_STACK 1 #define PCU_CR0_DEVID 0x3258 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) -#define PCU_CR0_PLATFORM_INFO 0xa8 -#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 -#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) -#define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK BIT(31) -#define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 -#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) -#define PKG_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR0_PMAX 0xf0 -#define PMAX_LOCK BIT(31) -#define PCU_CR0_VR_CURRENT_CONFIG_CFG 0xf8 -#define VR_CURRENT_CONFIG_LOCK BIT(31) - -#define PCU_CR1_FUN 1 +/* PCU [B:31, D:30, F:1] */ #define PCU_CR1_DEVID 0x3259 -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 - -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) - -#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xbc -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) - -#define PCU_CR2_FUN 2 +/* PCU [B:31, D:30, F:2] */ #define PCU_CR2_DEVID 0x325a -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) -#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 -#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) -#define DRAM_POWER_INFO_LOCK_UPR BIT(31) - -#define PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR 0xf0 -#define PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR (PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR + 4) -#define PP_PWR_LIM_LOCK_UPR BIT(31) - -#define PCU_CR3_FUN 3 +/* PCU [B:31, D:30, F:3] */ #define PCU_CR3_DEVID 0x325b -#define PCU_CR3_CAPID4 0x94 -#define ERR_SPOOFING_DIS 1 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) -#define PCU_CR3_CONFIG_TDP_CONTROL 0xd8 -#define TDP_LOCK BIT(31) -#define PCU_CR3_FLEX_RATIO 0xa0 -#define OC_LOCK BIT(20) - -#define PCU_CR4_FUN 4 -#define PCU_CR4_DEVID 0x325c -#define PCU_VIRAL_CONTROL 0x84 -#define PCU_FW_ERR_EN (1 << 10) -#define PCU_UC_ERR_EN (1 << 9) -#define PCU_HW_ERR_EN (1 << 8) -#define PCU_EMCA_MODE (1 << 2) - -#define PCU_CR6_FUN 6 +/* PCU [B:31, D:30, F:6] */ #define PCU_CR6_DEVID 0x325e -#define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) -#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 -#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) -#define PLT_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR6_PLATFORM_POWER_INFO_CFG_LWR 0xb0 -#define PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR (PCU_CR6_PLATFORM_POWER_INFO_CFG_LWR + 4) -#define PLT_PWR_INFO_LOCK_UPR BIT(31) /* Memory Map/VTD Device Functions * These are available in each IIO stack diff --git a/src/soc/intel/xeon_sp/include/soc/pcu.h b/src/soc/intel/xeon_sp/include/soc/pcu.h new file mode 100644 index 0000000..f6e024b --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pcu.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PCU_H_ +#define _SOC_PCU_H_ + +#if !defined(__SIMPLE_DEVICE__) +#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#else +#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#endif + +#define PCU_DEV 30 + +#define PCU_CR0_FUN 0 +#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) +#define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 +#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) +#define PCU_CR0_P_STATE_LIMITS 0xd8 +#define P_STATE_LIMITS_LOCK_SHIFT 31 +#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) +#define PCU_CR0_TEMPERATURE_TARGET 0xe4 +#define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 +#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) +#define PKG_PWR_LIM_LOCK_UPR BIT(31) +#define PCU_CR0_CURRENT_CONFIG 0xf8 +#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ +#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) +#define PCU_CR0_PMAX 0xf0 +#define PMAX_LOCK BIT(31) +#define PCU_CR0_VR_CURRENT_CONFIG_CFG 0xf8 +#define VR_CURRENT_CONFIG_LOCK BIT(31) + +#define PCU_CR1_FUN 1 + +#define PCU_CR1_C2C3TT_REG 0xdc +#define PCU_CR1_PCIE_ILTR_OVRD 0xfc +#define PCU_CR1_SAPMCTL 0xb0 + +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c + +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK BIT(31) +#define BIOS_MB_CMD_MASK 0xff +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x01 + +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK BIT(1) +#define RST_CPL2_MASK BIT(2) +#define RST_CPL3_MASK BIT(3) +#define RST_CPL4_MASK BIT(4) +#define PCODE_INIT_DONE1_MASK BIT(9) +#define PCODE_INIT_DONE2_MASK BIT(10) +#define PCODE_INIT_DONE3_MASK BIT(11) +#define PCODE_INIT_DONE4_MASK BIT(12) + +#define PCU_CR1_MC_BIOS_REQ 0x98 + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)) +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 +#else +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xbc +#endif +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) + +#define PCU_CR1_SAPMCTL 0xb0 +#define SAPMCTL_LOCK_MASK BIT(31) + +#define PCU_CR2_FUN 2 +#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c +#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 +#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ +#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 +#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) +#define DRAM_POWER_INFO_LOCK_UPR BIT(31) +#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc +#define UNCORE_PLIMIT_OVERRIDE_BIT 20 +#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) +#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 +#define PROCHOT_RATIO 0xa /* bits 0:7 */ +#define PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR 0xf0 +#define PP_PWR_LIM_LOCK BIT(31) +#define PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR (PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR + 4) +#define PP_PWR_LIM_LOCK_UPR BIT(31) + +#define PCU_CR3_FUN 3 +#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) +#define PCU_CR3_CAPID4 0x94 +#define ERR_SPOOFING_DIS 1 +#if (CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)) +#define PCU_CR3_CONFIG_TDP_CONTROL 0x60 +#else +#define PCU_CR3_CONFIG_TDP_CONTROL 0xd8 +#endif +#define TDP_LOCK BIT(31) +#define PCU_CR3_FLEX_RATIO 0xa0 +#define OC_LOCK BIT(20) + +#define PCU_CR4_FUN 4 +#define PCU_VIRAL_CONTROL 0x84 +#define PCU_FW_ERR_EN (1 << 10) +#define PCU_UC_ERR_EN (1 << 9) +#define PCU_HW_ERR_EN (1 << 8) +#define PCU_EMCA_MODE (1 << 2) + +#define PCU_CR6_FUN 6 +#define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) +#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 +#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) +#define PLT_PWR_LIM_LOCK_UPR BIT(31) +#define PCU_CR6_PLATFORM_POWER_INFO_CFG_LWR 0xb0 +#define PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR (PCU_CR6_PLATFORM_POWER_INFO_CFG_LWR + 4) +#define PLT_PWR_INFO_LOCK_UPR BIT(31) + +#endif /* _SOC_PCU_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 8e5833a..c4ea591 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -14,7 +14,6 @@ const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); bool soc_cpu_is_enabled(const size_t idx); -void set_bios_init_completion(void); bool is_memtype_non_volatile(uint16_t mem_type); bool is_memtype_reserved(uint16_t mem_type); diff --git a/src/soc/intel/xeon_sp/pcu0.c b/src/soc/intel/xeon_sp/pcu0.c new file mode 100644 index 0000000..1bc3c2a --- /dev/null +++ b/src/soc/intel/xeon_sp/pcu0.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pcu.h> +#include <soc/ramstage.h> +#include <soc/util.h> + +static void pcu0_final(struct device *dev) +{ + printk(BIOS_INFO, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, + TURBO_ACTIVATION_RATIO_LOCK); + + /* Set PMAX_LOCK - must be set before RESET CPL4 */ + pci_or_config32(dev, PCU_CR0_PMAX, PMAX_LOCK); +} + +static struct device_operations pcu0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .final = pcu0_final, +}; + +static const struct pci_driver pcu0_driver __pci_driver = { + .ops = &pcu0_ops, + .vendor = PCI_VID_INTEL, + .device = PCU_CR0_DEVID, +}; diff --git a/src/soc/intel/xeon_sp/pcu1.c b/src/soc/intel/xeon_sp/pcu1.c new file mode 100644 index 0000000..a19bfa8 --- /dev/null +++ b/src/soc/intel/xeon_sp/pcu1.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootstate.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/chip_common.h> +#include <soc/pci_devs.h> +#include <soc/pcu.h> +#include <soc/ramstage.h> +#include <soc/util.h> +#include <timer.h> + +/* return true if command timed out else false */ +static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask, + uint32_t target) +{ + const uint32_t max_delay = 5000; /* 5 seconds max */ + const uint32_t step_delay = 50; /* 50 us */ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, max_delay); + while ((pci_read_config32(pcu1, reg) & mask) != target) { + udelay(step_delay); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s timed out for dev: %s, reg: 0x%x, " + "mask: 0x%x, target: 0x%x\n", + __func__, dev_path(pcu1), reg, mask, target); + return true; /* timedout */ + } + } + return false; /* successful */ +} + +/* return true if command timed out else false */ +static bool write_bios_mailbox_cmd(struct device *pcu1, uint32_t command, uint32_t data) +{ + /* verify bios is not in busy state */ + if (wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) + return true; /* timed out */ + + /* write data to data register */ + printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_DATA_REG, data); + + pci_write_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write the command */ + printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, + PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); + + pci_write_config32(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, + command | BIOS_MB_RUN_BUSY_MASK); + + /* wait for completion or time out*/ + return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, + BIOS_MB_RUN_BUSY_MASK, 0); +} + +/* return true if command timed out else false */ +static bool set_bios_reset_cpl_for_package(struct device *pcu1, + uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, + uint32_t val) +{ + /* update BIOS RESET completion bit */ + pci_update_config32(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, ~rst_cpl_mask, val); + + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, + pcode_init_mask, pcode_init_mask); +} + +static void set_bios_init_completion_for_package(uint32_t socket) +{ + struct device *pcu1 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR1_DEVID); + bool timedout; + + if (!pcu1) + die("Failed to locate PCU PCI device\n"); + + /* update RST_CPL3, PCODE_INIT_DONE3 */ + timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL3_MASK, + PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); + if (timedout) + die("BIOS RESET CPL3 timed out.\n"); + + /* update RST_CPL4, PCODE_INIT_DONE4 */ + timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL4_MASK, + PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); + if (timedout) + die("BIOS RESET CPL4 timed out.\n"); +} + +static void set_bios_init_completion(void *unused) +{ + uint32_t sbsp_socket_id = 0; + + /* + * According to the BIOS Writer's Guide, the SBSP must be the last socket + * to receive the BIOS init completion message. So, we send it to all non-SBSP + * sockets first. + */ + for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { + if (!soc_cpu_is_enabled(socket)) + continue; + if (socket == sbsp_socket_id) + continue; + set_bios_init_completion_for_package(socket); + } + + /* And finally, take care of the SBSP */ + set_bios_init_completion_for_package(sbsp_socket_id); +} + +/* Set BIOS INIT completion after locking registers */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, set_bios_init_completion, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_bios_init_completion, NULL); + +static void pcu1_init(struct device *dev) +{ + u32 data; + bool timedout; + + printk(BIOS_INFO, "%s: init registers\n", dev_path(dev)); + + /* Make sure to issue BIOS_CMD_WRITE_PCU_MISC_CFG at least once */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) { + /* 2nd try */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) + die("BIOS PCU Misc Config Read timed out.\n"); + } + + data = pci_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); + printk(BIOS_SPEW, "%s - pci_read_config32 reg: 0x%x, data: 0x%x\n", + __func__, PCU_CR1_BIOS_MB_DATA_REG, data); + + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); + if (timedout) + die("BIOS PCU Misc Config Write timed out.\n"); + + if (CONFIG(SOC_INTEL_SKYLAKE_SP)) { + /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ + pci_and_config32(dev, PCU_CR1_SAPMCTL, 0xfffffff); + } +} + +static void pcu1_final(struct device *dev) +{ + printk(BIOS_INFO, "%s: locking registers\n", dev_path(dev)); + if (CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)) { + pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); + } + pci_or_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, + PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK); +} + +static struct device_operations pcu1_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pcu1_init, + .final = pcu1_final, +}; + +static const struct pci_driver pcu1_driver __pci_driver = { + .ops = &pcu1_ops, + .vendor = PCI_VID_INTEL, + .device = PCU_CR1_DEVID, +}; diff --git a/src/soc/intel/xeon_sp/pcu2.c b/src/soc/intel/xeon_sp/pcu2.c new file mode 100644 index 0000000..278bdb8 --- /dev/null +++ b/src/soc/intel/xeon_sp/pcu2.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pcu.h> +#include <soc/ramstage.h> +#include <soc/util.h> + +static void pcu2_init(struct device *dev) +{ + printk(BIOS_INFO, "%s: init registers\n", dev_path(dev)); + + if (CONFIG(SOC_INTEL_SKYLAKE_SP)) { + pci_or_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, 0xFFFFFF); + pci_or_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, 7); + + pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, + PROCHOT_RATIO); + pci_or_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, + UNOCRE_PLIMIT_OVERRIDE_SHIFT); + } +} + +static void pcu2_final(struct device *dev) +{ + printk(BIOS_INFO, "%s: locking registers\n", dev_path(dev)); + if (CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)) { + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR, + PP_PWR_LIM_LOCK); + } else { + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, + PP_PWR_LIM_LOCK_UPR); + } + pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, + DRAM_POWER_INFO_LOCK_UPR); +} + +static struct device_operations pcu2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pcu2_init, + .final = pcu2_final, +}; + +static const struct pci_driver pcu2_driver __pci_driver = { + .ops = &pcu2_ops, + .vendor = PCI_VID_INTEL, + .device = PCU_CR2_DEVID, +}; diff --git a/src/soc/intel/xeon_sp/pcu3.c b/src/soc/intel/xeon_sp/pcu3.c new file mode 100644 index 0000000..cd859e3 --- /dev/null +++ b/src/soc/intel/xeon_sp/pcu3.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pcu.h> +#include <soc/ramstage.h> +#include <soc/util.h> + +static void pcu3_final(struct device *dev) +{ + printk(BIOS_INFO, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + if (CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)) { + pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + } +} + +static struct device_operations pcu3_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .final = pcu3_final, +}; + +static const struct pci_driver pcu3_driver __pci_driver = { + .ops = &pcu3_ops, + .vendor = PCI_VID_INTEL, + .device = PCU_CR3_DEVID, +}; diff --git a/src/soc/intel/xeon_sp/pcu6.c b/src/soc/intel/xeon_sp/pcu6.c new file mode 100644 index 0000000..60a609e --- /dev/null +++ b/src/soc/intel/xeon_sp/pcu6.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pcu.h> +#include <soc/ramstage.h> +#include <soc/util.h> + +static void pcu6_final(struct device *dev) +{ + printk(BIOS_INFO, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, + PLT_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, + PLT_PWR_INFO_LOCK_UPR); +} + +static struct device_operations pcu6_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .final = pcu6_final, +}; + +static const struct pci_driver pcu6_driver __pci_driver = { + .ops = &pcu6_ops, + .vendor = PCI_VID_INTEL, + .device = PCU_CR6_DEVID, +}; diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk index 624d60a..2955cbf 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.mk +++ b/src/soc/intel/xeon_sp/skx/Makefile.mk @@ -23,7 +23,10 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += hob_display.c - +ramstage-y += ../pcu0.c +ramstage-y += ../pcu1.c +ramstage-y += ../pcu2.c +ramstage-y += ../pcu3.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 50a3ee3..2f05cfb 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -38,42 +38,6 @@ } } -static void set_pcu_locks(void) -{ - struct device *dev = NULL; - - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, - PKG_PWR_LIM_LOCK_UPR); - pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, - TURBO_ACTIVATION_RATIO_LOCK); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, - PP_PWR_LIM_LOCK); - pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, - DRAM_POWER_INFO_LOCK_UPR); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); - pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK); - } -} - static void set_imc_locks(void) { struct device *dev = 0; @@ -92,11 +56,8 @@ { // Temp Fix - should be done by FSP, in 2S bios completion // is not carried out on socket 2 - set_pcu_locks(); set_imc_locks(); set_upi_locks(); - - set_bios_init_completion(); } static void soc_init(void *data) diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 36dc63b..1becda8 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -293,8 +293,6 @@ */ chip_config = bus->dev->chip_info; - config_reset_cpl3_csrs(); - /* calls src/cpu/x86/mp_init.c */ /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(bus, &mp_ops); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 78393c1..b6414ad 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -9,16 +9,6 @@ #include <hob_iiouds.h> #include <soc/pch_pci_devs.h> -#define dump_csr(dev, reg) \ - printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x\n", \ - dev_path(dev), \ - #reg, reg, pci_read_config32(dev, reg)) - -#define dump_csr64(dev, reg) \ - printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x%x\n", \ - dev_path(dev), #reg, reg, \ - pci_read_config32(dev, reg+4), pci_read_config32(dev, reg)) - #define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x40 @@ -26,93 +16,11 @@ #define SAD_ALL_PAM456_CSR 0x44 #define SAD_ALL_DEVID 0x2054 -#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - #define PCU_IIO_STACK 1 -#define PCU_DEV 30 - -#define PCU_CR0_FUN 0 #define PCU_CR0_DEVID 0x2080 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) -#define PCU_CR0_PLATFORM_INFO 0xa8 -#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 -#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) -#define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK_SHIFT 31 -#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) -#define PCU_CR0_TEMPERATURE_TARGET 0xe4 -#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8 -#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT + 4) -#define PKG_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR0_CURRENT_CONFIG 0xf8 -#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ -#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) -#define PCU_CR0_PMAX 0xf0 -#define PMAX_LOCK BIT(31) - -#define PCU_CR1_FUN 1 #define PCU_CR1_DEVID 0x2081 - -#define PCU_CR1_C2C3TT_REG 0xdc -#define PCU_CR1_PCIE_ILTR_OVRD 0xfc -#define PCU_CR1_SAPMCTL 0xb0 - -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 - -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) - -#define PCU_CR1_MC_BIOS_REQ 0x98 - -#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) - -#define PCU_CR1_SAPMCTL 0xb0 -#define SAPMCTL_LOCK_MASK BIT(31) - -#define PCU_CR2_FUN 2 #define PCU_CR2_DEVID 0x2082 -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) -#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c -#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ -#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 -#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ -#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 -#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) -#define DRAM_POWER_INFO_LOCK_UPR BIT(31) -#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc -#define UNCORE_PLIMIT_OVERRIDE_BIT 20 -#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) -#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 -#define PROCHOT_RATIO 0xa /* bits 0:7 */ -#define PCU_CR2_DRAM_PLANE_POWER_LIMIT 0xf0 -#define PP_PWR_LIM_LOCK BIT(31) - -#define PCU_CR3_FUN 3 #define PCU_CR3_DEVID 0x2083 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) -#define PCU_CR3_CONFIG_TDP_CONTROL 0x60 -#define TDP_LOCK BIT(31) -#define PCU_CR3_FLEX_RATIO 0xa0 -#define OC_LOCK BIT(20) #if !defined(__SIMPLE_DEVICE__) #define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index ce7c645..f0e1761 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -9,8 +9,6 @@ #define xSTACK_RES STACK_RES #define xIIO_RESOURCE_INSTANCE IIO_RESOURCE_INSTANCE -void config_reset_cpl3_csrs(void); - const struct SystemMemoryMapHob *get_system_memory_map(void); uint8_t get_cxl_node_count(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 387b566..5a035f5 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -83,42 +83,6 @@ return false; } -#if ENV_RAMSTAGE -void config_reset_cpl3_csrs(void) -{ - uint32_t data; - struct device *dev; - - // FIXME: Looks like this needs to run after FSP-S since it modifies FSP defaults! - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { - data = pci_read_config32(dev, PCU_CR1_SAPMCTL); - /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ - data &= 0x0fffffff; - pci_write_config32(dev, PCU_CR1_SAPMCTL, data); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { - data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); - - data = KTI_IN_PKGCSTATE_L1_MASK; - pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); - - data = PROCHOT_RATIO; - printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); - dump_csr(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); - - data = pci_read_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); - data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_write_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); - } -} -#endif - bool is_memtype_reserved(uint16_t mem_type) { return !!(mem_type & MEM_TYPE_RESERVED); diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index f1755e4..39d6a99 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -17,6 +17,12 @@ ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +ramstage-y += ../pcu0.c +ramstage-y += ../pcu1.c +ramstage-y += ../pcu2.c +ramstage-y += ../pcu3.c +ramstage-y += ../pcu6.c + CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08 diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index e179df0..9fd747d 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -59,44 +59,6 @@ } } -static void set_pcu_locks(void) -{ - struct device *dev = NULL; - - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, - PKG_PWR_LIM_LOCK_UPR); - pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, - TURBO_ACTIVATION_RATIO_LOCK); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, - DRAM_POWER_INFO_LOCK_UPR); - pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, - PP_PWR_LIM_LOCK_UPR); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); - } - - dev = NULL; - while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR6_DEVID, dev))) { - printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); - pci_or_config32(dev, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, - PLT_PWR_LIM_LOCK_UPR); - pci_or_config32(dev, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, - PLT_PWR_INFO_LOCK_UPR); - } -} - static void chip_final(void *data) { /* Lock SBI */ @@ -105,7 +67,6 @@ /* LOCK PAM */ pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); - set_pcu_locks(); tco_lockdown(); p2sb_hide(); @@ -116,8 +77,6 @@ lock_oc_cfg(true); /* Disable CPU Crashlog to avoid conflict between CPU Crashlog and BMC ACD. */ disable_cpu_crashlog(); - - set_bios_init_completion(); } static void chip_init(void *data) diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index ae1a020..0825260 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -29,60 +29,14 @@ /* PCU [B:31, D:30, F:0] */ #define PCU_IIO_STACK 1 #define PCU_CR0_DEVID 0x3258 -#define PCU_CR0_PLATFORM_INFO 0xa8 -#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 -#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) -#define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK BIT(31) -#define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 -#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) -#define PKG_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR0_PMAX 0xf0 -#define PMAX_LOCK BIT(31) - /* PCU [B:31, D:30, F:1] */ #define PCU_CR1_DEVID 0x3259 -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 - -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) - -#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xbc -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) - /* PCU [B:31, D:30, F:2] */ #define PCU_CR2_DEVID 0x325a -#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 -#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) -#define DRAM_POWER_INFO_LOCK_UPR BIT(31) - -#define PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR 0xf0 -#define PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR (PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR + 4) -#define PP_PWR_LIM_LOCK_UPR BIT(31) - /* PCU [B:31, D:30, F:3] */ #define PCU_CR3_DEVID 0x325b -#define PCU_CR3_CONFIG_TDP_CONTROL 0xd8 -#define TDP_LOCK BIT(31) -#define PCU_CR3_FLEX_RATIO 0xa0 -#define OC_LOCK BIT(20) - /* PCU [B:31, D:30, F:6] */ #define PCU_CR6_DEVID 0x325e -#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 -#define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) -#define PLT_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR6_PLATFORM_POWER_INFO_CFG_LWR 0xb0 -#define PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR (PCU_CR6_PLATFORM_POWER_INFO_CFG_LWR + 4) -#define PLT_PWR_INFO_LOCK_UPR BIT(31) /* Memory Map/VTD Device Functions * These are available in each IIO stack at B:D.F = B:0.0 diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 69f3c15..3dd0155 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -120,139 +120,3 @@ } return p2sb_get_ioapic_bdf(); } - -#if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ - -/* return true if command timed out else false */ -static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask, - uint32_t target) -{ - const uint32_t max_delay = 5000; /* 5 seconds max */ - const uint32_t step_delay = 50; /* 50 us */ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, max_delay); - while ((pci_read_config32(pcu1, reg) & mask) != target) { - udelay(step_delay); - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "%s timed out for dev: %s, reg: 0x%x, " - "mask: 0x%x, target: 0x%x\n", - __func__, dev_path(pcu1), reg, mask, target); - return true; /* timedout */ - } - } - return false; /* successful */ -} - -/* return true if command timed out else false */ -static bool write_bios_mailbox_cmd(struct device *pcu1, uint32_t command, uint32_t data) -{ - /* verify bios is not in busy state */ - if (wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) - return true; /* timed out */ - - /* write data to data register */ - printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_DATA_REG, data); - - pci_write_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG, data); - - /* write the command */ - printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, - PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); - - pci_write_config32(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, - command | BIOS_MB_RUN_BUSY_MASK); - - /* wait for completion or time out*/ - return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, - BIOS_MB_RUN_BUSY_MASK, 0); -} - -/* return true if command timed out else false */ -static bool set_bios_reset_cpl_for_package(struct device *pcu1, - uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, - uint32_t val) -{ - /* update BIOS RESET completion bit */ - pci_update_config32(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, ~rst_cpl_mask, val); - - /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, - pcode_init_mask, pcode_init_mask); -} - -static void set_bios_init_completion_for_package(uint32_t socket) -{ - struct device *pcu0 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR0_DEVID); - struct device *pcu1 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR1_DEVID); - uint32_t data; - bool timedout; - - if (!pcu0 || !pcu1) - die("Failed to locate PCU PCI device\n"); - - /* read PCU config */ - timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) { - /* 2nd try */ - timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) - die("BIOS PCU Misc Config Read timed out.\n"); - - /* Since the 1st try failed, we need to make sure PCU is in stable state */ - data = pci_read_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG); - printk(BIOS_SPEW, "%s - pci_read_config32 reg: 0x%x, data: 0x%x\n", - __func__, PCU_CR1_BIOS_MB_DATA_REG, data); - timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_WRITE_PCU_MISC_CFG, data); - if (timedout) - die("BIOS PCU Misc Config Write timed out.\n"); - } - - /* update RST_CPL3, PCODE_INIT_DONE3 */ - timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL3_MASK, - PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); - if (timedout) - die("BIOS RESET CPL3 timed out.\n"); - - /* Set PMAX_LOCK - must be set before RESET CPL4 */ - data = pci_read_config32(pcu0, PCU_CR0_PMAX); - data |= PMAX_LOCK; - pci_write_config32(pcu0, PCU_CR0_PMAX, data); - - /* update RST_CPL4, PCODE_INIT_DONE4 */ - timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL4_MASK, - PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); - if (timedout) - die("BIOS RESET CPL4 timed out.\n"); - - /* set CSR_DESIRED_CORES_CFG2 lock bit */ - data = pci_read_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG); - data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; - printk(BIOS_SPEW, "%s - pci_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", - __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); - pci_write_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG, data); -} - -void set_bios_init_completion(void) -{ - uint32_t sbsp_socket_id = 0; - - /* - * According to the BIOS Writer's Guide, the SBSP must be the last socket - * to receive the BIOS init completion message. So, we send it to all non-SBSP - * sockets first. - */ - for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - if (socket == sbsp_socket_id) - continue; - set_bios_init_completion_for_package(socket); - } - - /* And finally, take care of the SBSP */ - set_bios_init_completion_for_package(sbsp_socket_id); -} -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Gerrit-Change-Number: 85316 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... soc/intel/xeon_sp/skx: Configure IOAPICs FSP only configures the PCH IOAPIC. Let coreboot reconfigure all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI address for each IOAPIC instead of assume it's a linear address space. Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info() from advertising wrong GSI addresses. TEST: Booted on ocp/tiogapass with correct GSI bases asigned matching the _PRT advertised GSI bases. Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2. See Document Reference Number: 329595-002 Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/lpc_gen1.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk A src/soc/intel/xeon_sp/skx/ioapic.c 4 files changed, 74 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/lpc_gen1.c b/src/soc/intel/xeon_sp/lpc_gen1.c index 9a1c629..b1d1efe 100644 --- a/src/soc/intel/xeon_sp/lpc_gen1.c +++ b/src/soc/intel/xeon_sp/lpc_gen1.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <arch/ioapic.h> #include <console/console.h> #include <intelblocks/lpc_lib.h> @@ -7,6 +8,9 @@ { printk(BIOS_SPEW, "pch: lpc_init\n"); - /* FSP configures IOAPIC and PCHInterrupt Config */ - /* Should read back the ID to fill ACPI IOAPIC accordingly. */ + if (CONFIG(SOC_INTEL_SKYLAKE_SP)) { + /* FSP only configures PCH IOAPIC, but it doesn't configure PCI IOAPICs. + * Let coreboot handle all IOAPICs and assign unique IDs to each. */ + register_new_ioapic_gsi0(IO_APIC_ADDR); + } } diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 1783c66..970dba3 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -63,8 +63,4 @@ string default "lbg" -config XEON_SP_HAVE_IIO_IOAPIC - bool - default y - endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk index 456e932..624d60a 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.mk +++ b/src/soc/intel/xeon_sp/skx/Makefile.mk @@ -19,6 +19,7 @@ ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-y += soc_util.c ramstage-y += cpu.c +ramstage-y += ioapic.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += hob_display.c diff --git a/src/soc/intel/xeon_sp/skx/ioapic.c b/src/soc/intel/xeon_sp/skx/ioapic.c new file mode 100644 index 0000000..99a5368 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/ioapic.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <soc/chip_common.h> + +static void ioapic_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + u16 abar = pci_read_config16(dev, APIC_ABAR); + if (!abar) + return; + const u32 addr = IO_APIC_ADDR | ((abar & 0xfff) << 8); + + printk(BIOS_DEBUG, " %s: IOAPIC Address: 0x%x\n", + dev_path(dev), addr); + + mmio_range(dev, APIC_ABAR, addr, 0x100); +} + +static void ioapic_init(struct device *dev) +{ + struct resource *resource; + + pci_dev_init(dev); + + /* See if there is a resource with the appropriate index. */ + resource = probe_resource(dev, APIC_ABAR); + if (!resource) + return; + + const union xeon_domain_path dn = { + .domain_path = dev_get_domain_id(dev) + }; + + /* 14nm Xeon-SP has up to 6 stacks per socket */ + assert(dn.stack < MAX_LOGIC_IIO_STACK); + + /* Assign socket specific GSI_BASE */ + const u32 gsi_base = 24 + (dn.socket * MAX_LOGIC_IIO_STACK + dn.stack) * 8; + + ioapic_create_dev(dev, resource->base, gsi_base); +} + +static const unsigned short ioapic_ids[] = { + 0x2036, + 0x2026, + 0 +}; + +static struct device_operations ioapic_ops = { + .read_resources = ioapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, +}; + +static const struct pci_driver ioapic_driver __pci_driver = { + .ops = &ioapic_ops, + .vendor = PCI_VID_INTEL, + .devices = ioapic_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Tim Chu, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... Patch Set 12: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85170/comment/1e34479c_59ca709e?us… : PS11, Line 9: FSP only configures the PCH IOAPIC. Let coreboot reconfigure : all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, : and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact : GSI address for each IOAPIC instead of assume it's a linear address : space. > If you re-flowed for 72 characters per line, maybe you could save the last one. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 09:00:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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