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Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support
......................................................................
Patch Set 17:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85126/comment/80801639_c74430dc?us… :
PS17, Line 13: TEST=build pass
Were you able to run-time test it? Maybe print the new log messages.
File src/soc/mediatek/mt8196/pmif_spmi.c:
https://review.coreboot.org/c/coreboot/+/85126/comment/2c564f0a_12703761?us… :
PS17, Line 190: int
size_t
https://review.coreboot.org/c/coreboot/+/85126/comment/93b9a28f_6b46346e?us… :
PS17, Line 345: spmi
SPMI
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Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85464/comment/e67291f9_fe20432e?us… :
PS4, Line 9: The GPP_F23/ISH_GP_9A pin receives the lid open/close signal from
: SMC_LID. This pin is not utilized in the AP firmware stack; however, the
: ISH firmware requires this signal for its tablet mode support.
: Therefore, we configure this pin as an ISH GPIO.
The right side looks a little unaligned. It’d be great if you re-flowed.
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Change subject: mb/google/trulo/var/uldrenite: Add memory config
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85542/comment/245a55a4_1e10363b?us… :
PS4, Line 12: TEST=emerge-nissa coreboot
Were you able to run-time test it?
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Change subject: drivers/amd/nova: Add Nova Card directory
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84776/comment/beebba6d_e6ccaae3?us… :
PS5, Line 7: directory
As you add more than the directory, maybe just write “common driver”?
https://review.coreboot.org/c/coreboot/+/84776/comment/fe0c42ed_8c75d8db?us… :
PS5, Line 9: As multiple boards use the NOVA daughter card, the function that detects
: the connector type has been moved to the drivers folder and
: will be refactored in the soc path in the following patches.
This looks a little strange. Maybe also re-flow the second and third line.
File src/drivers/amd/nova/nova_card.c:
https://review.coreboot.org/c/coreboot/+/84776/comment/4b735efb_9fbf37fa?us… :
PS5, Line 24: uint16_t connector_type = data[1] | data[0] << 8;
> `please, no spaces at the start of a line`
Please fix.
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Change subject: mb/google/brya/var/uldrenite: update gpio settings
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85522/comment/f715fe1e_1eebe03b?us… :
PS2, Line 9: schematics
Please add the file name.
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Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c:
https://review.coreboot.org/c/coreboot/+/85146/comment/79d6304a_f44547da?us… :
PS14, Line 25: /* If battery is not present, limit the power to the power optimized configuration. */
Could be omitted as the code below is (luckily) very readable/understandable.
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Change subject: soc/intel/alderlake: Add a function to force disable memory channels
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85529/comment/5da32a4b_e3b98a33?us… :
PS3, Line 7: a
Articles can be omitted in the summary/title.
https://review.coreboot.org/c/coreboot/+/85529/comment/1d574cca_ebaf5f38?us… :
PS3, Line 8:
Maybe mention the motivation of incorrect DMI information.
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Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85537/comment/c7e6c232_a1fb0b94?us… :
PS3, Line 9: support
support*s*
https://review.coreboot.org/c/coreboot/+/85537/comment/15c0003f_d459ce7c?us… :
PS3, Line 11:
Please document the source for the sequence.
https://review.coreboot.org/c/coreboot/+/85537/comment/48f49852_e2d21eb6?us… :
PS3, Line 14: TEST=emerge-nissa coreboot
Is the boot time affected? Please mention the total time before and after.
File src/mainboard/google/brya/variants/uldrenite/variant.c:
https://review.coreboot.org/c/coreboot/+/85537/comment/485157c2_407c4379?us… :
PS3, Line 27: * RW350R power on seuqence:
: * De-assert WWAN_EN -> 20ms -> de-assert WWAN_RST -> 30ms ->
: * de-assert WWAN_PERST
: */
The asterisks need to be aligned with the very first one.
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Change subject: soc/intel/alderlake: Add a function to force disable memory channels
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/85529/comment/ebd0f09f_3784ce63?us… :
PS1, Line 252: if (ch_disable_mask == 0) {
> I need to check the answer internally, will reply later.
Per intel PDG doc "LPDDR5 x32 memory down placement and block diagram", MC0CH0/MC0CH1 enabled or MC0CH2/MC0CH3 enabled is valid case based on DRAM chip population, but correctly for one dram chip to support x32 we only do the validation on MC0Ch0/MC0Ch1 enabled.
Could we add a message to suggest using MC0Ch0/MC0Ch1 combination for x32 memory configuration?
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