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[M] Change in coreboot[main]: mb/hp/snb_ivb_laptops: Add SMBIOS slot information
by Felix Held (Code Review) 25 Jan '24

25 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80173?usp=email ) Change subject: mb/hp/snb_ivb_laptops: Add SMBIOS slot information ...................................................................... mb/hp/snb_ivb_laptops: Add SMBIOS slot information Looking at photos and service manuals, all the WLAN slots are short (half-height) and WWAN slots long (full-height). Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb 8 files changed, 56 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb index 8e9688f..092049c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb @@ -29,7 +29,10 @@ device ref pcie_rp1 on end device ref pcie_rp2 off end device ref pcie_rp3 on end # SD/MMC - device ref pcie_rp4 on end # WLAN + device ref pcie_rp4 on # WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 off end device ref pcie_rp6 off end device ref pcie_rp7 off end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index b1cc9fe..af80813 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -25,9 +25,15 @@ device ref xhci on end device ref pcie_rp1 on end - device ref pcie_rp2 on end # ExpressCard + device ref pcie_rp2 on + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end device ref pcie_rp3 on end # SD/MMC - device ref pcie_rp4 on end # WLAN + device ref pcie_rp4 on # WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 off end device ref pcie_rp6 off end device ref pcie_rp7 off end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb index 8299cce..9d1890a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb @@ -21,12 +21,21 @@ register "sata_port_map" = "0x21" device ref pcie_rp1 on end - device ref pcie_rp2 on end # ExpressCard + device ref pcie_rp2 on + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end device ref pcie_rp3 on end # SD/MMC - device ref pcie_rp4 on end # WLAN + device ref pcie_rp4 on # WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 off end device ref pcie_rp6 off end - device ref pcie_rp7 on end # WWAN + device ref pcie_rp7 on # WWAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp8 off end device ref lpc on chip ec/hp/kbc1126 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index b87c80a..bf64099 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -23,12 +23,21 @@ device ref me_kt on end device ref pcie_rp1 on end - device ref pcie_rp2 on end # ExpressCard + device ref pcie_rp2 on + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end device ref pcie_rp3 on end # SD/MMC - device ref pcie_rp4 on end # WLAN + device ref pcie_rp4 on # WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 off end device ref pcie_rp6 off end - device ref pcie_rp7 on end # WWAN + device ref pcie_rp7 on # WWAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp8 on end # NEC USB 3.0 Host Controller device ref lpc on chip ec/hp/kbc1126 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index b02b2f9..cfc5372 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -27,9 +27,15 @@ device ref xhci on end device ref me_kt on end device ref pcie_rp1 on end - device ref pcie_rp2 on end # ExpressCard + device ref pcie_rp2 on # ExpressCard + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end device ref pcie_rp3 on end # SD/MMC - device ref pcie_rp4 on end # WLAN + device ref pcie_rp4 on # WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 off end device ref pcie_rp6 off end device ref pcie_rp7 off end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index d30f179..f326c40 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -29,7 +29,10 @@ device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end # Media Card and FireWire host controller - device ref pcie_rp4 on end # Wireless LAN Adapter + device ref pcie_rp4 on # Wireless LAN Adapter + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 on end # SATA Controller 2 for dock device ref pcie_rp6 off end device ref pcie_rp7 off end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 1e690b5..1e3984d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -27,7 +27,10 @@ device ref pcie_rp1 on end device ref pcie_rp2 off end device ref pcie_rp3 on end # SDHCI - device ref pcie_rp4 on end # WLAN + device ref pcie_rp4 on # WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp5 off end device ref pcie_rp6 off end device ref pcie_rp7 off end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb index b76fe5b..64653bc 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb @@ -32,7 +32,10 @@ end device ref pcie_rp5 off end device ref pcie_rp6 off end - device ref pcie_rp7 on end # WWAN + device ref pcie_rp7 on # WWAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X" + end device ref pcie_rp8 off end device ref lpc on chip ec/hp/kbc1126 -- To view, visit https://review.coreboot.org/c/coreboot/+/80173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb Gerrit-Change-Number: 80173 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/brya/var/*: Ensure LCD device has a valid address
by Felix Held (Code Review) 25 Jan '24

25 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80062?usp=email ) Change subject: mb/google/brya/var/*: Ensure LCD device has a valid address ...................................................................... mb/google/brya/var/*: Ensure LCD device has a valid address Some variants added the generic gfx driver with an LCD device without specifying the address, which is required for the backlight controls to be functional under Windows. Add the address value where missing. Address value used (0x80010400) is same as on other Brya variants which did properly set it, and is taken from the ACPI 6.5 spec section B.4.2, _DOD (display output device enumeration), table B-2: - bit 31 = use the ACPI-defined (vs vendor-defined) bit scheme for bits 15-0 - bit 16 = platform firmware can detect the device - bit 10 = display type is internal/integrated flat panel (aka LCD) TEST=build/boot Win11 on google/brya (osiris), verify ACPI backlight controls functional. Change-Id: Id24e330cfb7c993d12665a704e1ca78e2e38874f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80062 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/anraggar/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/crota/overridetree.cb M src/mainboard/google/brya/variants/dochi/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/marasov/overridetree.cb M src/mainboard/google/brya/variants/mithrax/overridetree.cb M src/mainboard/google/brya/variants/omnigul/overridetree.cb M src/mainboard/google/brya/variants/osiris/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/skolas4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb 25 files changed, 50 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 0a72246..1961e09 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -118,6 +118,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index ed4037e..c7cce88 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -100,6 +100,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 2c4cecc..ca9c655 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -200,6 +200,8 @@ register "device_count" = "4" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 3e3c33c..38c4528 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -99,6 +99,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index d7eadbe..a4a0ae5 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -123,6 +123,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index b3cab3c..8b671e1 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -112,6 +112,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index 19ace7b..880b7bc 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -92,6 +92,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 46a841d..74f2114 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -98,6 +98,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP0 diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index b35a64f..0de70e5 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -79,6 +79,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 1962127..6351248 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -44,6 +44,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 8ef5ed2..cbce022 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -101,6 +101,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 3ea7092..64ca6a7 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -146,6 +146,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index cd79b2c..6df9b60 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -96,6 +96,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP0 diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 0942299d..4a3d368 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -131,6 +131,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index e8b78ca..0c21a61 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -75,6 +75,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index a06578d..d815587 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -87,6 +87,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 7301615..f8502aa 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -133,6 +133,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 1a619f8..6e00215 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -114,6 +114,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index bb6d1ea..3f17008 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -122,6 +122,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb index b020d01..326c675 100644 --- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb @@ -117,6 +117,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 744a870..27584cd 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -142,6 +142,8 @@ register "device_count" = "3" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB # TCP0 (DP-1) for port C0 register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index a2c79d5..22b3ca7 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -123,6 +123,8 @@ register "device_count" = "3" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB # TCP0 (DP-1) for port C0 register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 0d335b6..1e0101a 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -119,6 +119,8 @@ register "device_count" = "3" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB # TCP0 (DP-1) for port C0 register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 30df62a..6956312 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -98,6 +98,8 @@ register "device_count" = "5" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB # TCP0 (DP-1) for port C0 register "device[1].name" = ""DD01"" diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index c0dccfa..1de6626 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -93,6 +93,8 @@ register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" # DDIB for HDMI register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 -- To view, visit https://review.coreboot.org/c/coreboot/+/80062?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id24e330cfb7c993d12665a704e1ca78e2e38874f Gerrit-Change-Number: 80062 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: lib/smbios: Add 32 bit entry point if below 4G
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Felix Held, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76911?usp=email ) Change subject: lib/smbios: Add 32 bit entry point if below 4G ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cb426bb0c45282ed03ff4c65d15004b7f985dab Gerrit-Change-Number: 76911 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:40:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups
by Patrick Rudolph (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/79878/comment/7435a764_0824f0b1 : PS4, Line 33: return hob->PlatformData.CpuQpiInfo[dn.socket].PcieSegment; > in another word, how dn. […] correct. that's done in CB:80099 -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:39:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups
by Shuo Liu (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/79878/comment/4bd2ad48_ced1bfe9 : PS4, Line 33: return hob->PlatformData.CpuQpiInfo[dn.socket].PcieSegment; > I don't understand the question. in another word, how dn.socket is initially assigned? seems it is not defined in this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:32:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups
by Patrick Rudolph (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/79878/comment/4993fb1d_d0f7fcac : PS4, Line 33: return hob->PlatformData.CpuQpiInfo[dn.socket].PcieSegment; > how will the xeon_domain_path work? I don't understand the question. -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:21:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/opensil_console: fix host debug print function
by Matt DeVillier (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80203?usp=email ) Change subject: vc/amd/opensil/genoa_poc/opensil_console: fix host debug print function ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia931cc80dea5b7eabb75cfb19f8baa9a09cd2dbf Gerrit-Change-Number: 80203 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:16:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups
by Shuo Liu (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups ...................................................................... Patch Set 4: -Code-Review (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/79878/comment/db16039e_516d8e23 : PS4, Line 33: return hob->PlatformData.CpuQpiInfo[dn.socket].PcieSegment; how will the xeon_domain_path work? -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:14:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini
by Matt DeVillier (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Paul Menzel. Hello Jonathon Hall, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80182?usp=email to look at the new patch set (#2). Change subject: mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini ...................................................................... mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini As with other devices with only an external display, the Librem mini/ mini-v2 need a few extra seconds (vs an internal panel) for display init in order for the edk2 boot splash to be visible before the default boot target is booted. TEST=build/boot Librem Mini v2 w/edk2 payload, verify splash screen shown / user has time to enter setup menu. Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem_cnl/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/80182/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Gerrit-Change-Number: 80182 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini
by Matt DeVillier (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Paul Menzel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80182?usp=email ) Change subject: mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80182/comment/1dd7e12b_a589bef4 : PS1, Line 7: Set edk2 boot timeout for Librem Mini > Maybe more specific: Add 4 s edk2 boot timeout for Librem Mini not sure that's needed, it was using the default and we're setting an override value. https://review.coreboot.org/c/coreboot/+/80182/comment/59885b6f_a11e6935 : PS1, Line 9: display init > Is that dependent on the connected monitor? not really, just the current edk2 default is set based on the time it takes for an internal panel to come up; all Chromeboxes and many other boards without an internal display override to 4-5s -- To view, visit https://review.coreboot.org/c/coreboot/+/80182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Gerrit-Change-Number: 80182 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 25 Jan 2024 14:06:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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