Attention is currently required from: Felix Held, Paul Menzel, Varshit Pandya.
Hello Felix Held, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80204?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins)
Change subject: mb/amd/onyx_poc: Add and use APCB configuration data
......................................................................
mb/amd/onyx_poc: Add and use APCB configuration data
This patch adds APCB blobs to the mainboard directory and it replaces
https://review.coreboot.org/c/blobs/+/76445
Also this brings onyx_poc mainboard inline with how APCB are included in
other AMD mainboard:
commit 95d05d830162 ("mb/google/zork: Add and use APCB configuration data"),
commit I352f58e0d39 ("mb/google/skyrim: Add and use APCB configuration data")
and commit I1c34528fa0f ("mb/amd/onyx_poc: Add and use APCB configuration data")
BUG=none
TEST=build/boot onyx_poc
Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/mainboard/amd/onyx_poc/Makefile.mk
A src/mainboard/amd/onyx_poc/data.apcb
A src/mainboard/amd/onyx_poc/data1.apcb
A src/mainboard/amd/onyx_poc/data_rec.apcb
A src/mainboard/amd/onyx_poc/data_rec1.apcb
A src/mainboard/amd/onyx_poc/data_rec2.apcb
6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80204/5
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Change subject: nb/intel/*: Match ACPI with resource allocation
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Numbers look good. The comment could be more accurate. Technically, it only
> shouldn't be higher than what ACPI reports, so the OS doesn't get confused.
Done. Updated comments.
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Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Nico Huber.
Hello Angel Pons, Felix Held, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: nb/intel/*: Match ACPI with resource allocation
......................................................................
nb/intel/*: Match ACPI with resource allocation
Currently resource allocation starts top down from the default value
0xfe000000. This does not match what ACPI reports, so adapt
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be
---
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/x4x/Kconfig
7 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/80207/2
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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
Patch Set 16:
(1 comment)
Patchset:
PS4:
> I don't see any benefit of having support for SIMICS default QSP target as it's emulating even less bits than QEMU.
So this simulated target does not simulate a lot of hardware so this indeed is mostly a stub. So from the perspective of testing more stuff, it's not an added value. When SIMICS is used with another more real target, there is no use for this code.
I was told that Intel uses this QSP target (internally) in SIMICS training, so mostly to people get familiar with both firmware building and testing it on this simulator. I think this use case is what makes this target a valuable addition to coreboot.
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Change subject: nb/intel/*: Match ACPI with resource allocation
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Numbers look good. The comment could be more accurate. Technically, it only
shouldn't be higher than what ACPI reports, so the OS doesn't get confused.
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Change subject: nb/intel/*: Match ACPI with resource allocation
......................................................................
nb/intel/*: Match ACPI with resource allocation
Currently resource allocation starts top down from the default value
0xfe000000. This does not match what ACPI reports, so adapt
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be
---
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/x4x/Kconfig
7 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/80207/1
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 2a266b9..22625df 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -30,6 +30,10 @@
int
default 64
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config SMM_RESERVED_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 4b83a25..0f89cfb 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -60,6 +60,10 @@
int
default 64
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default ECAM_MMCONF_BASE_ADDRESS
+
config DCACHE_RAM_BASE
hex
default 0xff7c0000
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 9c1a111..941250f 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -40,6 +40,10 @@
int
default 64
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config OVERRIDE_CLOCK_DISABLE
bool
default n
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 502b99b..8dcfca1 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -46,6 +46,10 @@
config ECAM_MMCONF_BUS_NUMBER
default 256
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config INTEL_GMA_BCLV_OFFSET
default 0x48254
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index c652209..77df5f2 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -37,4 +37,8 @@
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 34a0939..aeffd6e 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -103,6 +103,10 @@
int
default 64
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default ECAM_MMCONF_BASE_ADDRESS
+
config DCACHE_RAM_BASE
hex
default 0xfefe0000
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 248852e..bb62e38 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -27,6 +27,10 @@
int
default 256
+# This must match ACPI
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config SMM_RESERVED_SIZE
hex
default 0x100000
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Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
Patch Set 1: Code-Review+1
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Hello Felix Held, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/amd/onyx_poc: Add and use APCB configuration data
......................................................................
mb/amd/onyx_poc: Add and use APCB configuration data
This patch adds APCB blobs to the mainboard directory and it replaces
CB:76445. Also this brings onyx_poc mainboard inline with how APCB are
included in other AMD mainboard, CB:79591, CB:79592 and CB:79593
BUG=none
TEST=build/boot onyx_poc
Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/mainboard/amd/onyx_poc/Makefile.mk
A src/mainboard/amd/onyx_poc/data.apcb
A src/mainboard/amd/onyx_poc/data1.apcb
A src/mainboard/amd/onyx_poc/data_rec.apcb
A src/mainboard/amd/onyx_poc/data_rec1.apcb
A src/mainboard/amd/onyx_poc/data_rec2.apcb
6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80204/4
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Hello Felix Held, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80204?usp=email
to look at the new patch set (#3).
Change subject: mb/amd/onyx_poc: Add and use APCB configuration data
......................................................................
mb/amd/onyx_poc: Add and use APCB configuration data
This patch adds APCB blobs to the mainboard directory and it replaces
https://review.coreboot.org/c/blobs/+/76445
Also this brings onyx_poc mainboard inline with how APCB are included in
other AMD mainboard:
commit 95d05d830162 ("mb/google/zork: Add and use APCB configuration data"),
commit I352f58e0d39 ("mb/google/skyrim: Add and use APCB configuration data")
and commit I1c34528fa0f ("mb/amd/onyx_poc: Add and use APCB configuration data")
BUG=none
TEST=build/boot onyx_poc
Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/mainboard/amd/onyx_poc/Makefile.mk
A src/mainboard/amd/onyx_poc/data.apcb
A src/mainboard/amd/onyx_poc/data1.apcb
A src/mainboard/amd/onyx_poc/data_rec.apcb
A src/mainboard/amd/onyx_poc/data_rec1.apcb
A src/mainboard/amd/onyx_poc/data_rec2.apcb
6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80204/3
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80173?usp=email )
Change subject: mb/hp/snb_ivb_laptops: Add SMBIOS slot information
......................................................................
mb/hp/snb_ivb_laptops: Add SMBIOS slot information
Looking at photos and service manuals, all the WLAN slots are short
(half-height) and WWAN slots long (full-height).
Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb
Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80173
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
8 files changed, 56 insertions(+), 14 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
index 8e9688f..092049c 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
@@ -29,7 +29,10 @@
device ref pcie_rp1 on end
device ref pcie_rp2 off end
device ref pcie_rp3 on end # SD/MMC
- device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp4 on # WLAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
device ref pcie_rp7 off end
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
index b1cc9fe..af80813 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
@@ -25,9 +25,15 @@
device ref xhci on end
device ref pcie_rp1 on end
- device ref pcie_rp2 on end # ExpressCard
+ device ref pcie_rp2 on
+ smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
+ "ExpressCard Slot" "SlotDataBusWidth1X"
+ end
device ref pcie_rp3 on end # SD/MMC
- device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp4 on # WLAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
device ref pcie_rp7 off end
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
index 8299cce..9d1890a 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
@@ -21,12 +21,21 @@
register "sata_port_map" = "0x21"
device ref pcie_rp1 on end
- device ref pcie_rp2 on end # ExpressCard
+ device ref pcie_rp2 on
+ smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
+ "ExpressCard Slot" "SlotDataBusWidth1X"
+ end
device ref pcie_rp3 on end # SD/MMC
- device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp4 on # WLAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
- device ref pcie_rp7 on end # WWAN
+ device ref pcie_rp7 on # WWAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp8 off end
device ref lpc on
chip ec/hp/kbc1126
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
index b87c80a..bf64099 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
@@ -23,12 +23,21 @@
device ref me_kt on end
device ref pcie_rp1 on end
- device ref pcie_rp2 on end # ExpressCard
+ device ref pcie_rp2 on
+ smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
+ "ExpressCard Slot" "SlotDataBusWidth1X"
+ end
device ref pcie_rp3 on end # SD/MMC
- device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp4 on # WLAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
- device ref pcie_rp7 on end # WWAN
+ device ref pcie_rp7 on # WWAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp8 on end # NEC USB 3.0 Host Controller
device ref lpc on
chip ec/hp/kbc1126
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
index b02b2f9..cfc5372 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
@@ -27,9 +27,15 @@
device ref xhci on end
device ref me_kt on end
device ref pcie_rp1 on end
- device ref pcie_rp2 on end # ExpressCard
+ device ref pcie_rp2 on # ExpressCard
+ smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
+ "ExpressCard Slot" "SlotDataBusWidth1X"
+ end
device ref pcie_rp3 on end # SD/MMC
- device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp4 on # WLAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
device ref pcie_rp7 off end
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
index d30f179..f326c40 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
@@ -29,7 +29,10 @@
device ref pcie_rp1 on end
device ref pcie_rp2 on end
device ref pcie_rp3 on end # Media Card and FireWire host controller
- device ref pcie_rp4 on end # Wireless LAN Adapter
+ device ref pcie_rp4 on # Wireless LAN Adapter
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 on end # SATA Controller 2 for dock
device ref pcie_rp6 off end
device ref pcie_rp7 off end
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
index 1e690b5..1e3984d 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
@@ -27,7 +27,10 @@
device ref pcie_rp1 on end
device ref pcie_rp2 off end
device ref pcie_rp3 on end # SDHCI
- device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp4 on # WLAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
device ref pcie_rp7 off end
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
index b76fe5b..64653bc 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
@@ -32,7 +32,10 @@
end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
- device ref pcie_rp7 on end # WWAN
+ device ref pcie_rp7 on # WWAN
+ smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X"
+ end
device ref pcie_rp8 off end
device ref lpc on
chip ec/hp/kbc1126
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb
Gerrit-Change-Number: 80173
Gerrit-PatchSet: 3
Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged