coreboot-gerrit January 2024

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[S] Change in coreboot[main]: vc/amd: move verstage on PSP files to new psp_verstage folder
by Felix Held (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80209?usp=email to look at the new patch set (#2). Change subject: vc/amd: move verstage on PSP files to new psp_verstage folder ...................................................................... vc/amd: move verstage on PSP files to new psp_verstage folder Move the verstage on PSP files in vendorcode from the fsp subdirectory to a new psp_verstage subdirectory, since those files aren't specific to the case of the FSP being used for the silicon initialization. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 --- M src/soc/amd/cezanne/psp_verstage/Makefile.mk M src/soc/amd/glinda/psp_verstage/Makefile.mk M src/soc/amd/mendocino/psp_verstage/Makefile.mk M src/soc/amd/phoenix/psp_verstage/Makefile.mk M src/soc/amd/picasso/Makefile.mk M src/soc/amd/picasso/psp_verstage/Makefile.mk R src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/common/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/glinda/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/phoenix/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_syscall_public.h 27 files changed, 17 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/80209/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 Gerrit-Change-Number: 80209 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: soc/amd/stoney: Match ACPI with resource allocation
by Nico Huber (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held. Hello Arthur Heymans, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/80190?usp=email to review the following change. Change subject: soc/amd/stoney: Match ACPI with resource allocation ...................................................................... soc/amd/stoney: Match ACPI with resource allocation Currently resource allocation starts top down from the default value 0xfe000000. This does not match what ACPI reports, so adapt CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that. Change-Id: I32d08ffd5bbd856b17f7ca2775c5923957d92c85 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/80190/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index e94c2f9..47de102 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -140,6 +140,10 @@ config ECAM_MMCONF_BUS_NUMBER default 64 +# This number must be equal or lower than what's reported in ACPI PCI _CRS +config DOMAIN_RESOURCE_32BIT_LIMIT + default ECAM_MMCONF_BASE_ADDRESS + config VGA_BIOS_ID string default "1002,9870" if AMD_APU_MERLINFALCON -- To view, visit https://review.coreboot.org/c/coreboot/+/80190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32d08ffd5bbd856b17f7ca2775c5923957d92c85 Gerrit-Change-Number: 80190 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: vc/amd: move verstage on files to new psp_verstage folder
by Felix Held (Code Review) 25 Jan '24

25 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80209?usp=email ) Change subject: vc/amd: move verstage on files to new psp_verstage folder ...................................................................... vc/amd: move verstage on files to new psp_verstage folder Move the verstage on PSP files in vendorcode from the fsp subdirectory to a new psp_verstage subdirectory, since those files aren't specific to the case of the FSP being used for the silicon initialization. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 --- M src/soc/amd/cezanne/psp_verstage/Makefile.mk M src/soc/amd/glinda/psp_verstage/Makefile.mk M src/soc/amd/mendocino/psp_verstage/Makefile.mk M src/soc/amd/phoenix/psp_verstage/Makefile.mk M src/soc/amd/picasso/Makefile.mk M src/soc/amd/picasso/psp_verstage/Makefile.mk R src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/common/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/glinda/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/phoenix/include/bl_uapp/bl_syscall_public.h R src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_end.S R src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_header.inc R src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_startup.S R src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_errorcodes_public.h R src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_syscall_public.h 27 files changed, 17 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/80209/1 diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.mk b/src/soc/amd/cezanne/psp_verstage/Makefile.mk index 2cb1345..bb9cc47 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.mk +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include +verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/cezanne/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include @@ -10,5 +10,5 @@ verstage-y += chipset.c verstage-y += uart.c -verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk index 472ca2d..f8ad736 100644 --- a/src/soc/amd/glinda/psp_verstage/Makefile.mk +++ b/src/soc/amd/glinda/psp_verstage/Makefile.mk @@ -6,14 +6,14 @@ verstage-generic-ccopts += -I$(src)/soc/amd/glinda/psp_verstage/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/glinda/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/glinda/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include verstage-y += svc.c verstage-y += chipset.c verstage-y += uart.c -verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S +verstage-y +=$(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S endif diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.mk b/src/soc/amd/mendocino/psp_verstage/Makefile.mk index 19dd8a7..347f26a 100644 --- a/src/soc/amd/mendocino/psp_verstage/Makefile.mk +++ b/src/soc/amd/mendocino/psp_verstage/Makefile.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/mendocino/include +verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/mendocino/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include @@ -10,5 +10,5 @@ verstage-y += chipset.c verstage-y += uart.c -verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.mk b/src/soc/amd/phoenix/psp_verstage/Makefile.mk index 6a2eace..fc9f413 100644 --- a/src/soc/amd/phoenix/psp_verstage/Makefile.mk +++ b/src/soc/amd/phoenix/psp_verstage/Makefile.mk @@ -3,12 +3,12 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/phoenix/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include verstage-y += svc.c verstage-y += chipset.c verstage-y += uart.c -verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S +verstage-y +=$(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk index ba58c91..7a21852 100644 --- a/src/soc/amd/picasso/Makefile.mk +++ b/src/soc/amd/picasso/Makefile.mk @@ -41,7 +41,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.mk b/src/soc/amd/picasso/psp_verstage/Makefile.mk index bf1a694..77ceb0c 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.mk +++ b/src/soc/amd/picasso/psp_verstage/Makefile.mk @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include +verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/picasso/include verstage-y += svc.c verstage-y += chipset.c verstage-y += uart.c -verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_end.S similarity index 100% rename from src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S rename to src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_header.inc similarity index 100% rename from src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_header.inc rename to src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_header.inc diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_startup.S similarity index 100% rename from src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S rename to src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/bl_uapp_startup.S diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_errorcodes_public.h similarity index 100% rename from src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_errorcodes_public.h rename to src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_errorcodes_public.h diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_syscall_public.h similarity index 100% rename from src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h rename to src/vendorcode/amd/psp_verstage/cezanne/include/bl_uapp/bl_syscall_public.h diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S similarity index 100% rename from src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S rename to src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_header.inc similarity index 100% rename from src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_header.inc rename to src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_header.inc diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S similarity index 100% rename from src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S rename to src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S diff --git a/src/vendorcode/amd/fsp/common/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/psp_verstage/common/include/bl_uapp/bl_errorcodes_public.h similarity index 100% rename from src/vendorcode/amd/fsp/common/include/bl_uapp/bl_errorcodes_public.h rename to src/vendorcode/amd/psp_verstage/common/include/bl_uapp/bl_errorcodes_public.h diff --git a/src/vendorcode/amd/fsp/glinda/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/psp_verstage/glinda/include/bl_uapp/bl_syscall_public.h similarity index 100% rename from src/vendorcode/amd/fsp/glinda/include/bl_uapp/bl_syscall_public.h rename to src/vendorcode/amd/psp_verstage/glinda/include/bl_uapp/bl_syscall_public.h diff --git a/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_end.S similarity index 100% rename from src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S rename to src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_end.S diff --git a/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_header.inc similarity index 100% rename from src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_header.inc rename to src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_header.inc diff --git a/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_startup.S similarity index 100% rename from src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S rename to src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/bl_uapp_startup.S diff --git a/src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_errorcodes_public.h similarity index 100% rename from src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_errorcodes_public.h rename to src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_errorcodes_public.h diff --git a/src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_syscall_public.h similarity index 100% rename from src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_syscall_public.h rename to src/vendorcode/amd/psp_verstage/mendocino/include/bl_uapp/bl_syscall_public.h diff --git a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/psp_verstage/phoenix/include/bl_uapp/bl_syscall_public.h similarity index 100% rename from src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h rename to src/vendorcode/amd/psp_verstage/phoenix/include/bl_uapp/bl_syscall_public.h diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_end.S similarity index 100% rename from src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S rename to src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_header.inc similarity index 100% rename from src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_header.inc rename to src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_header.inc diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_startup.S similarity index 100% rename from src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S rename to src/vendorcode/amd/psp_verstage/picasso/bl_uapp/bl_uapp_startup.S diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_errorcodes_public.h similarity index 100% rename from src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h rename to src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_errorcodes_public.h diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_syscall_public.h similarity index 100% rename from src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h rename to src/vendorcode/amd/psp_verstage/picasso/include/bl_uapp/bl_syscall_public.h -- To view, visit https://review.coreboot.org/c/coreboot/+/80209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 Gerrit-Change-Number: 80209 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach more stacks
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Christian Walter, Felix Held, Johnny Lin, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80091?usp=email ) Change subject: soc/intel/xeon_sp: Attach more stacks ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/skx/soc_util.c: https://review.coreboot.org/c/coreboot/+/80091/comment/8649bb0f_f80ae259 : PS4, Line 62: bool is_ubox_stack_res(const STACK_RES *res) : { : return res->Personality == 0; : } > We do not have tiogapass to validate and rely on community to confirm this. Maybe a FIXME and warning print could be added to reminder who uses the codes to validate when needed? This is wrong. On Skx no ubox gets reported as stack :-/ Personality 0 is disabled, Personality 1 is IIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 18:42:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: factor out common acpi_add_ivrs_table implementation
by Felix Held (Code Review) 25 Jan '24

25 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80208?usp=email ) Change subject: soc/amd: factor out common acpi_add_ivrs_table implementation ...................................................................... soc/amd: factor out common acpi_add_ivrs_table implementation Instead of open-coding this functionality in all AMD SoCs, factor it out into a common implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 --- M src/soc/amd/cezanne/agesa_acpi.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/glinda/agesa_acpi.c M src/soc/amd/mendocino/agesa_acpi.c M src/soc/amd/phoenix/agesa_acpi.c M src/soc/amd/picasso/agesa_acpi.c 8 files changed, 21 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/80208/1 diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c index fdfe3eb..e6ccd9c 100644 --- a/src/soc/amd/cezanne/agesa_acpi.c +++ b/src/soc/amd/cezanne/agesa_acpi.c @@ -10,8 +10,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -19,11 +17,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 605c4f5..547163c 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -297,7 +297,7 @@ return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev); } -unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) +static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { unsigned long current_backup; uint64_t mmio_x30_value; @@ -433,3 +433,16 @@ return current; } + +unsigned long acpi_add_ivrs_table(unsigned long current, acpi_rsdp_t *rsdp) +{ + acpi_ivrs_t *ivrs; + + current = acpi_align_current(current); + ivrs = (acpi_ivrs_t *)current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); + + return current; +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 9c70864..a195371 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -56,6 +56,6 @@ uintptr_t current); void acpi_log_events(const struct chipset_power_state *ps); -unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current); +unsigned long acpi_add_ivrs_table(unsigned long current, acpi_rsdp_t *rsdp); #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index 7762e9d..cadf8db 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -42,12 +42,7 @@ struct acpi_rsdp *rsdp) { /* IVRS */ - acpi_ivrs_t *ivrs; - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/glinda/agesa_acpi.c b/src/soc/amd/glinda/agesa_acpi.c index 7ac19c7..f6c3c98 100644 --- a/src/soc/amd/glinda/agesa_acpi.c +++ b/src/soc/amd/glinda/agesa_acpi.c @@ -12,8 +12,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -21,11 +19,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/mendocino/agesa_acpi.c b/src/soc/amd/mendocino/agesa_acpi.c index d60a79d..1e4d600 100644 --- a/src/soc/amd/mendocino/agesa_acpi.c +++ b/src/soc/amd/mendocino/agesa_acpi.c @@ -12,8 +12,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -21,11 +19,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/phoenix/agesa_acpi.c b/src/soc/amd/phoenix/agesa_acpi.c index 251acc6..598ae81 100644 --- a/src/soc/amd/phoenix/agesa_acpi.c +++ b/src/soc/amd/phoenix/agesa_acpi.c @@ -13,8 +13,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -22,11 +20,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 9ee977f..7a32779 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -542,7 +542,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; struct acpi_crat_header *crat; /* CRAT */ @@ -557,11 +556,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); /* Add SRAT, MSCT, SLIT if needed in the future */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Gerrit-Change-Number: 80208 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/amd/onyx_poc: Add and use APCB configuration data
by Felix Held (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Matt DeVillier, Paul Menzel, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80204?usp=email ) Change subject: mb/amd/onyx_poc: Add and use APCB configuration data ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Gerrit-Change-Number: 80204 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 25 Jan 2024 17:09:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/amd/onyx_poc: Add and use APCB configuration data
by Varshit Pandya (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Felix Held, Matt DeVillier, Paul Menzel. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80204?usp=email ) Change subject: mb/amd/onyx_poc: Add and use APCB configuration data ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80204/comment/6dcc2bd1_136613cb : PS2, Line 9: This patch replaces [76445](https://review.coreboot.org/c/blobs/+/76445) > > This could go to the end. Maybe also name it change-set …. […] Done https://review.coreboot.org/c/coreboot/+/80204/comment/ff3e3962_bf369b19 : PS2, Line 10: It brings onyx_poc in-line with skyrim, guybrush and zork. > It means we're moving the APCB data to the mainboard dir, as was already done with the other listed […] Done Patchset: PS6: sorry for multiple patchsets, was experimenting a bit with clickable links 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/80204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Gerrit-Change-Number: 80204 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Jan 2024 17:07:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/*: Match ACPI with resource allocation
by Nico Huber (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80207?usp=email ) Change subject: nb/intel/*: Match ACPI with resource allocation ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be Gerrit-Change-Number: 80207 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Jan 2024 17:05:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Organize models configs alphabetically
by Subrata Banik (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Kapil Porwal, Nick Vaccaro, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80206?usp=email ) Change subject: mb/google/rex: Organize models configs alphabetically ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/80206/comment/2ae2b411_723ed052 : PS1, Line 66: BOARD_GOOGLE_MODEL_DEKU > What's the difference between BOARD_GOOGLE_MODEL_DEKU and BOARD_GOOGLE_DEKU ? > > I don't see any BOARD_GOOGLE_MODEL_XXX in brya's Kconfig, wasn't familiar with that. this is the easy way to avoid config duplication between each variants having QS and ES SoC. we have decided to create a model which selects all common config between QS and ES variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/80206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Gerrit-Change-Number: 80206 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 16:58:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Organize models configs alphabetically
by Nick Vaccaro (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Kapil Porwal, Subrata Banik, Tarun. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80206?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex: Organize models configs alphabetically ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/80206/comment/7b004cb4_7edac284 : PS1, Line 66: BOARD_GOOGLE_MODEL_DEKU What's the difference between BOARD_GOOGLE_MODEL_DEKU and BOARD_GOOGLE_DEKU ? I don't see any BOARD_GOOGLE_MODEL_XXX in brya's Kconfig, wasn't familiar with that. -- To view, visit https://review.coreboot.org/c/coreboot/+/80206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Gerrit-Change-Number: 80206 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 16:50:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2024