coreboot-gerrit January 2024

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[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by David Ruth (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Cliff Huang, David Ruth, Lance Zhao, Paul Menzel, Subrata Banik, Subrata Banik, Tim Wawrzynczak. Hello Cliff Huang, Lance Zhao, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80170?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Add MTCL function to ACPI SSDT tables The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Adds acpigen_write_mtcl in order to generate the AML code for the MTCL method. * Adds the mtcl.c file to abstract functionality related to reading the binary file that defines the MTCL, and verifying that the format is one intended to be handled by this implementation. * Reads a binary file called "wifi_mtcl.hex" in cbfs * Verifies that the format matches a supported value * Returns the size and byte array to caller * Adds config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Adds config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Adds config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.hex" * Adds functionality to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for WiFi devices when the above flags are enabled BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.hex blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth(a)chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 --- M src/acpi/acpigen.c M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.inc M src/drivers/wifi/generic/acpi.c A src/drivers/wifi/generic/mtcl.c M src/include/acpi/acpigen.h M src/include/device/pci_ids.h A src/include/mtcl.h 8 files changed, 219 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 8 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/common: Add lunarlake device IDs
by Bora Guvendik (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Appukuttan V K, Ashish Kumar Mishra. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79900?usp=email ) Change subject: soc/intel/common: Add lunarlake device IDs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Gerrit-Change-Number: 79900 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 21:54:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device: Add a helper function to add a downstream bus
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu. Hello Christian Walter, Johnny Lin, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80210?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: device: Add a helper function to add a downstream bus ...................................................................... device: Add a helper function to add a downstream bus Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 --- M src/device/device.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/spr/ioat.c 4 files changed, 39 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80210/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Gerrit-Change-Number: 80210 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/common: Add lunarlake device IDs
by Wonkyu Kim (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Appukuttan V K, Ashish Kumar Mishra, Bora Guvendik. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79900?usp=email ) Change subject: soc/intel/common: Add lunarlake device IDs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Gerrit-Change-Number: 79900 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 21:34:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common: Add lunarlake device IDs
by Wonkyu Kim (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Appukuttan V K, Ashish Kumar Mishra, Bora Guvendik. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79900?usp=email ) Change subject: soc/intel/common: Add lunarlake device IDs ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Gerrit-Change-Number: 79900 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Thu, 25 Jan 2024 21:34:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier, Nico Huber. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78328?usp=email ) Change subject: device/device.h: Drop multiple links ...................................................................... Patch Set 14: (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/78328/comment/cb95aed0_3b829c09 : PS14, Line 232: struct bus *bus = calloc(1, sizeof(struct bus)); : if (!bus) : die("Couldn't allocate downstream bus!\n"); : dev->link_list = bus; : bus->dev = dev; > It's probably a good idea to put this in a helper. I saw a similar flaw in the xeon_sp code where going upwards in the tree was broken due to lacking bus->dev. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Jan 2024 21:32:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device: Add a helper function to add a downstream bus
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Christian Walter, Johnny Lin, Tim Chu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80210?usp=email ) Change subject: device: Add a helper function to add a downstream bus ...................................................................... device: Add a helper function to add a downstream bus Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 --- M src/device/device.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/spr/ioat.c 4 files changed, 39 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80210/1 diff --git a/src/device/device.c b/src/device/device.c index 811b709..d6a1d07 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -125,6 +125,40 @@ return dev; } +DECLARE_SPIN_LOCK(bus_lock) + +/** + * Allocate a new bus structure. + * + * Allocate a new bus structure and attach it to the device tree + * + * @param parent Parent bus the newly created device should be attached to. + * @return Pointer to the newly created bus structure or the existing bus. + * + */ +static struct device *__alloc_bus(struct device *parent) +{ + if (parent->link_list) + return parent->link_list; + + struct bus *bus = calloc(1, sizeof(struct bus)); + if (!bus) + die("Couldn't allocate downstream bus!\n"); + parent->link_list = bus; + bus->dev = parent; + + return bus; +} + +struct device *alloc_bus(struct device *parent) +{ + struct device *dev; + spin_lock(&bus_lock); + dev = __alloc_bus(parent); + spin_unlock(&bus_lock); + return dev; +} + /** * See if a device structure already exists and if not allocate it. * diff --git a/src/include/device/device.h b/src/include/device/device.h index 83588d4..13bc8dc 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -171,6 +171,7 @@ /* Generic device interface functions */ struct device *alloc_dev(struct bus *parent, struct device_path *path); +struct bus *alloc_bus(struct device *parent); void dev_initialize_chips(void); void dev_enumerate(void); void dev_configure(void); @@ -229,10 +230,9 @@ static inline void mp_cpu_bus_init(struct device *dev) { /* Make sure the cpu cluster has a downstream bus for LAPICs to be allocated. */ - if (!dev->link_list) - add_more_links(dev, 1); + struct bus *bus = alloc_bus(dev); - mp_init_cpus(dev->link_list); + mp_init_cpus(bus); } /* Debug functions */ diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index bf2a015..845e968 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -72,14 +72,7 @@ if (!sr) return; - if (!dev->link_list) { - dev->link_list = calloc(1, sizeof(struct bus)); - if (!dev->link_list) - die("%s: out of memory.\n", __func__); - } - - struct bus *bus = dev->link_list; - bus->dev = dev; + struct bus *bus = alloc_bus(dev); bus->secondary = sr->BusBase; bus->subordinate = sr->BusBase; bus->max_subordinate = sr->BusLimit; diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 02f35cf..60936a8 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -45,12 +45,7 @@ domain->ops = &ioat_domain_ops; - domain->link_list = calloc(1, sizeof(struct bus)); - if (!domain->link_list) - die("%s: out of memory.\n", __func__); - - struct bus *const bus = domain->link_list; - bus->dev = domain; + struct bus *const bus = alloc_bus(domain); bus->secondary = bus_base; bus->subordinate = bus->secondary; bus->max_subordinate = bus_limit; -- To view, visit https://review.coreboot.org/c/coreboot/+/80210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Gerrit-Change-Number: 80210 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh. Hello Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78330?usp=email to look at the new patch set (#21). Change subject: device/device.h: Rename busses for clarity ...................................................................... device/device.h: Rename busses for clarity This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/x86/mpspec.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/device/cardbus_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/i2c_bus.c M src/device/mdio.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/interrupt.c M src/device/pci_device.c M src/device/pci_rom.c M src/device/pciexp_device.c M src/device/pcix_device.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/device/root_device.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pcie/generic/generic.c M src/drivers/spi/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/smbios.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/google/chromeec/ec_acpi.c M src/include/device/device.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/brox/mainboard.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/kahlee/variants/careena/mainboard.c M src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/roda/rk9/ti_pci7xx1.c M src/mainboard/siemens/fa_ehl/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/xhci.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/xhci.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/intel/apollolake/chip.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/pcie.c M src/superio/common/generic.c M src/superio/common/ssdt.c M src/superio/nuvoton/npcd378/superio.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M util/sconfig/main.c 104 files changed, 342 insertions(+), 347 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/78330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Gerrit-Change-Number: 78330 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Piotr Król 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Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Arthur Heymans (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier, Nico Huber. Hello Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78328?usp=email to look at the new patch set (#15). Change subject: device/device.h: Drop multiple links ...................................................................... device/device.h: Drop multiple links Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b --- M src/arch/x86/mpspec.c M src/device/device.c M src/device/device_util.c M src/device/pci_device.c M src/device/root_device.c M src/include/device/device.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/common/block/lpc/lpc.c M src/southbridge/amd/pi/hudson/lpc.c M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.y 16 files changed, 185 insertions(+), 360 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78328/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: soc/amd: factor out common acpi_add_ivrs_table implementation
by Marshall Dawson (Code Review) 25 Jan '24

25 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80208?usp=email ) Change subject: soc/amd: factor out common acpi_add_ivrs_table implementation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Gerrit-Change-Number: 80208 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Jan 2024 21:31:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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