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Change subject: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80000/comment/126fe483_daf1e586 :
PS5, Line 8:
> Please start by mentioning that the touchscreen does not work.
No, the touchscreen can work. But the default setting of SOC_TCHSCR_RST is native function 1. Set SOC_TCHSCR_RST to output low to prevent it pull high unexpectedly.
https://review.coreboot.org/c/coreboot/+/80000/comment/cb1edd24_5a48a55b :
PS5, Line 10: Set SOC_TCHSCR_RST to output low in bootblock.
> Why in bootblock? So, the delay can be reduced?
It's related to CB:79571. The reason of set EN_TCHSCR_PWR to output high in bootblock is because the delay time between EN_TCHSCR_PWR high --> SOC_TCHSCR_RST high is too short to meet spec. To extend the delay time, set EN_TCHSCR_PWR to output high from romstage_gpio_table to early_gpio_table.
Set SOC_TCHSCR_RST to output low in early_gpio_table is because the default setting of SOC_TCHSCR_RST is native function 1. To prevent it pull high unexpectedly, set it to output low in early_gpio_table.
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Change subject: mb/google/nissa/var/anraggar: Enable BT audio offload
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Patch Set 5: Code-Review+2
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Change subject: mb/google/rex: Organize models configs alphabetically
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/Kconfig:
https://review.coreboot.org/c/coreboot/+/80206/comment/ac8532bf_5a9a858b :
PS1, Line 66: BOARD_GOOGLE_MODEL_DEKU
> > What's the difference between BOARD_GOOGLE_MODEL_DEKU and BOARD_GOOGLE_DEKU ?
> >
> > I don't see any BOARD_GOOGLE_MODEL_XXX in brya's Kconfig, wasn't familiar with that.
>
> this is the easy way to avoid config duplication between each variants having QS and ES SoC. we have decided to create a model which selects all common config between QS and ES variants.
@Nick, I'm marking resolve. let me know otherwise
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Change subject: mb/google/rex: Organize models configs alphabetically
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I would suggest modify the create variant script too.
good idea. let me talk to SIE folks.
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Change subject: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Hi Felix, The CL review is set CR+2 over 1 day. Could you kindly help to submit if no concern? Thanks.
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Change subject: soc/intel/commonlake: Re-add SATA to soc_api_name() list
......................................................................
soc/intel/commonlake: Re-add SATA to soc_api_name() list
Now that we've added an ACPI device for SATA, add the name back
to the soc_acpi_name() list so the PEPD LPI constraint list
generates a valid reference to the SATA device.
TEST=build/boot Win11 on google/puff (kaisa).
Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059
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---
M src/soc/intel/cannonlake/chip.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Felix Singer: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index a1ba17e..0da6e40 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -94,6 +94,7 @@
case PCH_DEVFN_CSE_IDER: return "CSED";
case PCH_DEVFN_CSE_KT: return "CSKT";
case PCH_DEVFN_CSE_3: return "CSE3";
+ case PCH_DEVFN_SATA: return "SATA";
case PCH_DEVFN_UART2: return "UAR2";
case PCH_DEVFN_I2C4: return "I2C4";
case PCH_DEVFN_I2C5: return "I2C5";
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Change subject: soc/intel/commonlake: Re-add SATA to soc_api_name() list
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Patch Set 1: Code-Review+2
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