coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

[XL] Change in coreboot[main]: Docs: Replace Recommonmark with MyST Parser
by Nicholas Chin (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth, Nicholas Chin. Hello Angel Pons, Daniel Maslowski, Felix Singer, Jason Glenesk, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73158?usp=email to look at the new patch set (#6). Change subject: Docs: Replace Recommonmark with MyST Parser ...................................................................... Docs: Replace Recommonmark with MyST Parser Recommonmark has been deprecated since 2021 [1] and the last release was over 3 years ago [2]. As per their announcement, Markedly Structured Text (MyST) Parser [3] is the recommended replacement. For the most part, the existing documentation is compatible with MyST, as both parsers are built around the CommonMark flavor of Markdown. The main difference that affects coreboot is how the Sphinx toctree is generated. Recommonmark has a feature called auto_toc_tree, which converts single level lists of references into a toctree: * [Part 1: Starting from scratch](part1.md) * [Part 2: Submitting a patch to coreboot.org](part2.md) * [Part 3: Writing unit tests](part3.md) * [Managing local additions](managing_local_additions.md) * [Flashing firmware](flashing_firmware/index.md) MyST Parser does not provide a replacement for this feature, meaning the toctree must be defined manually. This is done using MyST's syntax for Sphinx directives: ```{toctree} :maxdepth: 1 Part 1: Starting from scratch <part1.md> Part 2: Submitting a patch to coreboot.org <part2.md> Part 3: Writing unit tests <part3.md> Managing local additions <managing_local_additions.md> Flashing firmware <flashing_firmware/index.md> ``` Internally, auto_toc_tree essentially converts lists of references into the Sphinx toctree structure that the MyST syntax above more directly represents. This was converted using by running all md files through the following Python script, and then manually reverting some false positives: ``` import re import sys in_list = False f = open(sys.argv[1]) lines = f.readlines() f.close() with open(sys.argv[1], "w") as f: for line in lines: match = re.match(r"^[-*+] \[(.*)\]$(.*)$$", line) if match is not None: if not in_list: in_list = True f.write("```{toctree}\n") f.write(":maxdepth: 1\n\n") f.write(match.group(1) + " <" + match.group(2) + ">\n") else: if in_list: f.write("```\n") f.write(line) in_list = False if in_list: f.write("```\n") ``` While this does add a little more work for creating the toctree, this does give more control over exactly what goes into the toctree. For instance, lists of links to external resources currently end up in the toctree, but we may want to limit it to pages within coreboot. This change does break rendering and navigation of the documentation in applications that can render Markdown, such as Okular, Gitiles, or the GitHub mirror. Assuming the docs are mainly intended to be viewed after being rendered to doc.coreboot.org, this is probably not an issue in practice. Another difference is that MyST natively supports Markdown tables, whereas with Recommonmark, tables had to be written in embedded rST [6]. However, MyST also supports embedded rST, so the existing tables can be easily converted as the syntax is nearly identical. These were converted using `find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"` Makefile.sphinx and conf.py were regenerated from scratch by running `sphinx-quickstart` using the updated version of Sphinx, which removes a lot of old commented out boilerplate. Any relevant changes coreboot had made on top of the previous autogenerated versions of these files were ported over to the newly generated file. From some initial testing the generated webpages appear identical to the existing documentation, though highlighting in searches also does not seem to be working. This is likely due to the with the newer versions of Sphinx and sphinx-rtd-theme. [1] https://github.com/readthedocs/recommonmark/issues/221 [2] https://pypi.org/project/recommonmark/ [3] https://myst-parser.readthedocs.io/en/latest/ [4] https://doc.coreboot.org/getting_started/writing_documentation.html Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/Makefile.sphinx M Documentation/acpi/index.md M Documentation/acronyms.md M Documentation/arch/index.md M Documentation/arch/x86/index.md M Documentation/community/index.md M Documentation/conf.py M Documentation/contributing/index.md M Documentation/drivers/index.md M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md M Documentation/external_docs.md M Documentation/getting_started/build_system.md M Documentation/getting_started/gpio.md M Documentation/getting_started/index.md M Documentation/getting_started/kconfig.md M Documentation/gfx/display-panel.md M Documentation/index.md M Documentation/infrastructure/builders.md M Documentation/infrastructure/index.md M Documentation/lib/index.md M Documentation/lib/payloads/index.md M Documentation/mainboard/acer/g43t-am3.md M Documentation/mainboard/amd/pademelon/pademelon.md M Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/a88xm-e.md M Documentation/mainboard/asus/f2a85-m.md M Documentation/mainboard/asus/p2b-ls.md M Documentation/mainboard/asus/p3b-f.md M Documentation/mainboard/asus/p5q.md M Documentation/mainboard/asus/p8c_ws.md M Documentation/mainboard/asus/p8h61-m_lx.md M Documentation/mainboard/asus/p8h61-m_pro.md M Documentation/mainboard/asus/p8h77-v.md M Documentation/mainboard/asus/p8z77-m.md M Documentation/mainboard/asus/p8z77-m_pro.md M Documentation/mainboard/asus/p8z77-v.md M Documentation/mainboard/asus/wifigo_v1.md M Documentation/mainboard/cavium/cn8100_sff_evb.md M Documentation/mainboard/clevo/n130wu/index.md M Documentation/mainboard/dell/optiplex_9010.md M Documentation/mainboard/facebook/fbg1701.md M Documentation/mainboard/facebook/monolith.md M Documentation/mainboard/foxconn/d41s.md M Documentation/mainboard/gigabyte/ga-g41m-es2l.md M Documentation/mainboard/gigabyte/ga-h61m-s2pv.md M Documentation/mainboard/hp/2170p.md M Documentation/mainboard/hp/2560p.md M Documentation/mainboard/hp/8760w.md M Documentation/mainboard/hp/compaq_8200_sff.md M Documentation/mainboard/hp/compaq_8300_usdt.md M Documentation/mainboard/hp/elitebook_820_g2.md M Documentation/mainboard/hp/folio_9480m.md M Documentation/mainboard/hp/z220_sff.md M Documentation/mainboard/index.md M Documentation/mainboard/intel/dg43gt.md M Documentation/mainboard/intel/dq67sw.md M Documentation/mainboard/intel/kblrvp11.md M Documentation/mainboard/kontron/mal10.md M Documentation/mainboard/lenovo/Ivy_Bridge_series.md M Documentation/mainboard/lenovo/Sandy_Bridge_series.md M Documentation/mainboard/lenovo/codenames.md M Documentation/mainboard/lenovo/ivb_internal_flashing.md M Documentation/mainboard/lenovo/montevina_series.md M Documentation/mainboard/lenovo/t410.md M Documentation/mainboard/libretrend/lt1000.md M Documentation/mainboard/msi/ms7707/ms7707.md M Documentation/mainboard/ocp/deltalake.md M Documentation/mainboard/ocp/tiogapass.md M Documentation/mainboard/opencellular/elgon.md M Documentation/mainboard/pcengines/apu1.md M Documentation/mainboard/pcengines/apu2.md M Documentation/mainboard/portwell/pq7-m107.md M Documentation/mainboard/prodrive/hermes.md M Documentation/mainboard/protectli/fw2b_fw4b.md M Documentation/mainboard/protectli/fw6.md M Documentation/mainboard/protectli/vp2420.md M Documentation/mainboard/protectli/vp46xx.md M Documentation/mainboard/purism/librem_14.md M Documentation/mainboard/purism/librem_mini.md M Documentation/mainboard/starlabs/labtop_cml.md M Documentation/mainboard/starlabs/labtop_kbl.md M Documentation/mainboard/starlabs/lite_glk.md M Documentation/mainboard/starlabs/lite_glkr.md M Documentation/mainboard/starlabs/starbook_adl.md M Documentation/mainboard/starlabs/starbook_tgl.md M Documentation/mainboard/supermicro/x10slm-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md M Documentation/mainboard/supermicro/x9sae.md M Documentation/mainboard/system76/addw1.md M Documentation/mainboard/system76/addw2.md M Documentation/mainboard/system76/addw3.md M Documentation/mainboard/system76/bonw14.md M Documentation/mainboard/system76/bonw15.md M Documentation/mainboard/system76/darp6.md M Documentation/mainboard/system76/darp7.md M Documentation/mainboard/system76/darp8.md M Documentation/mainboard/system76/darp9.md M Documentation/mainboard/system76/galp4.md M Documentation/mainboard/system76/galp5.md M Documentation/mainboard/system76/galp6.md M Documentation/mainboard/system76/galp7.md M Documentation/mainboard/system76/gaze15.md M Documentation/mainboard/system76/gaze16.md M Documentation/mainboard/system76/gaze17.md M Documentation/mainboard/system76/gaze18.md M Documentation/mainboard/system76/lemp10.md M Documentation/mainboard/system76/lemp11.md M Documentation/mainboard/system76/lemp12.md M Documentation/mainboard/system76/lemp9.md M Documentation/mainboard/system76/oryp10.md M Documentation/mainboard/system76/oryp11.md M Documentation/mainboard/system76/oryp5.md M Documentation/mainboard/system76/oryp6.md M Documentation/mainboard/system76/oryp7.md M Documentation/mainboard/system76/oryp8.md M Documentation/mainboard/system76/oryp9.md M Documentation/mainboard/system76/serw13.md M Documentation/mainboard/ti/beaglebone-black.md M Documentation/mainboard/up/squared/index.md M Documentation/northbridge/index.md M Documentation/northbridge/intel/haswell/index.md M Documentation/northbridge/intel/haswell/known-issues.md M Documentation/northbridge/intel/index.md M Documentation/northbridge/intel/sandybridge/index.md M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_features.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/northbridge/intel/sandybridge/nri_read.md M Documentation/northbridge/intel/sandybridge/nri_registers.md M Documentation/releases/boards_supported_on_branches.md M Documentation/releases/checklist.md M Documentation/releases/coreboot-4.17-relnotes.md M Documentation/releases/coreboot-4.19-relnotes.md M Documentation/releases/coreboot-4.20.1-relnotes.md M Documentation/releases/coreboot-4.21-relnotes.md M Documentation/releases/coreboot-4.22-relnotes.md M Documentation/releases/index.md M Documentation/releases/templates.md M Documentation/security/index.md M Documentation/security/memory_clearing.md M Documentation/security/vboot/index.md M Documentation/soc/amd/index.md M Documentation/soc/amd/psp_integration.md M Documentation/soc/cavium/cn81xx/index.md M Documentation/soc/cavium/index.md M Documentation/soc/index.md M Documentation/soc/intel/broadwell/index.md M Documentation/soc/intel/code_development_model/code_development_model.md M Documentation/soc/intel/fit.md M Documentation/soc/intel/fsp/index.md M Documentation/soc/intel/fsp/ppi/mp_service_ppi.md M Documentation/soc/intel/fsp/ppi/ppi.md M Documentation/soc/intel/index.md M Documentation/soc/intel/mp_init/mp_init.md M Documentation/soc/intel/xeon_sp/index.md M Documentation/soc/qualcomm/index.md M Documentation/superio/index.md M Documentation/superio/nuvoton/npcd378.md M Documentation/technotes/asan.md M Documentation/technotes/console.md M Documentation/technotes/index.md M Documentation/tutorial/flashing_firmware/index.md M Documentation/tutorial/index.md M Documentation/tutorial/part3.md M Documentation/util.md M Documentation/util/cbfstool/index.md M Documentation/util/ifdtool/index.md M Documentation/util/ifdtool/layout.md M Documentation/vendorcode/cavium/index.md M Documentation/vendorcode/eltan/index.md M Documentation/vendorcode/index.md 178 files changed, 1,259 insertions(+), 1,019 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/73158/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/73158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Gerrit-Change-Number: 73158 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock
by Tyler Wang (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80000?usp=email ) Change subject: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80000/comment/126fe483_daf1e586 : PS5, Line 8: > Please start by mentioning that the touchscreen does not work. No, the touchscreen can work. But the default setting of SOC_TCHSCR_RST is native function 1. Set SOC_TCHSCR_RST to output low to prevent it pull high unexpectedly. https://review.coreboot.org/c/coreboot/+/80000/comment/cb1edd24_5a48a55b : PS5, Line 10: Set SOC_TCHSCR_RST to output low in bootblock. > Why in bootblock? So, the delay can be reduced? It's related to CB:79571. The reason of set EN_TCHSCR_PWR to output high in bootblock is because the delay time between EN_TCHSCR_PWR high --> SOC_TCHSCR_RST high is too short to meet spec. To extend the delay time, set EN_TCHSCR_PWR to output high from romstage_gpio_table to early_gpio_table. Set SOC_TCHSCR_RST to output low in early_gpio_table is because the default setting of SOC_TCHSCR_RST is native function 1. To prevent it pull high unexpectedly, set it to output low in early_gpio_table. -- To view, visit https://review.coreboot.org/c/coreboot/+/80000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Gerrit-Change-Number: 80000 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 06:35:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Enable BT audio offload
by Subrata Banik (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Simon Yang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80001?usp=email ) Change subject: mb/google/nissa/var/anraggar: Enable BT audio offload ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e6731c8ceaad6ee58b525d4246fa769bfe1b0c7 Gerrit-Change-Number: 80001 Gerrit-PatchSet: 5 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 06:30:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/karis: Skip tcc_offset override
by Subrata Banik (Code Review) 26 Jan '24

26 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80160?usp=email ) Change subject: mb/google/rex/var/karis: Skip tcc_offset override ...................................................................... mb/google/rex/var/karis: Skip tcc_offset override This change eliminates the unnecessary override of the tcc_offset chip configuration to 10, as the default rex baseboard now handles this setting correctly. TEST=Successfully built and booted google/karis, confirming tcc_offset remains at 10. Change-Id: Ie40db1431fb0197ee360ad5656878e57f51c855b Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80160 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/variants/karis/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Tyler Wang: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index 0233762..371109a 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -77,8 +77,6 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "tcc_offset" = "10" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/80160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie40db1431fb0197ee360ad5656878e57f51c855b Gerrit-Change-Number: 80160 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Modify TCC_offset to 20
by Subrata Banik (Code Review) 26 Jan '24

26 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80159?usp=email ) Change subject: mb/google/rex/var/screebo: Modify TCC_offset to 20 ...................................................................... mb/google/rex/var/screebo: Modify TCC_offset to 20 Follow thermal team request, override tcc_offset to 20. TEST=Build and verified by thermal team using google/screebo. Change-Id: Idc76f9c0054f21f066b779e6404a1c175eb396a0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80159 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index a3ab01c..c66b5cb 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -90,6 +90,9 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # Override TCC of 90C = Tj max (110) - TCC_Offset (20) + register "tcc_offset" = "20" + # Acoustic Noise settings and slew rate configuration: # slew rate for IA Domain: Fast/8 # slew rate for GT Domain: Fast/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/80159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc76f9c0054f21f066b779e6404a1c175eb396a0 Gerrit-Change-Number: 80159 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: mb/google/rex: Organize models configs alphabetically
by Subrata Banik (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Nick Vaccaro, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80206?usp=email ) Change subject: mb/google/rex: Organize models configs alphabetically ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/80206/comment/ac8532bf_5a9a858b : PS1, Line 66: BOARD_GOOGLE_MODEL_DEKU > > What's the difference between BOARD_GOOGLE_MODEL_DEKU and BOARD_GOOGLE_DEKU ? > > > > I don't see any BOARD_GOOGLE_MODEL_XXX in brya's Kconfig, wasn't familiar with that. > > this is the easy way to avoid config duplication between each variants having QS and ES SoC. we have decided to create a model which selects all common config between QS and ES variants. @Nick, I'm marking resolve. let me know otherwise -- To view, visit https://review.coreboot.org/c/coreboot/+/80206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Gerrit-Change-Number: 80206 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 06:12:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/google/rex: Organize models configs alphabetically
by Subrata Banik (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Nick Vaccaro, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80206?usp=email ) Change subject: mb/google/rex: Organize models configs alphabetically ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I would suggest modify the create variant script too. good idea. let me talk to SIE folks. -- To view, visit https://review.coreboot.org/c/coreboot/+/80206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Gerrit-Change-Number: 80206 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 06:11:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL
by Daniel Peng (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Edward Dai, Felix Held, Ivan Chen, Karthik Ramasubramanian, Paul Menzel. Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80150?usp=email ) Change subject: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Felix, The CL review is set CR+2 over 1 day. Could you kindly help to submit if no concern? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/80150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Gerrit-Change-Number: 80150 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Edward Dai <edwarddai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Edward Dai <edwarddai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Jan 2024 06:04:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/commonlake: Re-add SATA to soc_api_name() list
by Felix Singer (Code Review) 26 Jan '24

26 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80059?usp=email ) Change subject: soc/intel/commonlake: Re-add SATA to soc_api_name() list ...................................................................... soc/intel/commonlake: Re-add SATA to soc_api_name() list Now that we've added an ACPI device for SATA, add the name back to the soc_acpi_name() list so the PEPD LPI constraint list generates a valid reference to the SATA device. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a1ba17e..0da6e40 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -94,6 +94,7 @@ case PCH_DEVFN_CSE_IDER: return "CSED"; case PCH_DEVFN_CSE_KT: return "CSKT"; case PCH_DEVFN_CSE_3: return "CSE3"; + case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; -- To view, visit https://review.coreboot.org/c/coreboot/+/80059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Gerrit-Change-Number: 80059 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/intel/commonlake: Re-add SATA to soc_api_name() list
by Felix Singer (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80059?usp=email ) Change subject: soc/intel/commonlake: Re-add SATA to soc_api_name() list ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Gerrit-Change-Number: 80059 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 05:49:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2024