coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: [Test] Follow rex0 setting
by Tyler Wang (Code Review) 26 Jan '24

26 Jan '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80215?usp=email ) Change subject: [Test] Follow rex0 setting ...................................................................... [Test] Follow rex0 setting BUG=none TEST=none Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1 --- M src/mainboard/google/rex/variants/karis/fw_config.c 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/80215/1 diff --git a/src/mainboard/google/rex/variants/karis/fw_config.c b/src/mainboard/google/rex/variants/karis/fw_config.c index 6dbf31d..c209295 100644 --- a/src/mainboard/google/rex/variants/karis/fw_config.c +++ b/src/mainboard/google/rex/variants/karis/fw_config.c @@ -35,14 +35,6 @@ }; static const struct pad_config cnvi_bt_disable_pads[] = { - /* GPP_F00 : [] ==> CNV_BRI_DT_R */ - PAD_NC(GPP_F00, NONE), - /* GPP_F01 : [] ==> CNV_BRI_RSP */ - PAD_NC(GPP_F01, NONE), - /* GPP_F02 : [] ==> CNV_RGI_DT_Rl */ - PAD_NC(GPP_F02, NONE), - /* GPP_F03 : [] ==> CNV_RGI_RSP */ - PAD_NC(GPP_F03, NONE), /* GPP_F04 : [] ==> CNV_RF_RST_L */ PAD_NC(GPP_F04, NONE), /* GPP_F05 : [] ==> CNV_CLKREQ */ @@ -54,8 +46,6 @@ PAD_NC(GPP_S01, NONE), /* GPP_S02 : [] ==> DMIC_SOC_CLK0_WLAN_PCM_OUT */ PAD_NC(GPP_S02, NONE), - /* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */ - PAD_NC(GPP_D21, NONE), }; static const struct pad_config bt_i2s_enable_pads[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/80215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1 Gerrit-Change-Number: 80215 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock
by Tyler Wang (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, Tarun. Hello David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80000?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock ...................................................................... mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock Check MTL EDS2, SOC_TCHSCR_RST(GPP_C01) default setting is NF1. Set SOC_TCHSCR_RST to output low in early_gpio_table. BUG=none TEST=Build and test on karis, touchscreen function works Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80000/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Gerrit-Change-Number: 80000 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s
by Jan Samek (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80214?usp=email ) Change subject: mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Gerrit-Change-Number: 80214 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 10:19:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
by Mario Scheithauer (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Jan Samek, Johannes Hahn, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80186?usp=email ) Change subject: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Gerrit-Change-Number: 80186 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 10:16:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s
by Mario Scheithauer (Code Review) 26 Jan '24

26 Jan '24

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80214?usp=email ) Change subject: mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s ...................................................................... mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. The patch has already been made for mc_ehl3 and serves the purpose of standardization. commit c0221aa980d3 ("mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s") Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/80214/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c index f3c5bd5..0d189a3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c @@ -82,8 +82,8 @@ cfg->t2_delay = 0x01; /* LVDS to backlight active delay: 200 ms */ cfg->t3_timing = 0x04; - /* Minimum re-power delay: 500 ms */ - cfg->t12_timing = 0x0a; + /* Minimum re-power delay: 1 s */ + cfg->t12_timing = 0x14; /* Backlight off to LVDS inactive delay: 200 ms */ cfg->t4_timing = 0x04; /* Enable LVDS to VDD inactive delay. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Gerrit-Change-Number: 80214 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: [Test] mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD
by Tyler Wang (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80213?usp=email ) Change subject: [Test] mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD ...................................................................... [Test] mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD Follow reference design rex0, tggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=none TEST=none Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/gpio.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/80213/1 diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c index 9ecc45d..6bd23ca 100644 --- a/src/mainboard/google/rex/variants/karis/gpio.c +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -367,6 +367,11 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ @@ -393,9 +398,6 @@ /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), - /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), @@ -406,6 +408,9 @@ }; static const struct pad_config romstage_gpio_table[] = { + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_B11 : [] ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* A20 : [] ==> SSD_PERST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Gerrit-Change-Number: 80213 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: [Test] Pull TCH_RST to low in bootblock
by Tyler Wang (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, Tarun. Hello David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80000?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Sumeet R Pawnikar, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: [Test] Pull TCH_RST to low in bootblock ...................................................................... [Test] Pull TCH_RST to low in bootblock Check EDS, TCH_RST default setting is NF1, set it to output low. BUG=none TEST=Build and test on karis, touchscreen function works Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80000/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Gerrit-Change-Number: 80000 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
by Jan Samek (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Johannes Hahn, Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80186?usp=email ) Change subject: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80186/comment/ec117cc5_800a1b9d : PS1, Line 10: 1 > 0 Done File src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c: https://review.coreboot.org/c/coreboot/+/80186/comment/7be8f399_9102e2b4 : PS1, Line 111: PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ : PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ > I think C6 and C7 belong to GBE1. You should be able to set both to NC. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Gerrit-Change-Number: 80186 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 10:06:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
by Jan Samek (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Jan Samek, Johannes Hahn, Werner Zeh. Hello Johannes Hahn, Mario Scheithauer, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80186?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1 ...................................................................... mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1 As a result of hardware changes on this board, the PHY previously routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake SoC. This patch changes the device PCI ID in the board's devicetree and accordingly, the GPIO configuration. BUG=none TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE are working, while PSE GbE 1 remains inactive (not listed by 'ip link') . Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c 2 files changed, 38 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/80186/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Gerrit-Change-Number: 80186 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brya: Correct EC-is-trusted logic
by Qinghong Zeng (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Reka Norman, Subrata Banik. Qinghong Zeng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80158?usp=email ) Change subject: mb/google/brya: Correct EC-is-trusted logic ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80158/comment/551e11e6_a988d084 : PS1, Line 21: firmware-DevMode > firmware_DevMode […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I308f8b36411030911c4421d80827fc49ff325a1b Gerrit-Change-Number: 80158 Gerrit-PatchSet: 2 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 26 Jan 2024 09:05:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2024