coreboot-gerrit January 2024

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[M] Change in coreboot[main]: device: Add a helper function to add a downstream bus
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Patrick Rudolph, Shuo Liu, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80210?usp=email ) Change subject: device: Add a helper function to add a downstream bus ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: > looks good to me, but i want to run a test on hardware before giving a +2 ubuntu still boots on mandolin -- To view, visit https://review.coreboot.org/c/coreboot/+/80210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Gerrit-Change-Number: 80210 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 18:59:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[NoOp] Change in blobs[main]: mb/amd/onyx: Add 1P Genoa reference board APCB blobs
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has abandoned this change. ( https://review.coreboot.org/c/blobs/+/76445?usp=email ) Change subject: mb/amd/onyx: Add 1P Genoa reference board APCB blobs ...................................................................... Abandoned replaced by CB:80204 -- To view, visit https://review.coreboot.org/c/blobs/+/76445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I0689dabd90e06190c3b3779675586d8220f7076a Gerrit-Change-Number: 76445 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: mb/amd/onyx_poc: Add and use APCB configuration data
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80204?usp=email ) Change subject: mb/amd/onyx_poc: Add and use APCB configuration data ...................................................................... mb/amd/onyx_poc: Add and use APCB configuration data This patch adds APCB blobs to the mainboard directory and it replaces CB:76445 Also this brings onyx_poc mainboard inline with how APCB are included in other AMD mainboard: commit 95d05d830162 ("mb/google/zork: Add and use APCB configuration data"), commit I352f58e0d39 ("mb/google/ skyrim: Add and use APCB configuration data") and commit I1c34528fa0f ("mb/amd/onyx_poc: Add and use APCB configuration data"). BUG=none TEST=build/boot onyx_poc Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80204 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/onyx_poc/Makefile.mk A src/mainboard/amd/onyx_poc/data.apcb A src/mainboard/amd/onyx_poc/data1.apcb A src/mainboard/amd/onyx_poc/data_rec.apcb A src/mainboard/amd/onyx_poc/data_rec1.apcb A src/mainboard/amd/onyx_poc/data_rec2.apcb 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/onyx_poc/Makefile.mk b/src/mainboard/amd/onyx_poc/Makefile.mk index 4ebcf26..5ee83d4 100644 --- a/src/mainboard/amd/onyx_poc/Makefile.mk +++ b/src/mainboard/amd/onyx_poc/Makefile.mk @@ -1,11 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin),) -APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin -APCB_SOURCES1 = $(MAINBOARD_BLOBS_DIR)/Typex60_0_1_0_Apcb.bin -APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/Typex68_0_0_0_ApcbRec.bin -APCB_SOURCES_RECOVERY1 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_8_0_ApcbRec.bin -APCB_SOURCES_RECOVERY2 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_9_0_ApcbRec.bin +ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/data.apcb),) +APCB_SOURCES = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb +APCB_SOURCES1 = $(src)/mainboard/$(MAINBOARDDIR)/data1.apcb +APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/data_rec.apcb +APCB_SOURCES_RECOVERY1 = $(src)/mainboard/$(MAINBOARDDIR)/data_rec1.apcb +APCB_SOURCES_RECOVERY2 = $(src)/mainboard/$(MAINBOARDDIR)/data_rec2.apcb else show_notices:: warn_no_apcb endif diff --git a/src/mainboard/amd/onyx_poc/data.apcb b/src/mainboard/amd/onyx_poc/data.apcb new file mode 100644 index 0000000..76219a4 --- /dev/null +++ b/src/mainboard/amd/onyx_poc/data.apcb Binary files differ diff --git a/src/mainboard/amd/onyx_poc/data1.apcb b/src/mainboard/amd/onyx_poc/data1.apcb new file mode 100644 index 0000000..015123f --- /dev/null +++ b/src/mainboard/amd/onyx_poc/data1.apcb Binary files differ diff --git a/src/mainboard/amd/onyx_poc/data_rec.apcb b/src/mainboard/amd/onyx_poc/data_rec.apcb new file mode 100644 index 0000000..ce36636 --- /dev/null +++ b/src/mainboard/amd/onyx_poc/data_rec.apcb Binary files differ diff --git a/src/mainboard/amd/onyx_poc/data_rec1.apcb b/src/mainboard/amd/onyx_poc/data_rec1.apcb new file mode 100644 index 0000000..1267ff9 --- /dev/null +++ b/src/mainboard/amd/onyx_poc/data_rec1.apcb Binary files differ diff --git a/src/mainboard/amd/onyx_poc/data_rec2.apcb b/src/mainboard/amd/onyx_poc/data_rec2.apcb new file mode 100644 index 0000000..4fb24b3 --- /dev/null +++ b/src/mainboard/amd/onyx_poc/data_rec2.apcb Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/80204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Gerrit-Change-Number: 80204 Gerrit-PatchSet: 7 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: lib/smbios: Add 32 bit entry point if below 4G
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76911?usp=email ) Change subject: lib/smbios: Add 32 bit entry point if below 4G ...................................................................... Patch Set 4: (1 comment) File src/lib/smbios.c: https://review.coreboot.org/c/coreboot/+/76911/comment/f095ffb8_539373ed : PS4, Line 1216: // only add a 32 bit entry point if SMBIOS table is below 4G > i don't see the need to change anything, but just fyi: the style guide prefers the /* */ comment sty […] meh, gerrit ate the two * -- To view, visit https://review.coreboot.org/c/coreboot/+/76911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cb426bb0c45282ed03ff4c65d15004b7f985dab Gerrit-Change-Number: 76911 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 26 Jan 2024 18:40:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib/smbios: Add 32 bit entry point if below 4G
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76911?usp=email ) Change subject: lib/smbios: Add 32 bit entry point if below 4G ...................................................................... Patch Set 4: (1 comment) File src/lib/smbios.c: https://review.coreboot.org/c/coreboot/+/76911/comment/679df5d6_390852c6 : PS4, Line 1216: // only add a 32 bit entry point if SMBIOS table is below 4G i don't see the need to change anything, but just fyi: the style guide prefers the /* */ comment style over the // style, but still allows both -- To view, visit https://review.coreboot.org/c/coreboot/+/76911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cb426bb0c45282ed03ff4c65d15004b7f985dab Gerrit-Change-Number: 76911 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 26 Jan 2024 18:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: factor out common acpi_add_ivrs_table implementation
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80208?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd: factor out common acpi_add_ivrs_table implementation ...................................................................... soc/amd: factor out common acpi_add_ivrs_table implementation Instead of open-coding this functionality in all AMD SoCs, factor it out into a common implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80208 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/cezanne/agesa_acpi.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/glinda/agesa_acpi.c M src/soc/amd/mendocino/agesa_acpi.c M src/soc/amd/phoenix/agesa_acpi.c M src/soc/amd/picasso/agesa_acpi.c 8 files changed, 21 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c index fdfe3eb..e6ccd9c 100644 --- a/src/soc/amd/cezanne/agesa_acpi.c +++ b/src/soc/amd/cezanne/agesa_acpi.c @@ -10,8 +10,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -19,11 +17,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 605c4f5..547163c 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -297,7 +297,7 @@ return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev); } -unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) +static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { unsigned long current_backup; uint64_t mmio_x30_value; @@ -433,3 +433,16 @@ return current; } + +unsigned long acpi_add_ivrs_table(unsigned long current, acpi_rsdp_t *rsdp) +{ + acpi_ivrs_t *ivrs; + + current = acpi_align_current(current); + ivrs = (acpi_ivrs_t *)current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); + + return current; +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 9c70864..a195371 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -56,6 +56,6 @@ uintptr_t current); void acpi_log_events(const struct chipset_power_state *ps); -unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current); +unsigned long acpi_add_ivrs_table(unsigned long current, acpi_rsdp_t *rsdp); #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index 7762e9d..cadf8db 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -42,12 +42,7 @@ struct acpi_rsdp *rsdp) { /* IVRS */ - acpi_ivrs_t *ivrs; - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/glinda/agesa_acpi.c b/src/soc/amd/glinda/agesa_acpi.c index 7ac19c7..f6c3c98 100644 --- a/src/soc/amd/glinda/agesa_acpi.c +++ b/src/soc/amd/glinda/agesa_acpi.c @@ -12,8 +12,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -21,11 +19,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/mendocino/agesa_acpi.c b/src/soc/amd/mendocino/agesa_acpi.c index d60a79d..1e4d600 100644 --- a/src/soc/amd/mendocino/agesa_acpi.c +++ b/src/soc/amd/mendocino/agesa_acpi.c @@ -12,8 +12,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -21,11 +19,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/phoenix/agesa_acpi.c b/src/soc/amd/phoenix/agesa_acpi.c index 251acc6..598ae81 100644 --- a/src/soc/amd/phoenix/agesa_acpi.c +++ b/src/soc/amd/phoenix/agesa_acpi.c @@ -13,8 +13,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; - /* TODO: look into adding CRAT */ /* add ALIB SSDT from HOB */ @@ -22,11 +20,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); return current; } diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 9ee977f..7a32779 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -542,7 +542,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { - acpi_ivrs_t *ivrs; struct acpi_crat_header *crat; /* CRAT */ @@ -557,11 +556,7 @@ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = acpi_align_current(current); - ivrs = (acpi_ivrs_t *)current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); + current = acpi_add_ivrs_table(current, rsdp); /* Add SRAT, MSCT, SLIT if needed in the future */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Gerrit-Change-Number: 80208 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/*/acpi: use common soc_acpi_write_tables prototype
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80221?usp=email to look at the new patch set (#3). Change subject: soc/amd/*/acpi: use common soc_acpi_write_tables prototype ...................................................................... soc/amd/*/acpi: use common soc_acpi_write_tables prototype Since the definition is the same for all SoCs, move it to the common amdblock/acpi.h header. Since the Stoneyridge northbridge.c file also includes this prototype, remove the static attribute of the function there. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib9aa215f2b4ba58f43fed2c751d989f1719e0a17 --- M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/genoa_poc/chip.c M src/soc/amd/genoa_poc/include/soc/acpi.h M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/include/soc/acpi.h M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/include/soc/acpi.h M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/include/soc/acpi.h M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/northbridge.c 14 files changed, 11 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/80221/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9aa215f2b4ba58f43fed2c751d989f1719e0a17 Gerrit-Change-Number: 80221 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/common/include/acpi: add missing device/device.h include
by Matt DeVillier (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80220?usp=email ) Change subject: soc/amd/common/include/acpi: add missing device/device.h include ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5245fa132ec9b84bbc483a31788bcd6fac0736e1 Gerrit-Change-Number: 80220 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Jan 2024 17:42:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/fsp: use expected types for add_agesa_fsp_acpi_table
by Matt DeVillier (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80219?usp=email ) Change subject: soc/amd/common/fsp: use expected types for add_agesa_fsp_acpi_table ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9f770b1d847ea28e4dbd96298a723d794b91a02 Gerrit-Change-Number: 80219 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Jan 2024 17:42:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd: use expected function signature for soc_acpi_write_tables
by Matt DeVillier (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80218?usp=email ) Change subject: soc/amd: use expected function signature for soc_acpi_write_tables ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee45badb904fa20c6db146edbc00c40ca09361d1 Gerrit-Change-Number: 80218 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Jan 2024 17:41:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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