coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by David Ruth (Code Review) 27 Jan '24

27 Jan '24

Attention is currently required from: Arthur Heymans, Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Paul Menzel, Subrata Banik, Subrata Banik, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80170?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Arthur Heymans, Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Add MTCL function to ACPI SSDT tables The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Adds the mtcl.c file to abstract functionality related to reading the binary file that defines the MTCL, and verifying that the format is one intended to be handled by this implementation. * Reads a binary file called "wifi_mtcl.hex" in cbfs * Verifies that the format matches a supported value * Writes the verified content as appropriate AML. * Adds config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Adds config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Adds config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.hex" * Adds functionality to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for WiFi devices when the above flags are enabled BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.hex blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth(a)chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 --- M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.inc M src/drivers/wifi/generic/acpi.c A src/drivers/wifi/generic/mtcl.c M src/include/device/pci_ids.h A src/include/mtcl.h 6 files changed, 217 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 9 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: malloc/memalign: Return NULL if the request is too large
by Julius Werner (Code Review) 27 Jan '24

27 Jan '24

Attention is currently required from: Brandon Weeks, Patrick Georgi. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80226?usp=email ) Change subject: malloc/memalign: Return NULL if the request is too large ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80226/comment/0392439b_5ae4ce77 : PS1, Line 18: nit: Maybe mention that callers that explicitly want the `die()` behavior should be using the `xmalloc()` macro instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/80226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262fbad7daae0ca3aab583fda00665a2592deaa8 Gerrit-Change-Number: 80226 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Comment-Date: Sat, 27 Jan 2024 00:05:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80150?usp=email ) Change subject: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Hi Felix, The CL review is set CR+2 over 1 day. […] done fyi: i use this serach in gerrit to see which patches can be submitted after having another look at them: status:open label:All-Comments-Resolved=ok age:1d label:Code-Review=2 label:Verified=1 is:mergeable -label:Verified-1 -label:Code-Review<0 project:coreboot so i only see patches on that list that haven't had any change, review or message within the last day. haven't found a filter to show patches where the last patch set has been pushed at least a day ago and that also match the other conditions in there, so pinging me on a patch might result in me not seeing that one on my list the next day. i also had to disable email notifications from gerrit, since the amount of emails i got from gerrit became way too large. saw the patch in my gerrit dashboard view when i was looking for another patch in there and didn't see it yet in my search for patches that can be submitted -- To view, visit https://review.coreboot.org/c/coreboot/+/80150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Gerrit-Change-Number: 80150 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Edward Dai <edwarddai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 23:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80150?usp=email ) Change subject: mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL ...................................................................... mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCL Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:320137193 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80150 Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/dedede/variants/galtic/memory/Makefile.mk M src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 3 deletions(-) Approvals: Daniel Peng: Looks good to me, but someone else must approve build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.mk b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.mk index b4a4e64..5154e6e 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.mk @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build591443712/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +# /tmp/go-build378545252/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt index 73b84c1..8c8acfa 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build591443712/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +# /tmp/go-build378545252/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) @@ -9,3 +9,4 @@ K4U6E3S4AA-MGCR 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) +K4U6E3S4AB-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt index 816c1b0..17b8266 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -9,3 +9,4 @@ K4U6E3S4AA-MGCR MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE +K4U6E3S4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/80150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Gerrit-Change-Number: 80150 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Edward Dai <edwarddai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brox: Enable Touchscreen
by Shelley Chen (Code Review) 26 Jan '24

26 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79895?usp=email ) Change subject: mb/google/brox: Enable Touchscreen ...................................................................... mb/google/brox: Enable Touchscreen BUG=b:300690448,b:319393777 BRANCH=None TEST=tested on a device with i2cdetect Also tested with evtest and make sure Wacom is listed Change-Id: I4f528b0d778c8c4a4e83774d5c167ccb2d6afd9a Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79895 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 2 files changed, 21 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index be31df6..8ea21b0 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -168,6 +168,26 @@ device i2c 0x15 on end end end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""WACOM4A0D"" + register "generic.desc" = ""BOE Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" + register "generic.reset_delay_ms" = "100" + register "generic.reset_off_delay_ms" = "10" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "generic.stop_off_delay_ms" = "100" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x0A on + end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index da70da1..5432bd1 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -244,7 +244,7 @@ /* GPP_F6 : [NF1: CNV_PA_BLANKING NF6: USB_C_GPP_F6] ==> SOC_GPP_F6 (NC)*/ PAD_NC(GPP_F6, NONE), /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_F7, 0, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_F9, 1, DEEP), /* GPP_F10 : GPP_F10 ==> GPP_F10_STRAP (NC) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f528b0d778c8c4a4e83774d5c167ccb2d6afd9a Gerrit-Change-Number: 79895 Gerrit-PatchSet: 25 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Remove CNVi Bluetooth
by Shelley Chen (Code Review) 26 Jan '24

26 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80211?usp=email ) Change subject: mb/google/brox: Remove CNVi Bluetooth ...................................................................... mb/google/brox: Remove CNVi Bluetooth This is causing an assertion error on the devices that don't have CNVi enabled because CNVi is hidden behind a FW_CONFIG flag in the overridetree now. BUG=b:319188820 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure we can boot to kernel on device. Change-Id: Ifcfbc04825d4d4e7f2874a4c52f9c5cf3e657856 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80211 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index fd2c8ed..be31df6 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -23,9 +23,6 @@ register "tcc_offset" = "10" # TCC of 90 - # Enable CNVi BT - register "cnvi_bt_core" = "true" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcfbc04825d4d4e7f2874a4c52f9c5cf3e657856 Gerrit-Change-Number: 80211 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/brox: Enable HDA Codec ALC256
by Shelley Chen (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Paul Menzel, Poornima Tom, Vamshi Krishna Gopal. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79723?usp=email ) Change subject: mb/google/brox: Enable HDA Codec ALC256 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79723?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Gerrit-Change-Number: 79723 Gerrit-PatchSet: 6 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 23:05:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/*/acpi: drop CRAT TODO
by Matt DeVillier (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80227?usp=email ) Change subject: soc/amd/*/acpi: drop CRAT TODO ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 Gerrit-Change-Number: 80227 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Jan 2024 22:28:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/*/acpi: drop CRAT TODO
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80227?usp=email ) Change subject: soc/amd/*/acpi: drop CRAT TODO ...................................................................... soc/amd/*/acpi: drop CRAT TODO The CRAT (Component Resource Attribute Table) isn't used on the APUs from Renoir on and has also been marked as deprecated in version 6.5 of the ACPI specification. So remove the 'TODO: look into adding CRAT' comment from all SoCs from Renoir/Cezanne on. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/80227/1 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index c99159a..f60512d 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -58,8 +58,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 8b6031c..eb1d478 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -61,8 +61,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 898e75e..e7f0d96 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -60,8 +60,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index a8be10e..a6482ee 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -61,8 +61,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); -- To view, visit https://review.coreboot.org/c/coreboot/+/80227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 Gerrit-Change-Number: 80227 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/common: Add lunarlake device IDs
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79900?usp=email ) Change subject: soc/intel/common: Add lunarlake device IDs ...................................................................... soc/intel/common: Add lunarlake device IDs Added Lunar Lake device IDs the device specific functions Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh(a)intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/drivers/intel/ish/ish.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/ipu/ipu.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xhci/xhci.c 21 files changed, 62 insertions(+), 0 deletions(-) Approvals: Wonkyu Kim: Looks good to me, approved Bora Guvendik: Looks good to me, approved Saurabh Mishra: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index d1b85f5..9711632 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -79,6 +79,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_ISHB, PCI_DID_INTEL_MTL_ISHB, PCI_DID_INTEL_CNL_ISHB, PCI_DID_INTEL_CML_ISHB, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index cb09385..bd43545 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -32,6 +32,7 @@ }; static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 8a92332..6d7569d 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1477,6 +1477,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_GLK_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 5419a29..1f11df0 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -13,6 +13,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_AUDIO_1, + PCI_DID_INTEL_LNL_AUDIO_2, + PCI_DID_INTEL_LNL_AUDIO_3, + PCI_DID_INTEL_LNL_AUDIO_4, + PCI_DID_INTEL_LNL_AUDIO_5, + PCI_DID_INTEL_LNL_AUDIO_6, + PCI_DID_INTEL_LNL_AUDIO_7, + PCI_DID_INTEL_LNL_AUDIO_8, PCI_DID_INTEL_MTL_AUDIO_1, PCI_DID_INTEL_MTL_AUDIO_2, PCI_DID_INTEL_MTL_AUDIO_3, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 621dc96..74449df 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -563,6 +563,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_HWSEQ_SPI, PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI, PCI_DID_INTEL_ADP_P_HWSEQ_SPI, PCI_DID_INTEL_ADP_S_HWSEQ_SPI, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 9b780da..ef4b269 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -332,6 +332,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_M_GT2, PCI_DID_INTEL_RPL_U_GT1, PCI_DID_INTEL_RPL_U_GT2, PCI_DID_INTEL_RPL_U_GT3, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index fdd78fc..44c0341 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -21,6 +21,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_AUDIO_1, + PCI_DID_INTEL_LNL_AUDIO_2, + PCI_DID_INTEL_LNL_AUDIO_3, + PCI_DID_INTEL_LNL_AUDIO_4, + PCI_DID_INTEL_LNL_AUDIO_5, + PCI_DID_INTEL_LNL_AUDIO_6, + PCI_DID_INTEL_LNL_AUDIO_7, + PCI_DID_INTEL_LNL_AUDIO_8, PCI_DID_INTEL_MTL_AUDIO_1, PCI_DID_INTEL_MTL_AUDIO_2, PCI_DID_INTEL_MTL_AUDIO_3, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 141b66e..c0f0b6e0 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -174,6 +174,12 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_I2C0, + PCI_DID_INTEL_LNL_I2C1, + PCI_DID_INTEL_LNL_I2C2, + PCI_DID_INTEL_LNL_I2C3, + PCI_DID_INTEL_LNL_I2C4, + PCI_DID_INTEL_LNL_I2C5, PCI_DID_INTEL_MTL_I2C0, PCI_DID_INTEL_MTL_I2C1, PCI_DID_INTEL_MTL_I2C2, diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c index cd0293d..b2d3904 100644 --- a/src/soc/intel/common/block/ipu/ipu.c +++ b/src/soc/intel/common/block/ipu/ipu.c @@ -12,6 +12,7 @@ }; static const uint16_t pci_device_ids[] = { + PCI_DID_INTEL_LNL_IPU, PCI_DID_INTEL_RPL_IPU, PCI_DID_INTEL_MTL_IPU, PCI_DID_INTEL_TGL_IPU, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 0de3154..6d3b90f 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -138,6 +138,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_ESPI_0, + PCI_DID_INTEL_LNL_ESPI_1, + PCI_DID_INTEL_LNL_ESPI_2, + PCI_DID_INTEL_LNL_ESPI_3, + PCI_DID_INTEL_LNL_ESPI_4, + PCI_DID_INTEL_LNL_ESPI_5, + PCI_DID_INTEL_LNL_ESPI_6, + PCI_DID_INTEL_LNL_ESPI_7, PCI_DID_INTEL_MTL_ESPI_0, PCI_DID_INTEL_MTL_ESPI_1, PCI_DID_INTEL_MTL_ESPI_2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index dea1c78..04318c8 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -138,6 +138,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, PCI_DID_INTEL_RPP_P_P2SB, PCI_DID_INTEL_APL_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index d86ba83..5c6681d 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -67,6 +67,14 @@ }; static const unsigned short pcie_device_ids[] = { + PCI_DID_INTEL_LNL_PCIE_RP1, + PCI_DID_INTEL_LNL_PCIE_RP2, + PCI_DID_INTEL_LNL_PCIE_RP3, + PCI_DID_INTEL_LNL_PCIE_RP4, + PCI_DID_INTEL_LNL_PCIE_RP5, + PCI_DID_INTEL_LNL_PCIE_RP6, + PCI_DID_INTEL_LNL_PCIE_RP7, + PCI_DID_INTEL_LNL_PCIE_RP8, PCI_DID_INTEL_RPL_P_PCIE_RP1, PCI_DID_INTEL_RPL_P_PCIE_RP2, PCI_DID_INTEL_RPL_P_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 70e1449..ca575ff 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -111,6 +111,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_PMC, PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ce98505..4f2ed36 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -50,6 +50,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_S_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index b95ac96..d1063f1 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -123,6 +123,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_GSPI0, + PCI_DID_INTEL_LNL_GSPI1, + PCI_DID_INTEL_LNL_GSPI2, PCI_DID_INTEL_MTL_GSPI0, PCI_DID_INTEL_MTL_GSPI1, PCI_DID_INTEL_MTL_GSPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index a6f95e2..cd8c3fd 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -33,6 +33,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_SRAM, PCI_DID_INTEL_MTL_SOC_SRAM, PCI_DID_INTEL_MTL_IOE_M_SRAM, PCI_DID_INTEL_MTL_IOE_P_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 24c5a7e..c2d561a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -336,6 +336,7 @@ }; static const unsigned short systemagent_ids[] = { + PCI_DID_INTEL_LNL_M_ID, PCI_DID_INTEL_MTL_M_ID, PCI_DID_INTEL_MTL_P_ID_1, PCI_DID_INTEL_MTL_P_ID_2, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 9123498..533fbee 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -309,6 +309,7 @@ static const char *uart_acpi_name(const struct device *dev) { switch (dev->device) { + case PCI_DID_INTEL_LNL_UART0: case PCI_DID_INTEL_ADP_P_UART0: case PCI_DID_INTEL_APL_UART0: case PCI_DID_INTEL_GLK_UART0: @@ -316,6 +317,7 @@ case PCI_DID_INTEL_SPT_H_UART0: case PCI_DID_INTEL_CNP_H_UART0: return "UAR0"; + case PCI_DID_INTEL_LNL_UART1: case PCI_DID_INTEL_ADP_P_UART1: case PCI_DID_INTEL_APL_UART1: case PCI_DID_INTEL_GLK_UART1: @@ -323,6 +325,7 @@ case PCI_DID_INTEL_SPT_H_UART1: case PCI_DID_INTEL_CNP_H_UART1: return "UAR1"; + case PCI_DID_INTEL_LNL_UART2: case PCI_DID_INTEL_ADP_P_UART2: case PCI_DID_INTEL_APL_UART2: case PCI_DID_INTEL_GLK_UART2: @@ -349,6 +352,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_UART0, + PCI_DID_INTEL_LNL_UART1, + PCI_DID_INTEL_LNL_UART2, PCI_DID_INTEL_MTL_UART0, PCI_DID_INTEL_MTL_UART1, PCI_DID_INTEL_MTL_UART2, diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index a90a35a..a47bb9b 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -52,6 +52,8 @@ #endif static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_TBT_DMA0, + PCI_DID_INTEL_LNL_TBT_DMA1, PCI_DID_INTEL_RPL_TBT_DMA0, PCI_DID_INTEL_RPL_TBT_DMA1, PCI_DID_INTEL_MTL_M_TBT_DMA0, diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index d1a2dc6..4912e1a 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -26,6 +26,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_TCSS_XHCI, PCI_DID_INTEL_RPP_P_TCSS_XHCI, PCI_DID_INTEL_MTL_M_TCSS_XHCI, PCI_DID_INTEL_MTL_P_TCSS_XHCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 9cc4211..ff6fbf0 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_CNL_LP_XHCI, -- To view, visit https://review.coreboot.org/c/coreboot/+/79900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Gerrit-Change-Number: 79900 Gerrit-PatchSet: 4 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: merged

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