coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: payloads/Kconfig: Add flat binary as payload option
by Maximilian Brune (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Arthur Heymans. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80191?usp=email ) Change subject: payloads/Kconfig: Add flat binary as payload option ...................................................................... Patch Set 2: (1 comment) File payloads/Kconfig: https://review.coreboot.org/c/coreboot/+/80191/comment/16ba4328_185a0e7a : PS2, Line 96: config PAYLOAD_IS_FLAT_BINARY > Why do you need a separate Kconfig option? Won't PAYLOAD_FLAT_BINARY do? PAYLOAD_UBOOT also uses a flat binary and selects PAYLOAD_IS_FLAT_BINARY. Therefore it needs two separate options. -- To view, visit https://review.coreboot.org/c/coreboot/+/80191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a Gerrit-Change-Number: 80191 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 28 Jan 2024 08:06:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: include/device/device.h: Remove comma from CHIP_NAME() macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Hello Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80228?usp=email to look at the new patch set (#5). Change subject: include/device/device.h: Remove comma from CHIP_NAME() macro ...................................................................... include/device/device.h: Remove comma from CHIP_NAME() macro Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A good example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/cpu/amd/pi/00730F01/chip_name.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/slot_1/slot_1.c M src/cpu/power9/power9.c M src/cpu/qemu-power8/qemu.c M src/cpu/qemu-x86/qemu.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/crb/tis.c M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/alc1015/alc1015.c M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub_lv2/lv2.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/generic/nau8315/nau8315.c M src/drivers/genesyslogic/gl9750/gl9750.c M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9763e/gl9763e.c M src/drivers/gfx/generic/generic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/ck505/ck505.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/cs42l42/cs42l42.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/lm96000/lm96000.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/pca9538/pca9538.c M src/drivers/i2c/pcf8523/pcf8523.c M src/drivers/i2c/pi608gp/pi608gp.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/i2c/tas5825m/tas5825m.c M src/drivers/i2c/tpm/chip.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/pmc_mux/mux.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/net/atl1e.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pc80/tpm/tis.c M src/drivers/pcie/generic/generic.c M src/drivers/pcie/rtd3/device/chip.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/secunet/dmi/smbios.c M src/drivers/sof/sof.c M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc5682/alc5682.c M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/cs42l42/cs42l42.c M src/drivers/soundwire/max98363/max98363.c M src/drivers/soundwire/max98373/max98373.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/wifi/generic/generic.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/51nb/npce985la0dx/npce985la0dx.c M src/ec/clevo/it5570e/ec.c M src/ec/compal/ene932/ec.c M src/ec/dell/mec5035/mec5035.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/google/chromeec/mux/mux.c M src/ec/google/wilco/chip.c M src/ec/hp/kbc1126/ec.c M src/ec/kontron/it8516e/ec.c M src/ec/kontron/kempld/kempld.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c M src/include/device/device.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/chip.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c M src/soc/amd/stoneyridge/chip.c M src/soc/cavium/cn81xx/soc.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8186/soc.c M src/soc/mediatek/mt8188/soc.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/soc.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra210/soc.c M src/soc/qualcomm/ipq40xx/soc.c M src/soc/qualcomm/ipq806x/soc.c M src/soc/qualcomm/qcs405/soc.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/sifive/fu540/chip.c M src/soc/ti/am335x/soc.c M src/soc/ucb/riscv/chip.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/superio/aspeed/ast2400/superio.c M src/superio/common/generic.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f81803a/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8784e/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5539d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6687d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/smsc/sch555x/ramstage.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 236 files changed, 238 insertions(+), 237 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/80228/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Gerrit-Change-Number: 80228 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger 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[S] Change in coreboot[main]: payloads/Kconfig: Add flat binary as payload option
by Arthur Heymans (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Maximilian Brune. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80191?usp=email ) Change subject: payloads/Kconfig: Add flat binary as payload option ...................................................................... Patch Set 2: (1 comment) File payloads/Kconfig: https://review.coreboot.org/c/coreboot/+/80191/comment/ff1c6779_fe66c47f : PS2, Line 96: config PAYLOAD_IS_FLAT_BINARY Why do you need a separate Kconfig option? Won't PAYLOAD_FLAT_BINARY do? -- To view, visit https://review.coreboot.org/c/coreboot/+/80191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a Gerrit-Change-Number: 80191 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sun, 28 Jan 2024 03:15:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: include/device/device.h: Remove comma from CHIP_NAME macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Hello Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80228?usp=email to look at the new patch set (#4). Change subject: include/device/device.h: Remove comma from CHIP_NAME macro ...................................................................... include/device/device.h: Remove comma from CHIP_NAME macro Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A good example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/cpu/amd/pi/00730F01/chip_name.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/slot_1/slot_1.c M src/cpu/power9/power9.c M src/cpu/qemu-power8/qemu.c M src/cpu/qemu-x86/qemu.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/crb/tis.c M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/alc1015/alc1015.c M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub_lv2/lv2.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/generic/nau8315/nau8315.c M src/drivers/genesyslogic/gl9750/gl9750.c M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9763e/gl9763e.c M src/drivers/gfx/generic/generic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/ck505/ck505.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/cs42l42/cs42l42.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/lm96000/lm96000.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/pca9538/pca9538.c M src/drivers/i2c/pcf8523/pcf8523.c M src/drivers/i2c/pi608gp/pi608gp.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/i2c/tas5825m/tas5825m.c M src/drivers/i2c/tpm/chip.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/pmc_mux/mux.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/net/atl1e.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pc80/tpm/tis.c M src/drivers/pcie/generic/generic.c M src/drivers/pcie/rtd3/device/chip.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/secunet/dmi/smbios.c M src/drivers/sof/sof.c M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc5682/alc5682.c M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/cs42l42/cs42l42.c M src/drivers/soundwire/max98363/max98363.c M src/drivers/soundwire/max98373/max98373.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/wifi/generic/generic.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/51nb/npce985la0dx/npce985la0dx.c M src/ec/clevo/it5570e/ec.c M src/ec/compal/ene932/ec.c M src/ec/dell/mec5035/mec5035.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/google/chromeec/mux/mux.c M src/ec/google/wilco/chip.c M src/ec/hp/kbc1126/ec.c M src/ec/kontron/it8516e/ec.c M src/ec/kontron/kempld/kempld.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c M src/include/device/device.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/chip.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c M src/soc/amd/stoneyridge/chip.c M src/soc/cavium/cn81xx/soc.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8186/soc.c M src/soc/mediatek/mt8188/soc.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/soc.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra210/soc.c M src/soc/qualcomm/ipq40xx/soc.c M src/soc/qualcomm/ipq806x/soc.c M src/soc/qualcomm/qcs405/soc.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/sifive/fu540/chip.c M src/soc/ti/am335x/soc.c M src/soc/ucb/riscv/chip.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/superio/aspeed/ast2400/superio.c M src/superio/common/generic.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f81803a/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8784e/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5539d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6687d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/smsc/sch555x/ramstage.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 236 files changed, 238 insertions(+), 237 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/80228/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Gerrit-Change-Number: 80228 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> 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1 0

[L] Change in coreboot[main]: include/device: Remove comma from CHIP_NAME macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Hello Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80228?usp=email to look at the new patch set (#3). Change subject: include/device: Remove comma from CHIP_NAME macro ...................................................................... include/device: Remove comma from CHIP_NAME macro Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A good example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/cpu/amd/pi/00730F01/chip_name.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/slot_1/slot_1.c M src/cpu/power9/power9.c M src/cpu/qemu-power8/qemu.c M src/cpu/qemu-x86/qemu.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/crb/tis.c M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/alc1015/alc1015.c M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub_lv2/lv2.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/generic/nau8315/nau8315.c M src/drivers/genesyslogic/gl9750/gl9750.c M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9763e/gl9763e.c M src/drivers/gfx/generic/generic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/ck505/ck505.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/cs42l42/cs42l42.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/lm96000/lm96000.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/pca9538/pca9538.c M src/drivers/i2c/pcf8523/pcf8523.c M src/drivers/i2c/pi608gp/pi608gp.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/i2c/tas5825m/tas5825m.c M src/drivers/i2c/tpm/chip.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/pmc_mux/mux.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/net/atl1e.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pc80/tpm/tis.c M src/drivers/pcie/generic/generic.c M src/drivers/pcie/rtd3/device/chip.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/secunet/dmi/smbios.c M src/drivers/sof/sof.c M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc5682/alc5682.c M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/cs42l42/cs42l42.c M src/drivers/soundwire/max98363/max98363.c M src/drivers/soundwire/max98373/max98373.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/wifi/generic/generic.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/51nb/npce985la0dx/npce985la0dx.c M src/ec/clevo/it5570e/ec.c M src/ec/compal/ene932/ec.c M src/ec/dell/mec5035/mec5035.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/google/chromeec/mux/mux.c M src/ec/google/wilco/chip.c M src/ec/hp/kbc1126/ec.c M src/ec/kontron/it8516e/ec.c M src/ec/kontron/kempld/kempld.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c M src/include/device/device.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/chip.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c M src/soc/amd/stoneyridge/chip.c M src/soc/cavium/cn81xx/soc.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8186/soc.c M src/soc/mediatek/mt8188/soc.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/soc.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra210/soc.c M src/soc/qualcomm/ipq40xx/soc.c M src/soc/qualcomm/ipq806x/soc.c M src/soc/qualcomm/qcs405/soc.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/sifive/fu540/chip.c M src/soc/ti/am335x/soc.c M src/soc/ucb/riscv/chip.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/superio/aspeed/ast2400/superio.c M src/superio/common/generic.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f81803a/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8784e/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5539d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6687d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/smsc/sch555x/ramstage.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 236 files changed, 238 insertions(+), 237 deletions(-) git pull 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1 0

[L] Change in coreboot[main]: include/device: Remove comma from CHIP_NAME macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Hello Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80228?usp=email to look at the new patch set (#2). Change subject: include/device: Remove comma from CHIP_NAME macro ...................................................................... include/device: Remove comma from CHIP_NAME macro Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A good example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 seperate members of the same struct. Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/cpu/amd/pi/00730F01/chip_name.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/slot_1/slot_1.c M src/cpu/power9/power9.c M src/cpu/qemu-power8/qemu.c M src/cpu/qemu-x86/qemu.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/crb/tis.c M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/alc1015/alc1015.c M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub_lv2/lv2.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/generic/nau8315/nau8315.c M src/drivers/genesyslogic/gl9750/gl9750.c M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9763e/gl9763e.c M src/drivers/gfx/generic/generic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/ck505/ck505.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/cs42l42/cs42l42.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/lm96000/lm96000.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/pca9538/pca9538.c M src/drivers/i2c/pcf8523/pcf8523.c M src/drivers/i2c/pi608gp/pi608gp.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/i2c/tas5825m/tas5825m.c M src/drivers/i2c/tpm/chip.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/pmc_mux/mux.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/net/atl1e.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pc80/tpm/tis.c M src/drivers/pcie/generic/generic.c M src/drivers/pcie/rtd3/device/chip.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/secunet/dmi/smbios.c M src/drivers/sof/sof.c M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc5682/alc5682.c M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/cs42l42/cs42l42.c M src/drivers/soundwire/max98363/max98363.c M src/drivers/soundwire/max98373/max98373.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/wifi/generic/generic.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/51nb/npce985la0dx/npce985la0dx.c M src/ec/clevo/it5570e/ec.c M src/ec/compal/ene932/ec.c M src/ec/dell/mec5035/mec5035.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/google/chromeec/mux/mux.c M src/ec/google/wilco/chip.c M src/ec/hp/kbc1126/ec.c M src/ec/kontron/it8516e/ec.c M src/ec/kontron/kempld/kempld.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c M src/include/device/device.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/chip.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c M src/soc/amd/stoneyridge/chip.c M src/soc/cavium/cn81xx/soc.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8186/soc.c M src/soc/mediatek/mt8188/soc.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/soc.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra210/soc.c M src/soc/qualcomm/ipq40xx/soc.c M src/soc/qualcomm/ipq806x/soc.c M src/soc/qualcomm/qcs405/soc.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/sifive/fu540/chip.c M src/soc/ti/am335x/soc.c M src/soc/ucb/riscv/chip.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/superio/aspeed/ast2400/superio.c M src/superio/common/generic.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f81803a/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8784e/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5539d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6687d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/smsc/sch555x/ramstage.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 236 files changed, 238 insertions(+), 237 deletions(-) git pull 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1 0

[L] Change in coreboot[main]: include/device: Remove comma from CHIP_NAME macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

1 0

[L] Change in coreboot[main]: include/device: Remove comma from CHIP_NAME macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80228?usp=email ) Change subject: include/device: Remove comma from CHIP_NAME macro ...................................................................... include/device: Remove comma from CHIP_NAME macro Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A good example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 seperate members. Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/cpu/amd/pi/00730F01/chip_name.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/slot_1/slot_1.c M src/cpu/power9/power9.c M src/cpu/qemu-power8/qemu.c M src/cpu/qemu-x86/qemu.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/crb/tis.c M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/alc1015/alc1015.c M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub_lv2/lv2.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/generic/nau8315/nau8315.c M src/drivers/genesyslogic/gl9750/gl9750.c M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9763e/gl9763e.c M src/drivers/gfx/generic/generic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/ck505/ck505.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/cs42l42/cs42l42.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/lm96000/lm96000.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/pca9538/pca9538.c M src/drivers/i2c/pcf8523/pcf8523.c M src/drivers/i2c/pi608gp/pi608gp.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/i2c/tas5825m/tas5825m.c M src/drivers/i2c/tpm/chip.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/pmc_mux/mux.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/net/atl1e.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pc80/tpm/tis.c M src/drivers/pcie/generic/generic.c M src/drivers/pcie/rtd3/device/chip.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/secunet/dmi/smbios.c M src/drivers/sof/sof.c M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc5682/alc5682.c M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/cs42l42/cs42l42.c M src/drivers/soundwire/max98363/max98363.c M src/drivers/soundwire/max98373/max98373.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/wifi/generic/generic.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/51nb/npce985la0dx/npce985la0dx.c M src/ec/clevo/it5570e/ec.c M src/ec/compal/ene932/ec.c M src/ec/dell/mec5035/mec5035.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/google/chromeec/mux/mux.c M src/ec/google/wilco/chip.c M src/ec/hp/kbc1126/ec.c M src/ec/kontron/it8516e/ec.c M src/ec/kontron/kempld/kempld.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c M src/include/device/device.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/chip.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c M src/soc/amd/stoneyridge/chip.c M src/soc/cavium/cn81xx/soc.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8186/soc.c M src/soc/mediatek/mt8188/soc.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/soc.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra210/soc.c M src/soc/qualcomm/ipq40xx/soc.c M src/soc/qualcomm/ipq806x/soc.c M src/soc/qualcomm/qcs405/soc.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/sifive/fu540/chip.c M src/soc/ti/am335x/soc.c M src/soc/ucb/riscv/chip.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/superio/aspeed/ast2400/superio.c M src/superio/common/generic.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f81803a/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8784e/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5539d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6687d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/smsc/sch555x/ramstage.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 236 files changed, 238 insertions(+), 237 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/80228/1 diff --git a/src/cpu/amd/pi/00730F01/chip_name.c b/src/cpu/amd/pi/00730F01/chip_name.c index d5955cc..cc997a2 100644 --- a/src/cpu/amd/pi/00730F01/chip_name.c +++ b/src/cpu/amd/pi/00730F01/chip_name.c @@ -3,5 +3,5 @@ #include <device/device.h> struct chip_operations cpu_amd_pi_00730F01_ops = { - CHIP_NAME("AMD CPU Family 16h Model 30h-3Fh") + CHIP_NAME("AMD CPU Family 16h Model 30h-3Fh"), }; diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 3727d8a..0ea97e3 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -364,5 +364,5 @@ } struct chip_operations cpu_intel_haswell_ops = { - CHIP_NAME("Intel Haswell CPU") + CHIP_NAME("Intel Haswell CPU"), }; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 315e7c3..90c5f91 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -277,5 +277,5 @@ }; struct chip_operations cpu_intel_model_1067x_ops = { - CHIP_NAME("Intel Penryn CPU") + CHIP_NAME("Intel Penryn CPU"), }; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index d8fef62..f37dcc2 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -242,5 +242,5 @@ } struct chip_operations cpu_intel_model_2065x_ops = { - CHIP_NAME("Intel Arrandale CPU") + CHIP_NAME("Intel Arrandale CPU"), }; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f3bd67b..b1c4114 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -380,5 +380,5 @@ } struct chip_operations cpu_intel_model_206ax_ops = { - CHIP_NAME("Intel SandyBridge/IvyBridge CPU") + CHIP_NAME("Intel SandyBridge/IvyBridge CPU"), }; diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c index 0f5b157..4ec0ec7 100644 --- a/src/cpu/intel/slot_1/slot_1.c +++ b/src/cpu/intel/slot_1/slot_1.c @@ -3,5 +3,5 @@ #include <device/device.h> struct chip_operations cpu_intel_slot_1_ops = { - CHIP_NAME("Slot 1 CPU") + CHIP_NAME("Slot 1 CPU"), }; diff --git a/src/cpu/power9/power9.c b/src/cpu/power9/power9.c index fd33ff2..8ce425a 100644 --- a/src/cpu/power9/power9.c +++ b/src/cpu/power9/power9.c @@ -16,5 +16,5 @@ }; struct chip_operations cpu_power8_qemu_ops = { - CHIP_NAME("POWER9 CPU") + CHIP_NAME("POWER9 CPU"), }; diff --git a/src/cpu/qemu-power8/qemu.c b/src/cpu/qemu-power8/qemu.c index 2da3c9f..1183f46 100644 --- a/src/cpu/qemu-power8/qemu.c +++ b/src/cpu/qemu-power8/qemu.c @@ -21,5 +21,5 @@ }; struct chip_operations cpu_power8_qemu_ops = { - CHIP_NAME("QEMU POWER8 CPU") + CHIP_NAME("QEMU POWER8 CPU"), }; diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 06696c8..7d01635 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -22,5 +22,5 @@ }; struct chip_operations cpu_qemu_x86_ops = { - CHIP_NAME("QEMU x86 CPU") + CHIP_NAME("QEMU x86 CPU"), }; diff --git a/src/drivers/acpi/thermal_zone/thermal_zone.c b/src/drivers/acpi/thermal_zone/thermal_zone.c index 192e2e6..417664f 100644 --- a/src/drivers/acpi/thermal_zone/thermal_zone.c +++ b/src/drivers/acpi/thermal_zone/thermal_zone.c @@ -126,6 +126,6 @@ } struct chip_operations drivers_acpi_thermal_zone_ops = { - CHIP_NAME("ACPI Thermal Zone") + CHIP_NAME("ACPI Thermal Zone"), .enable_dev = thermal_zone_enable_dev, }; diff --git a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c index 7bd256d..2615cdd 100644 --- a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c +++ b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c @@ -95,6 +95,6 @@ } struct chip_operations drivers_amd_i2s_machine_dev_ops = { - CHIP_NAME("AMD I2S Machine Device") + CHIP_NAME("AMD I2S Machine Device"), .enable_dev = i2s_machine_dev_enable }; diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 2c9128e..64292a9 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -206,6 +206,6 @@ } struct chip_operations drivers_crb_ops = { - CHIP_NAME("CRB TPM") + CHIP_NAME("CRB TPM"), .enable_dev = enable_dev }; diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 63510cd..60615b1 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -67,6 +67,6 @@ } struct chip_operations drivers_generic_adau7002_ops = { - CHIP_NAME("Analog Digital DMIC") + CHIP_NAME("Analog Digital DMIC"), .enable_dev = adau7002_enable }; diff --git a/src/drivers/generic/alc1015/alc1015.c b/src/drivers/generic/alc1015/alc1015.c index ca685d6..efc22db 100644 --- a/src/drivers/generic/alc1015/alc1015.c +++ b/src/drivers/generic/alc1015/alc1015.c @@ -70,6 +70,6 @@ } struct chip_operations drivers_generic_alc1015_ops = { - CHIP_NAME("ASoC RT1015P Amplifier driver") + CHIP_NAME("ASoC RT1015P Amplifier driver"), .enable_dev = alc1015_enable }; diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 02abc22..608e76a 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -166,5 +166,5 @@ }; struct chip_operations drivers_generic_bayhub_ops = { - CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge") + CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge"), }; diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c index b8d4113..b2c51e6 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.c +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -81,5 +81,5 @@ }; struct chip_operations drivers_generic_bayhub_lv2_ops = { - CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge") + CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge"), }; diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index c0fd8de..514932e 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -120,6 +120,6 @@ } struct chip_operations drivers_generic_gpio_keys_ops = { - CHIP_NAME("GPIO Keys") + CHIP_NAME("GPIO Keys"), .enable_dev = gpio_keys_enable }; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 7a18b98..81d8c1a 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -93,6 +93,6 @@ } struct chip_operations drivers_generic_max98357a_ops = { - CHIP_NAME("Maxim Integrated 98357A Amplifier") + CHIP_NAME("Maxim Integrated 98357A Amplifier"), .enable_dev = max98357a_enable }; diff --git a/src/drivers/generic/nau8315/nau8315.c b/src/drivers/generic/nau8315/nau8315.c index ac2bfd1..d3c2a79 100644 --- a/src/drivers/generic/nau8315/nau8315.c +++ b/src/drivers/generic/nau8315/nau8315.c @@ -71,6 +71,6 @@ } struct chip_operations drivers_generic_nau8315_ops = { - CHIP_NAME("Nuvoton NAU8315 Amplifier") + CHIP_NAME("Nuvoton NAU8315 Amplifier"), .enable_dev = nau8315_enable }; diff --git a/src/drivers/genesyslogic/gl9750/gl9750.c b/src/drivers/genesyslogic/gl9750/gl9750.c index 8c40c49..436dedd 100644 --- a/src/drivers/genesyslogic/gl9750/gl9750.c +++ b/src/drivers/genesyslogic/gl9750/gl9750.c @@ -50,5 +50,5 @@ }; struct chip_operations drivers_generic_genesyslogic_gl9750_ops = { - CHIP_NAME("Genesys Logic GL9750") + CHIP_NAME("Genesys Logic GL9750"), }; diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c index bf4831c..8e08f04 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.c +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -58,5 +58,5 @@ }; struct chip_operations drivers_generic_genesyslogic_gl9755_ops = { - CHIP_NAME("Genesys Logic GL9755") + CHIP_NAME("Genesys Logic GL9755"), }; diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c index a4842e8..41b54a9 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.c +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -66,5 +66,5 @@ }; struct chip_operations drivers_generic_genesyslogic_ops = { - CHIP_NAME("Genesys Logic GL9763E") + CHIP_NAME("Genesys Logic GL9763E"), }; diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 0ab1676..0e5b9c4 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -160,6 +160,6 @@ } struct chip_operations drivers_gfx_generic_ops = { - CHIP_NAME("Generic Graphics Device") + CHIP_NAME("Generic Graphics Device"), .enable_dev = gfx_enable }; diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index ce6aa86..4dc31a1 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -41,6 +41,6 @@ } struct chip_operations drivers_i2c_at24rf08c_ops = { - CHIP_NAME("AT24RF08C") + CHIP_NAME("AT24RF08C"), .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index 58eaec6..3f47efe 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -55,6 +55,6 @@ } struct chip_operations drivers_i2c_ck505_ops = { - CHIP_NAME("CK505 Clock generator") + CHIP_NAME("CK505 Clock generator"), .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/cs35l53/cs35l53.c b/src/drivers/i2c/cs35l53/cs35l53.c index 9857203..4f00322 100644 --- a/src/drivers/i2c/cs35l53/cs35l53.c +++ b/src/drivers/i2c/cs35l53/cs35l53.c @@ -145,6 +145,6 @@ } struct chip_operations drivers_i2c_cs35l53_ops = { - CHIP_NAME("Cirrus Logic CS35L53 Audio Codec") + CHIP_NAME("Cirrus Logic CS35L53 Audio Codec"), .enable_dev = cs35l53_enable }; diff --git a/src/drivers/i2c/cs42l42/cs42l42.c b/src/drivers/i2c/cs42l42/cs42l42.c index dcf83e0..c0697ff 100644 --- a/src/drivers/i2c/cs42l42/cs42l42.c +++ b/src/drivers/i2c/cs42l42/cs42l42.c @@ -118,6 +118,6 @@ } struct chip_operations drivers_i2c_cs42l42_ops = { - CHIP_NAME("Cirrus Logic CS42l42 Audio Codec") + CHIP_NAME("Cirrus Logic CS42l42 Audio Codec"), .enable_dev = cs42l42_enable }; diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 80c5272..c45548c 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -110,6 +110,6 @@ } struct chip_operations drivers_i2c_da7219_ops = { - CHIP_NAME("Dialog Semiconductor DA7219 Audio Codec") + CHIP_NAME("Dialog Semiconductor DA7219 Audio Codec"), .enable_dev = da7219_enable }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 1a3ec40..8f75a39 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -229,6 +229,6 @@ } struct chip_operations drivers_i2c_generic_ops = { - CHIP_NAME("I2C Device") + CHIP_NAME("I2C Device"), .enable_dev = i2c_generic_enable }; diff --git a/src/drivers/i2c/gpiomux/bus/bus.c b/src/drivers/i2c/gpiomux/bus/bus.c index 2bdb1030..9d37cfe 100644 --- a/src/drivers/i2c/gpiomux/bus/bus.c +++ b/src/drivers/i2c/gpiomux/bus/bus.c @@ -55,6 +55,6 @@ } struct chip_operations drivers_i2c_gpiomux_bus_ops = { - CHIP_NAME("I2C GPIO MUX Bus Device") + CHIP_NAME("I2C GPIO MUX Bus Device"), .enable_dev = i2c_gpiomux_bus_enable }; diff --git a/src/drivers/i2c/gpiomux/mux/mux.c b/src/drivers/i2c/gpiomux/mux/mux.c index fa1b18c..561f797 100644 --- a/src/drivers/i2c/gpiomux/mux/mux.c +++ b/src/drivers/i2c/gpiomux/mux/mux.c @@ -77,6 +77,6 @@ } struct chip_operations drivers_i2c_gpiomux_mux_ops = { - CHIP_NAME("I2C GPIO MUX Device") + CHIP_NAME("I2C GPIO MUX Device"), .enable_dev = i2c_gpiomux_mux_enable }; diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 8705c1e..3c85bff 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -90,6 +90,6 @@ } struct chip_operations drivers_i2c_hid_ops = { - CHIP_NAME("I2C HID Device") + CHIP_NAME("I2C HID Device"), .enable_dev = i2c_hid_enable }; diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index a2b7a21..de40a7b 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -215,6 +215,6 @@ } struct chip_operations drivers_i2c_lm96000_ops = { - CHIP_NAME("LM96000") + CHIP_NAME("LM96000"), .enable_dev = lm96000_enable }; diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index eb5590d..0645727 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -90,6 +90,6 @@ } struct chip_operations drivers_i2c_max98373_ops = { - CHIP_NAME("Maxim MAX98373 Codec") + CHIP_NAME("Maxim MAX98373 Codec"), .enable_dev = max98373_enable }; diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index 11acd22..f8f158d 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -129,6 +129,6 @@ } struct chip_operations drivers_i2c_max98390_ops = { - CHIP_NAME("Maxim MAX98390 Codec") + CHIP_NAME("Maxim MAX98390 Codec"), .enable_dev = max98390_enable }; diff --git a/src/drivers/i2c/max98396/max98396.c b/src/drivers/i2c/max98396/max98396.c index 5288c4f..607ea88 100644 --- a/src/drivers/i2c/max98396/max98396.c +++ b/src/drivers/i2c/max98396/max98396.c @@ -96,6 +96,6 @@ } struct chip_operations drivers_i2c_max98396_ops = { - CHIP_NAME("Maxim MAX98396 Codec") + CHIP_NAME("Maxim MAX98396 Codec"), .enable_dev = max98396_enable }; diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index e80f569f..1558b81 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -86,6 +86,6 @@ } struct chip_operations drivers_i2c_max98927_ops = { - CHIP_NAME("Maxim MAX98927 Codec") + CHIP_NAME("Maxim MAX98927 Codec"), .enable_dev = max98927_enable }; diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 060df7c..726ca90 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -103,6 +103,6 @@ } struct chip_operations drivers_i2c_nau8825_ops = { - CHIP_NAME("Nuvoton NAU8825 Codec") + CHIP_NAME("Nuvoton NAU8825 Codec"), .enable_dev = nau8825_enable }; diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index bb52a3f..a4b84df 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -45,6 +45,6 @@ } struct chip_operations drivers_i2c_nct7802y_ops = { - CHIP_NAME("NCT7802Y") + CHIP_NAME("NCT7802Y"), .enable_dev = nct7802y_enable }; diff --git a/src/drivers/i2c/pca9538/pca9538.c b/src/drivers/i2c/pca9538/pca9538.c index 1658b9e..4012fe3 100644 --- a/src/drivers/i2c/pca9538/pca9538.c +++ b/src/drivers/i2c/pca9538/pca9538.c @@ -49,6 +49,6 @@ } struct chip_operations drivers_i2c_pca9538_ops = { - CHIP_NAME("PCA9538") + CHIP_NAME("PCA9538"), .enable_dev = pca9538_enable }; diff --git a/src/drivers/i2c/pcf8523/pcf8523.c b/src/drivers/i2c/pcf8523/pcf8523.c index 8d368b2..879ea03 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.c +++ b/src/drivers/i2c/pcf8523/pcf8523.c @@ -129,6 +129,6 @@ } struct chip_operations drivers_i2c_pcf8523_ops = { - CHIP_NAME("PCF8523") + CHIP_NAME("PCF8523"), .enable_dev = pcf8523_enable }; diff --git a/src/drivers/i2c/pi608gp/pi608gp.c b/src/drivers/i2c/pi608gp/pi608gp.c index 2c61a80..ae2432f 100644 --- a/src/drivers/i2c/pi608gp/pi608gp.c +++ b/src/drivers/i2c/pi608gp/pi608gp.c @@ -188,5 +188,5 @@ }; struct chip_operations drivers_i2c_pi608gp_ops = { - CHIP_NAME("PI7C9X2G608GP") + CHIP_NAME("PI7C9X2G608GP"), }; diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 7dee222..f2f8e11 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -148,7 +148,7 @@ } struct chip_operations drivers_i2c_ptn3460_ops = { - CHIP_NAME("PTN3460") + CHIP_NAME("PTN3460"), .enable_dev = ptn3460_enable }; diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index 9a21748..a538bbf 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -103,6 +103,6 @@ } struct chip_operations drivers_i2c_rt1011_ops = { - CHIP_NAME("Realtek RT1011 Codec") + CHIP_NAME("Realtek RT1011 Codec"), .enable_dev = rt1011_enable }; diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 9949566..142beab 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -84,6 +84,6 @@ } struct chip_operations drivers_i2c_rt5663_ops = { - CHIP_NAME("Realtek RT5663 Codec") + CHIP_NAME("Realtek RT5663 Codec"), .enable_dev = rt5663_enable }; diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 41dd887..e056657 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -235,6 +235,6 @@ } struct chip_operations drivers_i2c_rtd2132_ops = { - CHIP_NAME("Realtek RTD2132 LVDS Bridge") + CHIP_NAME("Realtek RTD2132 LVDS Bridge"), .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.c b/src/drivers/i2c/rv3028c7/rv3028c7.c index 87cbc24..051ceb7 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.c +++ b/src/drivers/i2c/rv3028c7/rv3028c7.c @@ -251,6 +251,6 @@ } struct chip_operations drivers_i2c_rv3028c7_ops = { - CHIP_NAME("RV-3028-C7") + CHIP_NAME("RV-3028-C7"), .enable_dev = rtc_enable }; diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 02b3d9f..1d99d33 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -239,6 +239,6 @@ } struct chip_operations drivers_i2c_rx6110sa_ops = { - CHIP_NAME("RX6110 SA") + CHIP_NAME("RX6110 SA"), .enable_dev = rx6110sa_enable }; diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 68aea6c..1fbc30c 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -131,6 +131,6 @@ } struct chip_operations drivers_i2c_sx9310_ops = { - CHIP_NAME(I2C_SX9310_ACPI_NAME) + CHIP_NAME(I2C_SX9310_ACPI_NAME), .enable_dev = i2c_sx9310_enable }; diff --git a/src/drivers/i2c/sx9324/sx9324.c b/src/drivers/i2c/sx9324/sx9324.c index 3678491..f313762 100644 --- a/src/drivers/i2c/sx9324/sx9324.c +++ b/src/drivers/i2c/sx9324/sx9324.c @@ -115,6 +115,6 @@ } struct chip_operations drivers_i2c_sx9324_ops = { - CHIP_NAME(I2C_SX9324_CHIP_NAME) + CHIP_NAME(I2C_SX9324_CHIP_NAME), .enable_dev = i2c_sx9324_enable }; diff --git a/src/drivers/i2c/sx9360/sx9360.c b/src/drivers/i2c/sx9360/sx9360.c index 9ea4c8b..7a0627b 100644 --- a/src/drivers/i2c/sx9360/sx9360.c +++ b/src/drivers/i2c/sx9360/sx9360.c @@ -102,6 +102,6 @@ } struct chip_operations drivers_i2c_sx9360_ops = { - CHIP_NAME(I2C_SX9360_CHIP_NAME) + CHIP_NAME(I2C_SX9360_CHIP_NAME), .enable_dev = i2c_sx9360_enable }; diff --git a/src/drivers/i2c/tas5825m/tas5825m.c b/src/drivers/i2c/tas5825m/tas5825m.c index 39e5575..3d90ae3 100644 --- a/src/drivers/i2c/tas5825m/tas5825m.c +++ b/src/drivers/i2c/tas5825m/tas5825m.c @@ -75,6 +75,6 @@ } struct chip_operations drivers_i2c_tas5825m_ops = { - CHIP_NAME("TI TAS5825M Amplifier") + CHIP_NAME("TI TAS5825M Amplifier"), .enable_dev = tas5825m_enable_dev, }; diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 07052f6..b41f6d8 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -95,6 +95,6 @@ } struct chip_operations drivers_i2c_tpm_ops = { - CHIP_NAME("I2C TPM") + CHIP_NAME("I2C TPM"), .enable_dev = i2c_tpm_enable }; diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 71a4ec3..d4bb932 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -636,6 +636,6 @@ } struct chip_operations drivers_intel_dptf_ops = { - CHIP_NAME("Intel DPTF") + CHIP_NAME("Intel DPTF"), .enable_dev = dptf_enable_dev, }; diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index d1b85f5..8331c27 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -96,6 +96,6 @@ }; struct chip_operations drivers_intel_ish_ops = { - CHIP_NAME("Intel ISH Chip") + CHIP_NAME("Intel ISH Chip"), .enable_dev = intel_ish_enable, }; diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 00c85a7..c7217ba 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -1033,6 +1033,6 @@ } struct chip_operations drivers_intel_mipi_camera_ops = { - CHIP_NAME("Intel MIPI Camera Device") + CHIP_NAME("Intel MIPI Camera Device"), .enable_dev = camera_enable }; diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index de8f2be..b4f1138 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -153,7 +153,7 @@ } struct chip_operations drivers_intel_pmc_mux_conn_ops = { - CHIP_NAME("Intel PMC MUX CONN Driver") + CHIP_NAME("Intel PMC MUX CONN Driver"), .enable_dev = conn_enable, }; diff --git a/src/drivers/intel/pmc_mux/mux.c b/src/drivers/intel/pmc_mux/mux.c index e209915..5a0f8c1 100644 --- a/src/drivers/intel/pmc_mux/mux.c +++ b/src/drivers/intel/pmc_mux/mux.c @@ -43,6 +43,6 @@ } struct chip_operations drivers_intel_pmc_mux_ops = { - CHIP_NAME("Intel PMC MUX Driver") + CHIP_NAME("Intel PMC MUX Driver"), .enable_dev = mux_enable, }; diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c index c7e84a5..f6e284a 100644 --- a/src/drivers/intel/soundwire/soundwire.c +++ b/src/drivers/intel/soundwire/soundwire.c @@ -94,6 +94,6 @@ } struct chip_operations drivers_intel_soundwire_ops = { - CHIP_NAME("Intel SoundWire Controller") + CHIP_NAME("Intel SoundWire Controller"), .enable_dev = intel_soundwire_enable }; diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 7fb600d..033b043 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -460,7 +460,7 @@ } struct chip_operations drivers_intel_usb4_retimer_ops = { - CHIP_NAME("Intel USB4 Retimer") + CHIP_NAME("Intel USB4 Retimer"), .enable_dev = usb4_retimer_enable }; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 2e5378f..a53fdd9 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -360,6 +360,6 @@ } struct chip_operations drivers_ipmi_ops = { - CHIP_NAME("IPMI KCS") + CHIP_NAME("IPMI KCS"), .enable_dev = enable_dev, }; diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c index e75edca..8df4fce 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -95,6 +95,6 @@ } struct chip_operations drivers_ipmi_ocp_ops = { - CHIP_NAME("IPMI OCP") + CHIP_NAME("IPMI OCP"), .enable_dev = enable_dev, }; diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index 7a5e20d..4700609 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -53,6 +53,6 @@ } struct chip_operations drivers_lenovo_hybrid_graphics_ops = { - CHIP_NAME("Lenovo hybrid graphics driver") + CHIP_NAME("Lenovo hybrid graphics driver"), .enable_dev = lenovo_hybrid_graphics_enable }; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index fb9bcde..75281e7 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -153,5 +153,5 @@ }; struct chip_operations drivers_net_ops = { - CHIP_NAME("Atheros AR8121/AR8113/AR8114") + CHIP_NAME("Atheros AR8121/AR8113/AR8114"), }; diff --git a/src/drivers/net/phy/m88e1512/m88e1512.c b/src/drivers/net/phy/m88e1512/m88e1512.c index 2e8994c..68dceb2 100644 --- a/src/drivers/net/phy/m88e1512/m88e1512.c +++ b/src/drivers/net/phy/m88e1512/m88e1512.c @@ -97,5 +97,5 @@ }; struct chip_operations drivers_net_phy_m88e1512_ops = { - CHIP_NAME("88E1512") + CHIP_NAME("88E1512"), }; diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index f21edd0..91bc43c 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -441,5 +441,5 @@ }; struct chip_operations drivers_net_ops = { - CHIP_NAME("Realtek r8168") + CHIP_NAME("Realtek r8168"), }; diff --git a/src/drivers/nxp/uwb/uwb.c b/src/drivers/nxp/uwb/uwb.c index 978edeb..8a91be8 100644 --- a/src/drivers/nxp/uwb/uwb.c +++ b/src/drivers/nxp/uwb/uwb.c @@ -133,6 +133,6 @@ } struct chip_operations drivers_nxp_uwb_ops = { - CHIP_NAME("NXP UWB Device") + CHIP_NAME("NXP UWB Device"), .enable_dev = nxb_uwb_enable }; diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 019e4a1..f78d54f 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -854,6 +854,6 @@ } struct chip_operations drivers_pc80_tpm_ops = { - CHIP_NAME("LPC TPM") + CHIP_NAME("LPC TPM"), .enable_dev = enable_dev }; diff --git a/src/drivers/pcie/generic/generic.c b/src/drivers/pcie/generic/generic.c index 1873e65..3f72903 100644 --- a/src/drivers/pcie/generic/generic.c +++ b/src/drivers/pcie/generic/generic.c @@ -68,6 +68,6 @@ } struct chip_operations drivers_pcie_generic_ops = { - CHIP_NAME("PCIe Device") + CHIP_NAME("PCIe Device"), .enable_dev = pcie_generic_enable }; diff --git a/src/drivers/pcie/rtd3/device/chip.c b/src/drivers/pcie/rtd3/device/chip.c index 88b85f1..745f33b 100644 --- a/src/drivers/pcie/rtd3/device/chip.c +++ b/src/drivers/pcie/rtd3/device/chip.c @@ -150,6 +150,6 @@ } struct chip_operations drivers_pcie_rtd3_device_ops = { - CHIP_NAME("PCIe Device w/ Runtime D3") + CHIP_NAME("PCIe Device w/ Runtime D3"), .enable_dev = pcie_rtd3_device_enable }; diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index c85b4d1..de0ade4 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -58,5 +58,5 @@ }; struct chip_operations drivers_ricoh_rce822_ops = { - CHIP_NAME("RICOH RCE822") + CHIP_NAME("RICOH RCE822"), }; diff --git a/src/drivers/secunet/dmi/smbios.c b/src/drivers/secunet/dmi/smbios.c index f407b51..e039ffd 100644 --- a/src/drivers/secunet/dmi/smbios.c +++ b/src/drivers/secunet/dmi/smbios.c @@ -91,6 +91,6 @@ } struct chip_operations drivers_secunet_dmi_ops = { - CHIP_NAME("secunet DMI") + CHIP_NAME("secunet DMI"), .enable_dev = enable_dev, }; diff --git a/src/drivers/sof/sof.c b/src/drivers/sof/sof.c index b353790..d49709b 100644 --- a/src/drivers/sof/sof.c +++ b/src/drivers/sof/sof.c @@ -85,6 +85,6 @@ } struct chip_operations drivers_sof_ops = { - CHIP_NAME("SOF") + CHIP_NAME("SOF"), .enable_dev = sof_enable }; diff --git a/src/drivers/soundwire/alc1308/alc1308.c b/src/drivers/soundwire/alc1308/alc1308.c index f16d3a2..e9d5b5a 100644 --- a/src/drivers/soundwire/alc1308/alc1308.c +++ b/src/drivers/soundwire/alc1308/alc1308.c @@ -146,6 +146,6 @@ } struct chip_operations drivers_soundwire_alc1308_ops = { - CHIP_NAME("Realtek ALC1308 SoundWire Codec") + CHIP_NAME("Realtek ALC1308 SoundWire Codec"), .enable_dev = soundwire_alc1308_enable }; diff --git a/src/drivers/soundwire/alc5682/alc5682.c b/src/drivers/soundwire/alc5682/alc5682.c index c1aaff6..c23e853 100644 --- a/src/drivers/soundwire/alc5682/alc5682.c +++ b/src/drivers/soundwire/alc5682/alc5682.c @@ -174,6 +174,6 @@ } struct chip_operations drivers_soundwire_alc5682_ops = { - CHIP_NAME("Realtek ALC5682 SoundWire Codec") + CHIP_NAME("Realtek ALC5682 SoundWire Codec"), .enable_dev = soundwire_alc5682_enable }; diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c index 34d55c7..c0dc9a7 100644 --- a/src/drivers/soundwire/alc711/alc711.c +++ b/src/drivers/soundwire/alc711/alc711.c @@ -151,6 +151,6 @@ } struct chip_operations drivers_soundwire_alc711_ops = { - CHIP_NAME("Realtek ALC711 SoundWire Codec") + CHIP_NAME("Realtek ALC711 SoundWire Codec"), .enable_dev = soundwire_alc711_enable }; diff --git a/src/drivers/soundwire/cs42l42/cs42l42.c b/src/drivers/soundwire/cs42l42/cs42l42.c index 111844c..6a3b382 100644 --- a/src/drivers/soundwire/cs42l42/cs42l42.c +++ b/src/drivers/soundwire/cs42l42/cs42l42.c @@ -226,6 +226,6 @@ } struct chip_operations drivers_soundwire_cs42l42_ops = { - CHIP_NAME("Cirrus Logic CS42L42 SoundWire Codec") + CHIP_NAME("Cirrus Logic CS42L42 SoundWire Codec"), .enable_dev = soundwire_cs42l42_enable }; diff --git a/src/drivers/soundwire/max98363/max98363.c b/src/drivers/soundwire/max98363/max98363.c index 2963cda..4e5bc44 100644 --- a/src/drivers/soundwire/max98363/max98363.c +++ b/src/drivers/soundwire/max98363/max98363.c @@ -136,6 +136,6 @@ } struct chip_operations drivers_soundwire_max98363_ops = { - CHIP_NAME("Maxim MAX98363 SoundWire Codec") + CHIP_NAME("Maxim MAX98363 SoundWire Codec"), .enable_dev = soundwire_max98363_enable }; diff --git a/src/drivers/soundwire/max98373/max98373.c b/src/drivers/soundwire/max98373/max98373.c index fb202fe..2c07a7a 100644 --- a/src/drivers/soundwire/max98373/max98373.c +++ b/src/drivers/soundwire/max98373/max98373.c @@ -160,6 +160,6 @@ } struct chip_operations drivers_soundwire_max98373_ops = { - CHIP_NAME("Maxim MAX98373 SoundWire Codec") + CHIP_NAME("Maxim MAX98373 SoundWire Codec"), .enable_dev = soundwire_max98373_enable }; diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 9b6fd80..2732312 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -200,6 +200,6 @@ } struct chip_operations drivers_spi_acpi_ops = { - CHIP_NAME("SPI Device") + CHIP_NAME("SPI Device"), .enable_dev = spi_acpi_enable }; diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c index c43dc52..eebf3b4 100644 --- a/src/drivers/uart/acpi/acpi.c +++ b/src/drivers/uart/acpi/acpi.c @@ -169,6 +169,6 @@ } struct chip_operations drivers_uart_acpi_ops = { - CHIP_NAME("ACPI UART Device") + CHIP_NAME("ACPI UART Device"), .enable_dev = uart_acpi_enable }; diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index b95ebc9..c0793ba 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -127,7 +127,7 @@ } struct chip_operations drivers_usb_acpi_ops = { - CHIP_NAME("USB ACPI Device") + CHIP_NAME("USB ACPI Device"), .enable_dev = usb_acpi_enable }; diff --git a/src/drivers/usb/hub/acpi.c b/src/drivers/usb/hub/acpi.c index 10e38fb6..9e8b20e 100644 --- a/src/drivers/usb/hub/acpi.c +++ b/src/drivers/usb/hub/acpi.c @@ -85,6 +85,6 @@ } struct chip_operations drivers_usb_hub_ops = { - CHIP_NAME("USB Hub") + CHIP_NAME("USB Hub"), .enable_dev = usb_hub_acpi_enable }; diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 19d281f..11aa4f7 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -67,7 +67,7 @@ } struct chip_operations drivers_wifi_generic_ops = { - CHIP_NAME("WIFI Device") + CHIP_NAME("WIFI Device"), .enable_dev = wifi_generic_enable }; diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c index 08f672f..0203a20 100644 --- a/src/drivers/wwan/fm/acpi_fm350gl.c +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -392,6 +392,6 @@ } struct chip_operations drivers_wwan_fm_ops = { - CHIP_NAME("Fibocom FM-350-GL") + CHIP_NAME("Fibocom FM-350-GL"), .enable_dev = wwan_fm350gl_acpi_enable }; diff --git a/src/ec/51nb/npce985la0dx/npce985la0dx.c b/src/ec/51nb/npce985la0dx/npce985la0dx.c index 06db530..8ba24a3 100644 --- a/src/ec/51nb/npce985la0dx/npce985la0dx.c +++ b/src/ec/51nb/npce985la0dx/npce985la0dx.c @@ -17,6 +17,6 @@ } struct chip_operations ec_51nb_npce985la0dx_ops = { - CHIP_NAME("51NB EC") + CHIP_NAME("51NB EC"), .enable_dev = ec_51nb_npce985la0dx_ops_enable, }; diff --git a/src/ec/clevo/it5570e/ec.c b/src/ec/clevo/it5570e/ec.c index 4f10750..faef8e4 100644 --- a/src/ec/clevo/it5570e/ec.c +++ b/src/ec/clevo/it5570e/ec.c @@ -123,6 +123,6 @@ } struct chip_operations ec_clevo_it5570e_ops = { - CHIP_NAME("Clevo IT5570E EC") + CHIP_NAME("Clevo IT5570E EC"), .enable_dev = enable_dev, }; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 6389383..0d67673 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -131,6 +131,6 @@ } struct chip_operations ec_compal_ene932_ops = { - CHIP_NAME("COMPAL ENE932 EC") + CHIP_NAME("COMPAL ENE932 EC"), .enable_dev = enable_dev }; diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c index eec79fb..4e2a0b2 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c @@ -131,6 +131,6 @@ } struct chip_operations ec_dell_mec5035_ops = { - CHIP_NAME("MEC5035 EC") + CHIP_NAME("MEC5035 EC"), .enable_dev = mec5035_enable, }; diff --git a/src/ec/google/chromeec/audio_codec/audio_codec.c b/src/ec/google/chromeec/audio_codec/audio_codec.c index 53037eb..a838e82 100644 --- a/src/ec/google/chromeec/audio_codec/audio_codec.c +++ b/src/ec/google/chromeec/audio_codec/audio_codec.c @@ -59,6 +59,6 @@ } struct chip_operations ec_google_chromeec_audio_codec_ops = { - CHIP_NAME("CrosEC Audio Codec Device") + CHIP_NAME("CrosEC Audio Codec Device"), .enable_dev = crosec_audio_codec_enable }; diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 080b95d..581ef20 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -451,7 +451,7 @@ } struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") + CHIP_NAME("Google Chrome EC"), .enable_dev = enable_dev, }; diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c index e61ecfd8..e5f3cfd 100644 --- a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -65,6 +65,6 @@ } struct chip_operations ec_google_chromeec_i2c_tunnel_ops = { - CHIP_NAME("CrosEC I2C Tunnel Device") + CHIP_NAME("CrosEC I2C Tunnel Device"), .enable_dev = crosec_i2c_tunnel_enable }; diff --git a/src/ec/google/chromeec/mux/conn/conn.c b/src/ec/google/chromeec/mux/conn/conn.c index e179c33..24f1718 100644 --- a/src/ec/google/chromeec/mux/conn/conn.c +++ b/src/ec/google/chromeec/mux/conn/conn.c @@ -52,6 +52,6 @@ } struct chip_operations ec_google_chromeec_mux_conn_ops = { - CHIP_NAME("CrosEC Type C Mux device") + CHIP_NAME("CrosEC Type C Mux device"), .enable_dev = conn_enable, }; diff --git a/src/ec/google/chromeec/mux/mux.c b/src/ec/google/chromeec/mux/mux.c index 9324d2e..7106d15 100644 --- a/src/ec/google/chromeec/mux/mux.c +++ b/src/ec/google/chromeec/mux/mux.c @@ -36,6 +36,6 @@ } struct chip_operations ec_google_chromeec_mux_ops = { - CHIP_NAME("CrosEC Type C Mux device") + CHIP_NAME("CrosEC Type C Mux device"), .enable_dev = mux_enable }; diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 88d416d..5b9af62 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -230,6 +230,6 @@ } struct chip_operations ec_google_wilco_ops = { - CHIP_NAME("Google Wilco EC") + CHIP_NAME("Google Wilco EC"), .enable_dev = wilco_ec_enable_dev, }; diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 8035b94..df8dbdf 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -120,6 +120,6 @@ } struct chip_operations ec_hp_kbc1126_ops = { - CHIP_NAME("SMSC KBC1126 for HP laptops") + CHIP_NAME("SMSC KBC1126 for HP laptops"), .enable_dev = kbc1126_enable }; diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 5288976..ef6f0be 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -239,6 +239,6 @@ } const struct chip_operations ec_kontron_it8516e_ops = { - CHIP_NAME("Kontron (Fintec/ITE) IT8516E EC") + CHIP_NAME("Kontron (Fintec/ITE) IT8516E EC"), .enable_dev = it8516e_enable }; diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index 9527429..66b23a3 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -105,6 +105,6 @@ } struct chip_operations ec_kontron_kempld_ops = { - CHIP_NAME("Kontron KEMPLD") + CHIP_NAME("Kontron KEMPLD"), .enable_dev = kempld_enable_dev, }; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 9b7bcc3..4b252fe 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -325,6 +325,6 @@ } struct chip_operations ec_lenovo_h8_ops = { - CHIP_NAME("Lenovo H8 EC") + CHIP_NAME("Lenovo H8 EC"), .enable_dev = h8_enable, }; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index fa24c68..e3c7385 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -126,6 +126,6 @@ } struct chip_operations ec_lenovo_pmh7_ops = { - CHIP_NAME("Lenovo Power Management Hardware Hub 7") + CHIP_NAME("Lenovo Power Management Hardware Hub 7"), .enable_dev = enable_dev, }; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 4b4f532..363decd 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -141,6 +141,6 @@ } struct chip_operations ec_quanta_ene_kb3940q_ops = { - CHIP_NAME("QUANTA EnE KB3940Q EC") + CHIP_NAME("QUANTA EnE KB3940Q EC"), .enable_dev = enable_dev }; diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 80aaa5d..64cf0aa 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -154,6 +154,6 @@ } struct chip_operations ec_quanta_it8518_ops = { - CHIP_NAME("QUANTA IT8518 EC") + CHIP_NAME("QUANTA IT8518 EC"), .enable_dev = enable_dev }; diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index cbeb210..9a63466 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -48,6 +48,6 @@ } struct chip_operations ec_roda_it8518_ops = { - CHIP_NAME("Roda IT8518 EC") + CHIP_NAME("Roda IT8518 EC"), .enable_dev = enable_dev }; diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index fb09aa5..bd09a01 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -112,6 +112,6 @@ } struct chip_operations ec_smsc_mec1308_ops = { - CHIP_NAME("SMSC MEC1308 EC Mailbox Interface") + CHIP_NAME("SMSC MEC1308 EC Mailbox Interface"), .enable_dev = mec1308_enable }; diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index daf5873..ecfa3a0 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -322,6 +322,6 @@ } struct chip_operations ec_starlabs_merlin_ops = { - CHIP_NAME("ITE EC") + CHIP_NAME("ITE EC"), .enable_dev = enable_dev }; diff --git a/src/ec/starlabs/merlin/nuvoton.c b/src/ec/starlabs/merlin/nuvoton.c index bad8d1b..a07e8c7 100644 --- a/src/ec/starlabs/merlin/nuvoton.c +++ b/src/ec/starlabs/merlin/nuvoton.c @@ -297,6 +297,6 @@ } struct chip_operations ec_starlabs_merlin_ops = { - CHIP_NAME("NUVOTON EC") + CHIP_NAME("NUVOTON EC"), .enable_dev = enable_dev }; diff --git a/src/include/device/device.h b/src/include/device/device.h index 83588d4..658b262 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -32,7 +32,7 @@ const char *name; }; -#define CHIP_NAME(X) .name = X, +#define CHIP_NAME(X) .name = X struct bus; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 5fe12e7..93058e7 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -276,11 +276,11 @@ } struct chip_operations mainboard_emulation_qemu_i440fx_ops = { - CHIP_NAME("QEMU Northbridge i440fx") + CHIP_NAME("QEMU Northbridge i440fx"), .enable_dev = northbridge_enable, }; struct chip_operations mainboard_emulation_qemu_q35_ops = { - CHIP_NAME("QEMU Northbridge q35") + CHIP_NAME("QEMU Northbridge q35"), .enable_dev = northbridge_enable, }; diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 98548e3..bb79bff 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -35,6 +35,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("X10SLM+-F") + CHIP_NAME("X10SLM+-F"), .enable_dev = mainboard_enable, }; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index a4409fb..a6fdf4b 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -693,7 +693,7 @@ }; struct chip_operations northbridge_amd_pi_00730F01_ops = { - CHIP_NAME("AMD FAM16 Root Complex") + CHIP_NAME("AMD FAM16 Root Complex"), .final = fam16_finalize, }; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 65a0212..56b153a 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -70,5 +70,5 @@ }; struct chip_operations northbridge_intel_e7505_ops = { - CHIP_NAME("Intel E7505 Northbridge") + CHIP_NAME("Intel E7505 Northbridge"), }; diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 4bddf20..4a6325c 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -233,7 +233,7 @@ } struct chip_operations northbridge_intel_gm45_ops = { - CHIP_NAME("Intel GM45 Northbridge") + CHIP_NAME("Intel GM45 Northbridge"), .init = gm45_init, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ef5b9e9..e94c2e4 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -542,5 +542,5 @@ }; struct chip_operations northbridge_intel_haswell_ops = { - CHIP_NAME("Intel Haswell integrated Northbridge") + CHIP_NAME("Intel Haswell integrated Northbridge"), }; diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 0670f72..ddc7fc7 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -105,6 +105,6 @@ } struct chip_operations northbridge_intel_i440bx_ops = { - CHIP_NAME("Intel 82443BX (440BX) Northbridge") + CHIP_NAME("Intel 82443BX (440BX) Northbridge"), .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1dfcc40..cca5352 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -134,7 +134,7 @@ }; struct chip_operations northbridge_intel_i945_ops = { - CHIP_NAME("Intel i945 Northbridge") + CHIP_NAME("Intel i945 Northbridge"), }; bool northbridge_support_slfm(void) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 74ddee2..9c4429c 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -217,6 +217,6 @@ }; struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel Ironlake integrated Northbridge") + CHIP_NAME("Intel Ironlake integrated Northbridge"), .init = ironlake_init, }; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index a23a0d5..18e2f19 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -159,6 +159,6 @@ } struct chip_operations northbridge_intel_pineview_ops = { - CHIP_NAME("Intel Pineview Northbridge") + CHIP_NAME("Intel Pineview Northbridge"), .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 6b89710..efbead4 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -407,5 +407,5 @@ }; struct chip_operations northbridge_intel_sandybridge_ops = { - CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") + CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge"), }; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 12a7a40..8eb266c 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -154,7 +154,7 @@ } struct chip_operations northbridge_intel_x4x_ops = { - CHIP_NAME("Intel 4-Series Northbridge") + CHIP_NAME("Intel 4-Series Northbridge"), .init = x4x_init, }; diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 4723321..4f1b93c 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -50,7 +50,7 @@ } struct chip_operations soc_amd_cezanne_ops = { - CHIP_NAME("AMD Cezanne SoC") + CHIP_NAME("AMD Cezanne SoC"), .init = soc_init, .final = soc_final }; diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c index 5f29428..1e90c4e 100644 --- a/src/soc/amd/genoa_poc/chip.c +++ b/src/soc/amd/genoa_poc/chip.c @@ -21,7 +21,7 @@ } struct chip_operations soc_amd_genoa_poc_ops = { - CHIP_NAME("AMD Genoa SoC Proof of Concept") + CHIP_NAME("AMD Genoa SoC Proof of Concept"), .init = soc_init, .final = soc_final, }; diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 32d3ce5..298feb9 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -52,7 +52,7 @@ } struct chip_operations soc_amd_glinda_ops = { - CHIP_NAME("AMD Glinda SoC") + CHIP_NAME("AMD Glinda SoC"), .init = soc_init, .final = soc_final }; diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 840d29a..85990d1 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -50,7 +50,7 @@ } struct chip_operations soc_amd_mendocino_ops = { - CHIP_NAME("AMD Mendocino SoC") + CHIP_NAME("AMD Mendocino SoC"), .init = soc_init, .final = soc_final }; diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index ebc3c7c..c7f2219 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -52,7 +52,7 @@ } struct chip_operations soc_amd_phoenix_ops = { - CHIP_NAME("AMD Phoenix SoC") + CHIP_NAME("AMD Phoenix SoC"), .init = soc_init, .final = soc_final }; diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 4ddfa56..266c2170 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -50,7 +50,7 @@ } struct chip_operations soc_amd_picasso_ops = { - CHIP_NAME("AMD Picasso SOC") + CHIP_NAME("AMD Picasso SOC"), .init = soc_init, .final = soc_final }; diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 09cede3..403f518 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -100,7 +100,7 @@ } struct chip_operations soc_amd_stoneyridge_ops = { - CHIP_NAME("AMD StoneyRidge SOC") + CHIP_NAME("AMD StoneyRidge SOC"), .init = soc_init, .final = soc_final }; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index ed1441b..4c2937e 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -394,6 +394,6 @@ } struct chip_operations soc_cavium_cn81xx_ops = { - CHIP_NAME("SOC Cavium CN81XX") + CHIP_NAME("SOC Cavium CN81XX"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/cavium/common/pci/uart.c b/src/soc/cavium/common/pci/uart.c index 4ee1cdf..25ac75d 100644 --- a/src/soc/cavium/common/pci/uart.c +++ b/src/soc/cavium/common/pci/uart.c @@ -26,5 +26,5 @@ }; struct chip_operations soc_cavium_common_pci_ops = { - CHIP_NAME("Cavium ThunderX UART") + CHIP_NAME("Cavium ThunderX UART"), }; diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 0639157..35fd4ae 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -286,7 +286,7 @@ } struct chip_operations soc_intel_alderlake_ops = { - CHIP_NAME("Intel Alderlake") + CHIP_NAME("Intel Alderlake"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 07c2637..82ac5f1 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -759,7 +759,7 @@ } struct chip_operations soc_intel_apollolake_ops = { - CHIP_NAME("Intel Apollolake SOC") + CHIP_NAME("Intel Apollolake SOC"), .enable_dev = &enable_dev, .init = &soc_init, .final = &soc_final diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 592e178..9454d8c 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -43,7 +43,7 @@ } struct chip_operations soc_intel_baytrail_ops = { - CHIP_NAME("Intel BayTrail SoC") + CHIP_NAME("Intel BayTrail SoC"), .enable_dev = enable_dev, .init = soc_init, }; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d3c41f8..5a6cfb7 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -294,7 +294,7 @@ } struct chip_operations soc_intel_braswell_ops = { - CHIP_NAME("Intel Braswell SoC") + CHIP_NAME("Intel Braswell SoC"), .enable_dev = enable_dev, .init = soc_init, }; diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 6525275..7edbcc7 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -419,6 +419,6 @@ } struct chip_operations soc_intel_broadwell_ops = { - CHIP_NAME("Intel Broadwell") + CHIP_NAME("Intel Broadwell"), .init = &broadwell_init_pre_device, }; diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c index 98fbc46..205ee86 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -196,7 +196,7 @@ } struct chip_operations soc_intel_broadwell_pch_ops = { - CHIP_NAME("Intel Broadwell PCH") + CHIP_NAME("Intel Broadwell PCH"), .enable_dev = &broadwell_pch_enable_dev, }; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0da6e40..376b450 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -206,7 +206,7 @@ } struct chip_operations soc_intel_cannonlake_ops = { - CHIP_NAME("Intel Cannonlake") + CHIP_NAME("Intel Cannonlake"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index abd7e466..6070574 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -567,6 +567,6 @@ } struct chip_operations soc_intel_common_block_pcie_rtd3_ops = { - CHIP_NAME("Intel PCIe Runtime D3") + CHIP_NAME("Intel PCIe Runtime D3"), .enable_dev = pcie_rtd3_acpi_enable }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 9123498..390948a 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -427,7 +427,7 @@ } struct chip_operations soc_intel_common_block_uart_ops = { - CHIP_NAME("LPSS UART in ACPI mode") + CHIP_NAME("LPSS UART in ACPI mode"), .enable_dev = uart_enable }; diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index 0139647..55e0b76 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -81,6 +81,6 @@ } struct chip_operations soc_intel_common_block_usb4_ops = { - CHIP_NAME("Intel USB4 PCIe Root Port") + CHIP_NAME("Intel USB4 PCIe Root Port"), .enable_dev = usb4_pcie_acpi_enable }; diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 1a4341e..f04f012 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -187,7 +187,7 @@ } struct chip_operations soc_intel_denverton_ns_ops = { - CHIP_NAME("Intel Denverton-NS SOC") + CHIP_NAME("Intel Denverton-NS SOC"), .enable_dev = soc_enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index 194591d..5aa4e02 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -159,7 +159,7 @@ } struct chip_operations soc_intel_elkhartlake_ops = { - CHIP_NAME("Intel Elkhartlake") + CHIP_NAME("Intel Elkhartlake"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index c049163f..01d1093 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -170,7 +170,7 @@ } struct chip_operations soc_intel_jasperlake_ops = { - CHIP_NAME("Intel Jasperlake") + CHIP_NAME("Intel Jasperlake"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index be957cc..d18d7cc 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -276,7 +276,7 @@ } struct chip_operations soc_intel_meteorlake_ops = { - CHIP_NAME("Intel Meteorlake") + CHIP_NAME("Intel Meteorlake"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, .final = &soc_init_final_device, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8df1ad3..e959a5e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -212,7 +212,7 @@ } struct chip_operations soc_intel_skylake_ops = { - CHIP_NAME("Intel 6th Gen") + CHIP_NAME("Intel 6th Gen"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index dd24679..02cc2bf 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -222,7 +222,7 @@ } struct chip_operations soc_intel_tigerlake_ops = { - CHIP_NAME("Intel Tigerlake") + CHIP_NAME("Intel Tigerlake"), .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 39a7eba..21667a7 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -186,7 +186,7 @@ } struct chip_operations soc_intel_xeon_sp_cpx_ops = { - CHIP_NAME("Intel Cooper Lake-SP") + CHIP_NAME("Intel Cooper Lake-SP"), .enable_dev = chip_enable_dev, .init = chip_init, .final = chip_final, diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index b468842..7d1806f 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -89,7 +89,7 @@ } struct chip_operations soc_intel_xeon_sp_skx_ops = { - CHIP_NAME("Intel Skylake-SP") + CHIP_NAME("Intel Skylake-SP"), .enable_dev = soc_enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 3b3c65e..afe14c0 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -159,7 +159,8 @@ } struct chip_operations soc_intel_xeon_sp_spr_ops = { - CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, + CHIP_NAME("Intel SapphireRapids-SP"), + .enable_dev = chip_enable_dev, .init = chip_init, .final = chip_final, }; diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c index ebdf4e5..bca3dfe 100644 --- a/src/soc/mediatek/mt8173/soc.c +++ b/src/soc/mediatek/mt8173/soc.c @@ -45,6 +45,6 @@ } struct chip_operations soc_mediatek_mt8173_ops = { - CHIP_NAME("SOC Mediatek MT8173") + CHIP_NAME("SOC Mediatek MT8173"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index 32ec4e4..6c01590 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -33,6 +33,6 @@ } struct chip_operations soc_mediatek_mt8183_ops = { - CHIP_NAME("SOC Mediatek MT8183") + CHIP_NAME("SOC Mediatek MT8183"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index a55e2ee..121ac60 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -50,6 +50,6 @@ } struct chip_operations soc_mediatek_mt8186_ops = { - CHIP_NAME("SOC Mediatek MT8186") + CHIP_NAME("SOC Mediatek MT8186"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/mediatek/mt8188/soc.c b/src/soc/mediatek/mt8188/soc.c index d0a29c5..42a3f93 100644 --- a/src/soc/mediatek/mt8188/soc.c +++ b/src/soc/mediatek/mt8188/soc.c @@ -65,6 +65,6 @@ } struct chip_operations soc_mediatek_mt8188_ops = { - CHIP_NAME("SOC Mediatek MT8188") + CHIP_NAME("SOC Mediatek MT8188"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 74d2579..c64ef6a 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -47,6 +47,6 @@ } struct chip_operations soc_mediatek_mt8192_ops = { - CHIP_NAME("SOC Mediatek MT8192") + CHIP_NAME("SOC Mediatek MT8192"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 5425695..df43122 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -70,6 +70,6 @@ } struct chip_operations soc_mediatek_mt8195_ops = { - CHIP_NAME("SOC Mediatek MT8195") + CHIP_NAME("SOC Mediatek MT8195"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 64fb868..819b097 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -47,6 +47,6 @@ } struct chip_operations soc_nvidia_tegra124_ops = { - CHIP_NAME("SOC Nvidia Tegra124") + CHIP_NAME("SOC Nvidia Tegra124"), .enable_dev = enable_tegra124_dev, }; diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index b037bdf..dafb060 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -80,7 +80,7 @@ } struct chip_operations soc_nvidia_tegra210_ops = { - CHIP_NAME("SOC Nvidia Tegra210") + CHIP_NAME("SOC Nvidia Tegra210"), .init = tegra210_init, .enable_dev = enable_tegra210_dev, }; diff --git a/src/soc/qualcomm/ipq40xx/soc.c b/src/soc/qualcomm/ipq40xx/soc.c index f482cff..2b03d30 100644 --- a/src/soc/qualcomm/ipq40xx/soc.c +++ b/src/soc/qualcomm/ipq40xx/soc.c @@ -49,6 +49,6 @@ } struct chip_operations soc_qualcomm_ipq40xx_ops = { - CHIP_NAME("SOC QCA 40xx") + CHIP_NAME("SOC QCA 40xx"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c index ad0510f..43de5b0 100644 --- a/src/soc/qualcomm/ipq806x/soc.c +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -39,6 +39,6 @@ } struct chip_operations soc_qualcomm_ipq806x_ops = { - CHIP_NAME("SOC Qualcomm 8064") + CHIP_NAME("SOC Qualcomm 8064"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index f1a2def..76eb784 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -27,6 +27,6 @@ } struct chip_operations soc_qualcomm_qcs405_ops = { - CHIP_NAME("SOC Qualcomm QCS405") + CHIP_NAME("SOC Qualcomm QCS405"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index cef7e8f..d44620c 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -36,6 +36,6 @@ } struct chip_operations soc_qualcomm_sc7180_ops = { - CHIP_NAME("SOC Qualcomm SC7180") + CHIP_NAME("SOC Qualcomm SC7180"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 783c557..0ad8e94 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -53,6 +53,6 @@ } struct chip_operations soc_qualcomm_sc7280_ops = { - CHIP_NAME("SOC Qualcomm SC7280") + CHIP_NAME("SOC Qualcomm SC7280"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 20f5cec..3f9dc4b 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -33,6 +33,6 @@ } struct chip_operations soc_rockchip_rk3288_ops = { - CHIP_NAME("SOC Rockchip 3288") + CHIP_NAME("SOC Rockchip 3288"), .enable_dev = enable_rk3288_dev, }; diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 03c39a9..8592e52 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -46,6 +46,6 @@ } struct chip_operations soc_rockchip_rk3399_ops = { - CHIP_NAME("SOC Rockchip RK3399") + CHIP_NAME("SOC Rockchip RK3399"), .enable_dev = enable_soc_dev, }; diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 06c9423..c297b5b 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -128,7 +128,7 @@ } struct chip_operations soc_samsung_exynos5250_ops = { - CHIP_NAME("SOC Samsung Exynos 5250") + CHIP_NAME("SOC Samsung Exynos 5250"), .enable_dev = enable_exynos5250_dev, }; diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 7869ab8..d892947 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -156,6 +156,6 @@ } struct chip_operations soc_samsung_exynos5420_ops = { - CHIP_NAME("SOC Samsung Exynos 5420") + CHIP_NAME("SOC Samsung Exynos 5420"), .enable_dev = enable_exynos5420_dev, }; diff --git a/src/soc/sifive/fu540/chip.c b/src/soc/sifive/fu540/chip.c index 6eab45c..4c6637f 100644 --- a/src/soc/sifive/fu540/chip.c +++ b/src/soc/sifive/fu540/chip.c @@ -3,5 +3,5 @@ #include <device/device.h> struct chip_operations soc_sifive_fu540_ops = { - CHIP_NAME("SIFIVE FU540") + CHIP_NAME("SIFIVE FU540"), }; diff --git a/src/soc/ti/am335x/soc.c b/src/soc/ti/am335x/soc.c index 410b2d7..b8c5416 100644 --- a/src/soc/ti/am335x/soc.c +++ b/src/soc/ti/am335x/soc.c @@ -10,6 +10,6 @@ } struct chip_operations soc_ti_am335x_ops = { - CHIP_NAME("TI AM335X") + CHIP_NAME("TI AM335X"), .enable_dev = soc_enable, }; diff --git a/src/soc/ucb/riscv/chip.c b/src/soc/ucb/riscv/chip.c index 187e96d..3797676 100644 --- a/src/soc/ucb/riscv/chip.c +++ b/src/soc/ucb/riscv/chip.c @@ -3,5 +3,5 @@ #include <device/device.h> struct chip_operations soc_ucb_riscv_ops = { - CHIP_NAME("UCB RISC-V") + CHIP_NAME("UCB RISC-V"), }; diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 59e293f..46eba7a 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -92,7 +92,7 @@ } struct chip_operations southbridge_amd_pi_hudson_ops = { - CHIP_NAME("ATI HUDSON") + CHIP_NAME("ATI HUDSON"), .enable_dev = hudson_enable, .init = hudson_init, .final = hudson_final diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 32ed5cd..a9820c7 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -358,6 +358,6 @@ } struct chip_operations southbridge_intel_bd82x6x_ops = { - CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") + CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge"), .enable_dev = pch_enable, }; diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index ce07152..bc02f42 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -35,5 +35,5 @@ #include <device/device.h> const struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") + CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge"), }; diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index ea90656..ca41f14 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -64,6 +64,6 @@ } struct chip_operations southbridge_intel_i82801dx_ops = { - CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge") + CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge"), .enable_dev = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 4783099..51effdd 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -83,7 +83,7 @@ } struct chip_operations southbridge_intel_i82801gx_ops = { - CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge") + CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge"), .enable_dev = i82801gx_enable, .init = i82801gx_init, }; diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 846c9d8..c056b24 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -203,7 +203,7 @@ } struct chip_operations southbridge_intel_i82801ix_ops = { - CHIP_NAME("Intel ICH9/ICH9-M (82801Ix) Series Southbridge") + CHIP_NAME("Intel ICH9/ICH9-M (82801Ix) Series Southbridge"), .enable_dev = i82801ix_enable_device, .init = i82801ix_init, }; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 6f903014..f625ab3 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -194,7 +194,7 @@ } struct chip_operations southbridge_intel_i82801jx_ops = { - CHIP_NAME("Intel ICH10 (82801Jx) Series Southbridge") + CHIP_NAME("Intel ICH10 (82801Jx) Series Southbridge"), .enable_dev = i82801jx_enable_device, .init = i82801jx_init, }; diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index 00bf6bb..bd611fb 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -38,5 +38,5 @@ }; struct chip_operations southbridge_intel_i82870_ops = { - CHIP_NAME("Intel 82870") + CHIP_NAME("Intel 82870"), }; diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 23768ed..6eb8922 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -84,6 +84,6 @@ } struct chip_operations southbridge_intel_ibexpeak_ops = { - CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge") + CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge"), .enable_dev = pch_enable, }; diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 8b037a9..514d006 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -199,7 +199,7 @@ } struct chip_operations southbridge_intel_lynxpoint_ops = { - CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge") + CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge"), .enable_dev = pch_enable, }; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 23476ec..78e4b4c 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -215,6 +215,6 @@ } struct chip_operations southbridge_ricoh_rl5c476_ops = { - CHIP_NAME("Ricoh RL5C476 CardBus Controller") + CHIP_NAME("Ricoh RL5C476 CardBus Controller"), .enable_dev = southbridge_init, }; diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index ccd3ce9..c55000d 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -73,5 +73,5 @@ }; struct chip_operations southbridge_ti_pci1x2x_ops = { - CHIP_NAME("TI PCI1x2x Cardbus controller") + CHIP_NAME("TI PCI1x2x Cardbus controller"), }; diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 6ef08a3..59ea313 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -80,5 +80,5 @@ }; struct chip_operations southbridge_ti_pci7420_ops = { - CHIP_NAME("Texas Instruments PCI7420/7620 Cardbus Controller") + CHIP_NAME("Texas Instruments PCI7420/7620 Cardbus Controller"), }; diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 4510c21..fa95e6d 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -103,6 +103,6 @@ } struct chip_operations superio_aspeed_ast2400_ops = { - CHIP_NAME("ASpeed AST2400/AST2500 Super I/O") + CHIP_NAME("ASpeed AST2400/AST2500 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index c690340..ba6170b 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -324,6 +324,6 @@ } struct chip_operations superio_common_ops = { - CHIP_NAME("Generic Super I/O") + CHIP_NAME("Generic Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c index 17fa379..0ac6d33 100644 --- a/src/superio/fintek/f71808a/superio.c +++ b/src/superio/fintek/f71808a/superio.c @@ -51,6 +51,6 @@ } struct chip_operations superio_fintek_f71808a_ops = { - CHIP_NAME("Fintek F71808A Super I/O") + CHIP_NAME("Fintek F71808A Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 1f44249..ae71920 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -33,6 +33,6 @@ } struct chip_operations superio_fintek_f71859_ops = { - CHIP_NAME("Fintek F71859 Super I/O") + CHIP_NAME("Fintek F71859 Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index c4e8dc9..513cbcc 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -50,6 +50,6 @@ } struct chip_operations superio_fintek_f71863fg_ops = { - CHIP_NAME("Fintek F71863FG Super I/O") + CHIP_NAME("Fintek F71863FG Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 3cfd387..cbc3259 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -107,6 +107,6 @@ } struct chip_operations superio_fintek_f71869ad_ops = { - CHIP_NAME("Fintek F71869AD Super I/O") + CHIP_NAME("Fintek F71869AD Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index 5304f9e..d5a3241 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -57,6 +57,6 @@ } struct chip_operations superio_fintek_f81803a_ops = { - CHIP_NAME("Fintek F81803A Super I/O") + CHIP_NAME("Fintek F81803A Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 9181bad..05d2c42 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -48,6 +48,6 @@ } struct chip_operations superio_fintek_f81865f_ops = { - CHIP_NAME("Fintek F81865F Super I/O") + CHIP_NAME("Fintek F81865F Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index 3803230..3b738c4 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -73,6 +73,6 @@ } struct chip_operations superio_fintek_f81866d_ops = { - CHIP_NAME("Fintek F81866AD-I Super I/O") + CHIP_NAME("Fintek F81866AD-I Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c index d135c0b..e0c6d5b 100644 --- a/src/superio/ite/it8528e/superio.c +++ b/src/superio/ite/it8528e/superio.c @@ -49,6 +49,6 @@ } struct chip_operations superio_ite_it8528e_ops = { - CHIP_NAME("ITE IT8528E Super I/O") + CHIP_NAME("ITE IT8528E Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c index c18c3ec..f65f4a0 100644 --- a/src/superio/ite/it8613e/superio.c +++ b/src/superio/ite/it8613e/superio.c @@ -63,6 +63,6 @@ } struct chip_operations superio_ite_it8613e_ops = { - CHIP_NAME("ITE IT8613E Super I/O") + CHIP_NAME("ITE IT8613E Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index 15e0071..8ffb079 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -60,6 +60,6 @@ } struct chip_operations superio_ite_it8623e_ops = { - CHIP_NAME("ITE IT8623E Super I/O") + CHIP_NAME("ITE IT8623E Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 17a1976..ddb454e 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -65,6 +65,6 @@ } struct chip_operations superio_ite_it8712f_ops = { - CHIP_NAME("ITE IT8712F Super I/O") + CHIP_NAME("ITE IT8712F Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index 1243e75..31be39b 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -71,6 +71,6 @@ } struct chip_operations superio_ite_it8718f_ops = { - CHIP_NAME("ITE IT8718F Super I/O") + CHIP_NAME("ITE IT8718F Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index 75d0be9..e88edb4 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -112,6 +112,6 @@ } struct chip_operations superio_ite_it8720f_ops = { - CHIP_NAME("ITE IT8720F Super I/O") + CHIP_NAME("ITE IT8720F Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index f69e1b0..39ef8d5 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -63,6 +63,6 @@ } struct chip_operations superio_ite_it8721f_ops = { - CHIP_NAME("ITE IT8721F Super I/O") + CHIP_NAME("ITE IT8721F Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 67ef218..59b9fea 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -60,6 +60,6 @@ } struct chip_operations superio_ite_it8728f_ops = { - CHIP_NAME("ITE IT8728F Super I/O") + CHIP_NAME("ITE IT8728F Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 82f30fa..b1e4d49 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -268,6 +268,6 @@ } struct chip_operations superio_ite_it8772f_ops = { - CHIP_NAME("ITE IT8772F Super I/O") + CHIP_NAME("ITE IT8772F Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8783ef/superio.c b/src/superio/ite/it8783ef/superio.c index d90ae5f..63cb09a 100644 --- a/src/superio/ite/it8783ef/superio.c +++ b/src/superio/ite/it8783ef/superio.c @@ -88,6 +88,6 @@ } struct chip_operations superio_ite_it8783ef_ops = { - CHIP_NAME("ITE IT8783E/F Super I/O") + CHIP_NAME("ITE IT8783E/F Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8784e/superio.c b/src/superio/ite/it8784e/superio.c index 85fc42e..615a2e3 100644 --- a/src/superio/ite/it8784e/superio.c +++ b/src/superio/ite/it8784e/superio.c @@ -82,6 +82,6 @@ } struct chip_operations superio_ite_it8784e_ops = { - CHIP_NAME("ITE IT8784E Super I/O") + CHIP_NAME("ITE IT8784E Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c index 8d9ec14..a626c2f 100644 --- a/src/superio/ite/it8786e/superio.c +++ b/src/superio/ite/it8786e/superio.c @@ -98,6 +98,6 @@ } struct chip_operations superio_ite_it8786e_ops = { - CHIP_NAME("ITE IT8786E Super I/O") + CHIP_NAME("ITE IT8786E Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 355aca4..b7c80d1c 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -41,6 +41,6 @@ } struct chip_operations superio_nsc_pc87382_ops = { - CHIP_NAME("NSC PC87382 Docking LPC Switch") + CHIP_NAME("NSC PC87382 Docking LPC Switch"), .enable_dev = enable_dev, }; diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index 88d4d36..93c1997 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -25,6 +25,6 @@ } struct chip_operations superio_nsc_pc87384_ops = { - CHIP_NAME("NSC PC87384 Super I/O") + CHIP_NAME("NSC PC87384 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index e65afea..a5ff9a5 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -35,6 +35,6 @@ } struct chip_operations superio_nsc_pc87392_ops = { - CHIP_NAME("NSC PC87392 Super I/O") + CHIP_NAME("NSC PC87392 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index be99f7f..16703d1 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -46,6 +46,6 @@ } struct chip_operations superio_nsc_pc87417_ops = { - CHIP_NAME("NSC PC87417 Super I/O") + CHIP_NAME("NSC PC87417 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index cfa2228..a68b7e3 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -232,6 +232,6 @@ } struct chip_operations superio_nuvoton_nct5104d_ops = { - CHIP_NAME("Nuvoton NCT5104D Super I/O") + CHIP_NAME("Nuvoton NCT5104D Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index ff37f5c..1205412 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -95,6 +95,6 @@ } struct chip_operations superio_nuvoton_nct5539d_ops = { - CHIP_NAME("NUVOTON NCT5539D Super I/O") + CHIP_NAME("NUVOTON NCT5539D Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 7e893ee..8e29cfc 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -104,6 +104,6 @@ } struct chip_operations superio_nuvoton_nct5572d_ops = { - CHIP_NAME("NUVOTON NCT5572D Super I/O") + CHIP_NAME("NUVOTON NCT5572D Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct6687d/superio.c b/src/superio/nuvoton/nct6687d/superio.c index a2eea8c..669e5f9 100644 --- a/src/superio/nuvoton/nct6687d/superio.c +++ b/src/superio/nuvoton/nct6687d/superio.c @@ -87,6 +87,6 @@ } struct chip_operations superio_nuvoton_nct6687d_ops = { - CHIP_NAME("NUVOTON NCT6687D Super I/O") + CHIP_NAME("NUVOTON NCT6687D Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index 4197d54..6c058ab 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -67,6 +67,6 @@ } struct chip_operations superio_nuvoton_nct6776_ops = { - CHIP_NAME("NUVOTON NCT6776 Super I/O") + CHIP_NAME("NUVOTON NCT6776 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 77058b0..a4b29fd 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -62,6 +62,6 @@ } struct chip_operations superio_nuvoton_nct6779d_ops = { - CHIP_NAME("NUVOTON NCT6779D Super I/O") + CHIP_NAME("NUVOTON NCT6779D Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 3244e05..28935b7 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -102,6 +102,6 @@ } struct chip_operations superio_nuvoton_nct6791d_ops = { - CHIP_NAME("NUVOTON NCT6791D Super I/O") + CHIP_NAME("NUVOTON NCT6791D Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 615bae5..72422be 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -460,6 +460,6 @@ } struct chip_operations superio_nuvoton_npcd378_ops = { - CHIP_NAME("NUVOTON NPCD378 Super I/O") + CHIP_NAME("NUVOTON NPCD378 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index 45c2e93..59fafa3 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -40,6 +40,6 @@ } struct chip_operations superio_nuvoton_wpcm450_ops = { - CHIP_NAME("Nuvoton WPCM450 Super I/O") + CHIP_NAME("Nuvoton WPCM450 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 293fe0e..ababab9 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -45,6 +45,6 @@ } struct chip_operations superio_renesas_m3885x_ops = { - CHIP_NAME("Renesas M3885x Super I/O") + CHIP_NAME("Renesas M3885x Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c index a62bba8..2cec395 100644 --- a/src/superio/smsc/fdc37n972/superio.c +++ b/src/superio/smsc/fdc37n972/superio.c @@ -46,6 +46,6 @@ } struct chip_operations superio_smsc_fdc37n972_ops = { - CHIP_NAME("SMSC FDC37N972 Super I/O") + CHIP_NAME("SMSC FDC37N972 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 862a77b..b7b44d4 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -14,7 +14,7 @@ static void kbc1100_init(struct device *dev); struct chip_operations superio_smsc_kbc1100_ops = { - CHIP_NAME("SMSC KBC1100 Super I/O") + CHIP_NAME("SMSC KBC1100 Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index cb297a5..5ee318b 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -58,6 +58,6 @@ } struct chip_operations superio_smsc_lpc47m10x_ops = { - CHIP_NAME("SMSC LPC47M10x Super I/O") + CHIP_NAME("SMSC LPC47M10x Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index e1e4883..3cfc547 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -14,7 +14,7 @@ static void lpc47m15x_init(struct device *dev); struct chip_operations superio_smsc_lpc47m15x_ops = { - CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") + CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index dcaf6e7..2ff2cbc 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -25,7 +25,7 @@ static void pnp_exit_conf_state(struct device *dev); struct chip_operations superio_smsc_lpc47n217_ops = { - CHIP_NAME("SMSC LPC47N217 Super I/O") + CHIP_NAME("SMSC LPC47N217 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 3712350..5ca8f9e 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -24,7 +24,7 @@ void lpc47n227_pnp_set_enable(struct device *dev, int enable); struct chip_operations superio_smsc_lpc47n227_ops = { - CHIP_NAME("SMSC LPC47N227 Super I/O") + CHIP_NAME("SMSC LPC47N227 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 6c8597c..d17537f 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -47,6 +47,6 @@ } struct chip_operations superio_smsc_mec1308_ops = { - CHIP_NAME("SMSC MEC1308 EC SuperIO Interface") + CHIP_NAME("SMSC MEC1308 EC SuperIO Interface"), .enable_dev = enable_dev }; diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c index 1ce1fd6..730674b 100644 --- a/src/superio/smsc/sch5545/superio.c +++ b/src/superio/smsc/sch5545/superio.c @@ -303,6 +303,6 @@ } struct chip_operations superio_smsc_sch5545_ops = { - CHIP_NAME("SMSC SCH5545 Super I/O") + CHIP_NAME("SMSC SCH5545 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/smsc/sch555x/ramstage.c b/src/superio/smsc/sch555x/ramstage.c index 2245001..d409886 100644 --- a/src/superio/smsc/sch555x/ramstage.c +++ b/src/superio/smsc/sch555x/ramstage.c @@ -136,6 +136,6 @@ } struct chip_operations superio_smsc_sch555x_ops = { - CHIP_NAME("SMSC SCH555x Super I/O") + CHIP_NAME("SMSC SCH555x Super I/O"), .enable_dev = sch555x_enable_dev, }; diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 3dcaae8..f052fd6 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -33,6 +33,6 @@ } struct chip_operations superio_smsc_sio1036_ops = { - CHIP_NAME("SMSC SIO1036 Super I/O") + CHIP_NAME("SMSC SIO1036 Super I/O"), .enable_dev = enable_dev }; diff --git a/src/superio/smsc/sio10n268/superio.c b/src/superio/smsc/sio10n268/superio.c index ca5a0c6..60c6e53 100644 --- a/src/superio/smsc/sio10n268/superio.c +++ b/src/superio/smsc/sio10n268/superio.c @@ -43,6 +43,6 @@ } struct chip_operations superio_smsc_sio10n268_ops = { - CHIP_NAME("SMSC SIO10N268 Super I/O") + CHIP_NAME("SMSC SIO10N268 Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index a182d90..2699160 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -281,6 +281,6 @@ } struct chip_operations superio_smsc_smscsuperio_ops = { - CHIP_NAME("Various SMSC Super I/Os") + CHIP_NAME("Various SMSC Super I/Os"), .enable_dev = enable_dev }; diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 2641cb3..8087d61 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -68,6 +68,6 @@ } struct chip_operations superio_winbond_w83627dhg_ops = { - CHIP_NAME("Winbond W83627DHG Super I/O") + CHIP_NAME("Winbond W83627DHG Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 1e36048..aedcdf0 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -129,6 +129,6 @@ } struct chip_operations superio_winbond_w83627ehg_ops = { - CHIP_NAME("Winbond W83627EHG Super I/O") + CHIP_NAME("Winbond W83627EHG Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index de2a0c6..f1913a1 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -129,6 +129,6 @@ } struct chip_operations superio_winbond_w83627hf_ops = { - CHIP_NAME("Winbond W83627HF Super I/O") + CHIP_NAME("Winbond W83627HF Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 4276da6..93e71d7 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -50,6 +50,6 @@ } struct chip_operations superio_winbond_w83627thg_ops = { - CHIP_NAME("Winbond W83627THG Super I/O") + CHIP_NAME("Winbond W83627THG Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 4b54bac..0e7d248 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -101,6 +101,6 @@ } struct chip_operations superio_winbond_w83627uhg_ops = { - CHIP_NAME("Winbond W83627UHG Super I/O") + CHIP_NAME("Winbond W83627UHG Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index a5abe61..e897c66 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -103,6 +103,6 @@ } struct chip_operations superio_winbond_w83667hg_a_ops = { - CHIP_NAME("WINBOND W83667HG-A Super I/O") + CHIP_NAME("WINBOND W83667HG-A Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index 4187b52..3fd1e6b 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -50,6 +50,6 @@ } struct chip_operations superio_winbond_w83977tf_ops = { - CHIP_NAME("Winbond W83977TF Super I/O") + CHIP_NAME("Winbond W83977TF Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c index a692eeb..6a3a70c 100644 --- a/src/superio/winbond/wpcd376i/superio.c +++ b/src/superio/winbond/wpcd376i/superio.c @@ -61,6 +61,6 @@ } struct chip_operations superio_winbond_wpcd376i_ops = { - CHIP_NAME("Winbond WPCD376I Super I/O") + CHIP_NAME("Winbond WPCD376I Super I/O"), .enable_dev = enable_dev, }; diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 89314ba..7fbba84 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -10,7 +10,7 @@ #include "../opensil.h" struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = { - CHIP_NAME("AMD GENOA MPIO") + CHIP_NAME("AMD GENOA MPIO"), }; static void nbio_config(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/80228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Gerrit-Change-Number: 80228 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: Documentation: Describe how SMMSTORE can be used safely
by Patrick Georgi (Code Review) 27 Jan '24

27 Jan '24

Attention is currently required from: Benjamin Doron, Nico Huber. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79095?usp=email ) Change subject: Documentation: Describe how SMMSTORE can be used safely ...................................................................... Patch Set 2: (2 comments) File Documentation/drivers/smmstore.md: https://review.coreboot.org/c/coreboot/+/79095/comment/ea19c22b_68a0e94a : PS2, Line 171: An attacker could mess with future calls into the APIs, but they : can already do so: Other common APIs for boot level variable are : implemented in RAM as well, so they can easily be defused. > nit: variables? Also, are you thinking of coreboot CMOS or UEFI variables here? Or both, I suppose. […] The attack vector is overwriting the UEFI entry point to the variable functions which isn't in SMM but in RAM: the modified-UEFI could then pretend to do whatever variable updates were requested that it doesn't want to see done (e.g. installing a blocklist), and even cache the data for the current run to return "good" values, but never actually write it down. In terms of UEFI Secure Boot: suppose some malicious boot level code is accidentally signed with a valid key, and the system wants to push a dbx update to block that malicious code from being accepted. On systems where that code already runs, to ensure its own persistence across boots it could intercept SetVariable and GetVariable and pretend that dbx is updated when it isn't. But yes, I need to see how to put that in the doc more clearly, so thanks for the feedback. https://review.coreboot.org/c/coreboot/+/79095/comment/b116b201_9de6c630 : PS2, Line 177: As a remedy, CLEAR could be disabled after the initial repacking, : within the boot process, so that SMMSTORE becomes an append-only : store. In this case, the attacker could fill up the buffer, leading : to a DoS of the variable store until it's repacked. As described : earlier, once there's an attacker on the system, the variable store : lost its function until the attacker has been evicted, anyway. > Raw WRITE has to be protected to, because writing 0xFF is equivalent to clearing. […] Raw write from outside SMM is supposed to be disabled in the SMMSTORE model, yes. I'll make that clearer. SMM is used to ensure that the flash region becomes append-only (except for CLEAR) -- To view, visit https://review.coreboot.org/c/coreboot/+/79095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48f44d3416d210e1e6b19d18cad787e380ffeebc Gerrit-Change-Number: 79095 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sat, 27 Jan 2024 20:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: tree: Use read{64;32;16;8}p and write{64;32;16;8}p
by Elyes Haouas (Code Review) 27 Jan '24

27 Jan '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80192?usp=email ) Change subject: tree: Use read{64;32;16;8}p and write{64;32;16;8}p ...................................................................... tree: Use read{64;32;16;8}p and write{64;32;16;8}p Change-Id: Ic596fa01c45d2454999b273fcaad11e3e0733f81 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/riscv/arch_timer.c M src/device/oprom/realmode/x86.c M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/clint.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/protectli/vault_cml/mainboard.c M src/mainboard/siemens/fa_ehl/romstage_fsp_params.c M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/intel/txt/romstage.c M src/security/intel/txt/txtlib.c M src/soc/amd/genoa_poc/uart.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/meteorlake/crashlog.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v2.c M src/soc/mediatek/common/ufs.c M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8186/ddp.c M src/soc/mediatek/mt8186/gic.c M src/soc/mediatek/mt8186/spm.c M src/soc/mediatek/mt8192/ddp.c M src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/ddp.c M src/soc/mediatek/mt8195/hdmi.c M src/soc/mediatek/mt8195/usb.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra210/bootblock.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/i2c6.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/qualcomm/common/qupv3_config.c M src/soc/qualcomm/sc7280/socinfo.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/smp.c M src/soc/sifive/fu540/clint.c 53 files changed, 202 insertions(+), 195 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80192/1 diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index ad678b7..6738751 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -10,5 +10,5 @@ { if (HLS()->time == NULL) die("time not set in HLS"); - mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time))); + mono_time_set_usecs(mt, (long)read64p((HLS()->time))); } diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 367614d..dafb949 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -72,7 +72,7 @@ memcpy((void *)0xfffd9, &ident, 7); /* system model: IBM-AT */ - write8((void *)0xffffe, 0xfc); + write8p(0xffffe, 0xfc); } static int (*intXX_handler[256])(void) = { NULL }; diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 10827fa..3436568 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,5 +14,5 @@ void set_msip(int hartid, int val) { - write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); + write32p((QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); } diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 4d45bce..f510e0b 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -15,5 +15,5 @@ void set_msip(int hartid, int val) { - write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); + write32p((SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); } diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e45ff8f..0dd1360 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -22,7 +22,7 @@ static void configure_sdhci(void) { /* Program eMMC drive strength to 16/10/10 mA */ - write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4); + write32p(SDC1_TLMM_CFG_ADDR, 0x9FE4); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/protectli/vault_cml/mainboard.c b/src/mainboard/protectli/vault_cml/mainboard.c index 1e06fc5..515cb70 100644 --- a/src/mainboard/protectli/vault_cml/mainboard.c +++ b/src/mainboard/protectli/vault_cml/mainboard.c @@ -51,14 +51,14 @@ static bool is_descriptor_writeable(uint8_t *desc) { /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { + if (read32p((desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { printk(BIOS_ERR, "Flash Descriptor is not valid\n"); printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n"); return false; } /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + if (!((read32p((desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); return false; } diff --git a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c index 506bcc6..7337e27 100644 --- a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c @@ -22,7 +22,7 @@ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index d386d75..b74a60e 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -26,7 +26,7 @@ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index b78394a..6fba958 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -100,7 +100,7 @@ void intel_txt_log_spad(void) { - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); printk(BIOS_INFO, "TXT-STS: ACM verification "); @@ -138,8 +138,8 @@ if (!CONFIG(INTEL_TXT)) return false; - ret = (read8((void *)TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || - (read64((void *)TXT_E2STS) & TXT_E2STS_SECRET_STS); + ret = (read8p(TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || + (read64p(TXT_E2STS) & TXT_E2STS_SECRET_STS); if (ret) printk(BIOS_CRIT, "TXT-STS: Secrets in memory!\n"); @@ -154,10 +154,10 @@ * Chapter B.1.7 and B.1.9 * Intel TXT Software Development Guide (Document: 315168-015) */ - uint32_t reg = read32((void *)TXT_VER_FSBIF); + uint32_t reg = read32p(TXT_VER_FSBIF); if (reg == 0 || reg == UINT32_MAX) - reg = read32((void *)TXT_VER_QPIIF); + reg = read32p(TXT_VER_QPIIF); return (reg & TXT_VER_PRODUCTION_FUSED) ? true : false; } @@ -320,11 +320,11 @@ return; /* FIXME: Do we need to program these two? */ - //write32((void *)MCU_BASE_ADDR, 0xffe1a990); - //write32((void *)APINIT_ADDR, 0xfffffff0); + //write32p(MCU_BASE_ADDR, 0xffe1a990); + //write32p(APINIT_ADDR, 0xfffffff0); - write32((void *)BIOACM_ADDR, (uintptr_t)acm_data); - write32((void *)SEMAPHORE, 0); + write32p(BIOACM_ADDR, (uintptr_t)acm_data); + write32p(SEMAPHORE, 0); /* * The time SCLEAN will take depends on the installed RAM size. @@ -364,14 +364,14 @@ cbfs_unmap(acm_data); - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); if (acm_status & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "TEE-TXT: FATAL ACM launch error !\n"); /* * WARNING ! * To clear TXT.BIOSACM.ERRORCODE you must issue a cold reboot! */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); return -1; } @@ -460,7 +460,7 @@ if ((eax & 0x7d) != 0x7d) failure = true; - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) { printk(BIOS_INFO, "TEE-TXT: TXT disabled by BIOS policy in FIT.\n"); diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 6485b86..e1692cf 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -35,7 +35,7 @@ */ static void log_txt_error(const char *phase) { - const uint64_t txt_error = read64((void *)TXT_ERROR); + const uint64_t txt_error = read64p(TXT_ERROR); if (txt_error & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "%s: Error occurred\n", phase); @@ -63,9 +63,9 @@ printk(BIOS_INFO, "TEE-TXT: State of ACM and ucode update:\n"); - bios_acm_error = read32((void *)TXT_BIOSACM_ERRORCODE); - acm_status = read64((void *)TXT_SPAD); - txt_error = read64((void *)TXT_ERROR); + bios_acm_error = read32p(TXT_BIOSACM_ERRORCODE); + acm_status = read64p(TXT_SPAD); + txt_error = read64p(TXT_ERROR); /* Errors by BIOS ACM or FIT */ if ((txt_error & ACMERROR_TXT_VALID) && @@ -81,10 +81,10 @@ } /* Check for fatal ACM error and TXT reset */ - uint8_t error = read8((void *)TXT_ESTS); + uint8_t error = read8p(TXT_ESTS); if (error & TXT_ESTS_TXT_RESET_STS) { printk(BIOS_CRIT, "TXT-STS: Intel TXT reset detected\n"); - intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + intel_txt_log_acm_error(read32p(TXT_ERROR)); } } @@ -178,12 +178,12 @@ { printk(BIOS_INFO, "TEE-TXT: Chipset Key Hash 0x"); for (int i = 0; i < TXT_ACM_KEY_HASH_LEN; i++) { - printk(BIOS_INFO, "%llx", read64((void *)TXT_ACM_KEY_HASH + + printk(BIOS_INFO, "%llx", read64p(TXT_ACM_KEY_HASH + (i * sizeof(uint64_t)))); } printk(BIOS_INFO, "\n"); - printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32((void *)TXT_DIDVID)); + printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32p(TXT_DIDVID)); printk(BIOS_INFO, "TEE-TXT: production fused chipset: %s\n", intel_txt_chipset_is_production_fused() ? "true" : "false"); } @@ -199,18 +199,18 @@ uint64_t reg64; - reg64 = read64((void *)TXT_HEAP_BASE); + reg64 = read64p(TXT_HEAP_BASE); if ((reg64 != 0 && reg64 != ~0UL) && - (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) + (read64p((uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t)); printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx, size %zu MiB\n", tseg_base, tseg_size / MiB); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64((void *)TXT_SINIT_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64((void *)TXT_MSEG_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64((void *)TXT_MSEG_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64p(TXT_HEAP_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64p(TXT_HEAP_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64p(TXT_SINIT_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64p(TXT_SINIT_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64p(TXT_MSEG_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64p(TXT_MSEG_SIZE)); if (bdr) { printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.bios_sinit_size 0x%x\n", diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 8a266a4..5c03da9 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -20,8 +20,8 @@ /* FIXME: Seems to work only on some platforms */ static void log_ibb_measurements(void) { - const uint64_t mseg_size = read64((void *)TXT_MSEG_SIZE); - uint64_t mseg_base = read64((void *)TXT_MSEG_BASE); + const uint64_t mseg_size = read64p(TXT_MSEG_SIZE); + uint64_t mseg_base = read64p(TXT_MSEG_BASE); if (!mseg_size || !mseg_base || mseg_size <= mseg_base) return; @@ -34,14 +34,14 @@ printk(BIOS_INFO, "TEE-TXT: IBB Hash 0x"); for (; mseg_base < mseg_size; mseg_base++) - printk(BIOS_INFO, "%02X", read8((void *)(uintptr_t)mseg_base)); + printk(BIOS_INFO, "%02X", read8p((uintptr_t)mseg_base)); printk(BIOS_INFO, "\n"); } void bootmem_platform_add_ranges(void) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -67,7 +67,7 @@ BM_MEM_RESERVED); const union dpr_register dpr = { - .raw = read32((void *)TXT_DPR), + .raw = read32p(TXT_DPR), }; const uint32_t dpr_base = dpr.top - dpr.size * MiB; @@ -78,13 +78,13 @@ static bool get_wake_error_status(void) { - const uint8_t error = read8((void *)TXT_ESTS); + const uint8_t error = read8p(TXT_ESTS); return !!(error & TXT_ESTS_WAKE_ERROR_STS); } static void check_secrets_txt(void *unused) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -102,7 +102,7 @@ intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); /* Should never reach this point ... */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); die("Waiting for platform reset...\n"); } } @@ -121,7 +121,7 @@ */ static void init_intel_txt(void *unused) { - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -250,10 +250,10 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec); - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, sinit_base, - read64((void *)TXT_SINIT_SIZE)); + read64p(TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -295,9 +295,9 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec); - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); /* Clear SINIT ACM memory */ - memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + memset(sinit_base, 0, read64p(TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -318,7 +318,7 @@ static void txt_initialize_heap(void) { /* Fill TXT.HEAP.BASE with 4 subregions */ - u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); + u8 *heap_struct = (void *)((uintptr_t)read64p(TXT_HEAP_BASE)); /* * Since we may have either BIOS ACM or both BIOS and SINIT ACMs in @@ -365,7 +365,7 @@ if (skip_intel_txt_lockdown()) return; - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); uint32_t txt_feature_flags = 0; uintptr_t tseg_base; @@ -401,7 +401,7 @@ * Chapter 5.5.6.1 DMA Protection Memory Region */ - const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & + const u8 dpr_capable = !!(read64p(TXT_CAPABILITIES) & TXT_CAPABILITIES_DPR); printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); @@ -443,28 +443,28 @@ dpr.prs = 0; dpr.epm = 0; - write64((void *)TXT_DPR, dpr.raw); + write64p(TXT_DPR, dpr.raw); printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", - read32((void *)TXT_DPR)); + read32p(TXT_DPR)); } /* * Document Number: 558294 * Chapter 5.5.6.3 Intel TXT Heap Memory Region */ - write64((void *)TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); - write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); + write64p(TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); + write64p(TXT_HEAP_BASE, + ALIGN_DOWN(tseg_base - read64p(TXT_HEAP_SIZE), 4096)); /* * Document Number: 558294 * Chapter 5.5.6.2 SINIT Memory Region */ - write64((void *)TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); - write64((void *)TXT_SINIT_BASE, - ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - - read64((void *)TXT_SINIT_SIZE), 4096)); + write64p(TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); + write64p(TXT_SINIT_BASE, + ALIGN_DOWN(read64p(TXT_HEAP_BASE) - + read64p(TXT_SINIT_SIZE), 4096)); /* * FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG. @@ -474,8 +474,8 @@ * Chapter 5.10.1 SMM in the Intel TXT for Servers Environment * Disable MSEG. */ - write64((void *)TXT_MSEG_SIZE, 0); - write64((void *)TXT_MSEG_BASE, 0); + write64p(TXT_MSEG_SIZE, 0); + write64p(TXT_MSEG_BASE, 0); /* Only initialize the heap on regular boots */ if (!acpi_is_wakeup_s3()) diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index aa7cc2c..643e7a9 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -63,7 +63,7 @@ return; } - const uint8_t txt_ests = read8((void *)TXT_ESTS); + const uint8_t txt_ests = read8p(TXT_ESTS); const bool establishment = is_establishment_bit_asserted(); const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); diff --git a/src/security/intel/txt/txtlib.c b/src/security/intel/txt/txtlib.c index 5478206..6ce86a3 100644 --- a/src/security/intel/txt/txtlib.c +++ b/src/security/intel/txt/txtlib.c @@ -20,7 +20,7 @@ stopwatch_init_msecs_expire(&timer, 50); while (true) { - access = read8((void *)TPM_ACCESS_REG); + access = read8p(TPM_ACCESS_REG); /* Register returns all ones if TPM is missing */ if (access == 0xff) diff --git a/src/soc/amd/genoa_poc/uart.c b/src/soc/amd/genoa_poc/uart.c index df8c54f..ffc5668 100644 --- a/src/soc/amd/genoa_poc/uart.c +++ b/src/soc/amd/genoa_poc/uart.c @@ -34,5 +34,5 @@ void clear_uart_legacy_config(void) { - write16((void *)FCH_LEGACY_UART_DECODE, 0); + write16p(FCH_LEGACY_UART_DECODE, 0); } diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 58970e83..ec2a54c 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -204,8 +204,8 @@ community->gpio_to_pad[gpio], gpio); #endif /* Write pad configurations to conf0 and conf1 register */ - write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0); - write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32p((reg + PAD_CONF0_REG), config->pad_conf0); + write32p((reg + PAD_CONF1_REG), config->pad_conf1); } } @@ -215,14 +215,14 @@ #endif /* Wake */ - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); + write32p((community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); /* Wake mask config for communities with 2 regs */ if (community->gpio_count > 32) - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); + write32p((community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); /* Interrupt */ - write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); + write32p((community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); } void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) @@ -233,7 +233,7 @@ * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg * to allow the SW interrupt mask register to be set */ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); + write32p((COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); printk(BIOS_DEBUG, "north\n"); setup_gpios(config->north, &gpnorth_community); diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index d476d5d..15a17b7 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -37,41 +37,41 @@ static void lpc_gpio_config(u32 cycle) { if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_PD20K(1)); } else { /* Resume cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); } } diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 92632d8..d776c6a 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -122,8 +122,8 @@ /* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); } static void lpe_init(struct device *dev) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97c..caa62bc 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -248,7 +248,7 @@ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); /* Use IRQ9 for SCI Interrupt */ - write32((void *)(ilb_base + ACTL), 0); + write32p((ilb_base + ACTL), 0); isa_dma_init(); @@ -256,11 +256,11 @@ /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) - write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); + write8p((pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); /* Set up the per device PIRQ routing base on static config. */ for (i = 0; i < NUM_IR_DEVS; i++) - write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); + write16p((ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..7cabcf64 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -8,6 +8,7 @@ #include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <string.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> @@ -168,7 +169,7 @@ uint64_t vtbar; unsigned long tmp = current; - vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; + vtbar = read64p((DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar); if (!vtbar) return current; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index ea99051..c85a157 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -65,7 +65,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_RXD), reg32); } @@ -77,31 +77,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_TXD), reg32); } // UART0_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_2) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_2 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK), reg32); } // UART0_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_3) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_3 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N), reg32); } @@ -115,7 +115,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_RXD), reg32); } @@ -127,31 +127,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_TXD), reg32); } // UART1_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT), reg32); } // UART1_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT), reg32); } diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 299f950..380e619 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -111,7 +111,7 @@ PadNumber %= 8; Mask = ((1 << 1) | (1 << 0)) << (PadNumber * 4); - PadOwnRegValue = read32((void *)PCH_PCR_ADDRESS( + PadOwnRegValue = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, RegOffset)); *PadOwnVal = (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4)); @@ -379,7 +379,7 @@ // PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; - Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg)); FinalValue = ((Data32 & (~Dw0RegMask)) | Dw0Reg); @@ -408,7 +408,7 @@ ~(uint32_t)Dw0RegMask, (uint32_t)Dw0Reg); } - Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4)); FinalValue = ((Data32 & (~Dw1RegMask)) | Dw1Reg); if (Data32 != FinalValue) { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1e..7eeb3c2 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -320,60 +320,60 @@ config_t *config = config_of(dev); /* Initialize PIRQ Routings */ - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), config->pirqa_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), config->pirqb_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), config->pirqc_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), config->pirqd_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), config->pirqe_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), config->pirqf_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), config->pirqg_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), config->pirqh_routing); /* Initialize device's Interrupt Routings */ - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), config->ir00_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), config->ir01_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), config->ir02_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), config->ir03_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), config->ir04_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), config->ir05_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), config->ir06_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), config->ir07_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), config->ir08_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), config->ir09_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), config->ir10_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), config->ir11_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), config->ir12_routing); /* Initialize device's Interrupt Polarity Control */ - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), config->ipc0); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), config->ipc1); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), config->ipc2); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), config->ipc3); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..20430b8 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -68,7 +68,7 @@ if (silicon_stepping() == SILICON_REV_DENVERTON_B0) { if (!(pci_read_config32(dev, GEN_PMCON_B) & GEN_PMCON_B_RTC_PWR_STS)) { - if (read32((void *)(pwrm_base + 0x124)) + if (read32p((pwrm_base + 0x124)) & ((1 << 11) | (1 << 12))) { /* Performs a global reset */ printk(BIOS_DEBUG, diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 3fb5d75..ee4ef8f 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -39,9 +39,9 @@ printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* Enable AHCI Mode */ - reg32 = read32((void *)(abar + 0x04)); + reg32 = read32p((abar + 0x04)); reg32 |= (1 << 31); - write32((void *)(abar + 0x04), reg32); + write32p((abar + 0x04), reg32); } static void sata_enable(struct device *dev) { /* TODO */ } diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 52d2371..b3159f5 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -5,6 +5,7 @@ #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <delay.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <intelblocks/crashlog.h> #include <intelblocks/pmc_ipc.h> @@ -34,7 +35,7 @@ static u64 get_disc_tab_header(void) { - return read64((void *)disc_tab_addr); + return read64p(disc_tab_addr); } /* Get the SRAM BAR. */ @@ -362,7 +363,7 @@ break; } - cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset)); + cpu_cl_disc_tab.buffers[i].data = read64p((disc_tab_addr + cur_offset)); printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, cpu_cl_disc_tab.buffers[i].fields.offset); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 9d2df2c..0e10ab5 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -32,7 +32,7 @@ { /* PMC controller is hidden - hence PWRMBASE can't be accessbile using PCI cfg space */ uintptr_t pmc_bar = PCH_PWRM_BASE_ADDRESS; - return read32((void *)pmc_bar + PMC_ACPI_CNT); + return read32p(pmc_bar + PMC_ACPI_CNT); } void soc_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 3485449..c16ccf1 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -21,7 +21,7 @@ for (j = 0; j < TRACKER_NUM; j++) { tra = &tracker_data[j]; - if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + if (!(read32p((tra->base_addr)) & tra->timeout)) continue; printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); @@ -29,7 +29,7 @@ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offset[k] + i * 4; - printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); + printk(BIOS_INFO, "%#lx:%#x,", reg, read32p(reg)); if (i % 4 == 3 || i == size - 1) printk(BIOS_INFO, "\n"); diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index fecde16..5cb90fc 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -57,16 +57,16 @@ * peri tracker clock: 78MHz */ val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p((INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32p((INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p((PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32p((PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); /* * Enable infra/peri tracker. @@ -77,6 +77,6 @@ * bit[14] - BUS_OT_WEN_CTRL */ val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); } diff --git a/src/soc/mediatek/common/ufs.c b/src/soc/mediatek/common/ufs.c index 2537fa7..8cab08e 100644 --- a/src/soc/mediatek/common/ufs.c +++ b/src/soc/mediatek/common/ufs.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/mmio.h> #include <soc/ufs.h> void ufs_disable_refclk(void) { /* disable ref clock to let UFSHCI release SPM signal */ - write32((void *)UFS_REFCLK_CTRL, 0); + write32p(UFS_REFCLK_CTRL, 0); } diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 395c821..cd5e831 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -70,7 +70,7 @@ { disp_clock_on(); /* Turn off M4U port. */ - write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0); + write32p((SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0); } void mtk_ddp_mode_set(const struct edid *edid) diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c index 5a5f544..e897cb3 100644 --- a/src/soc/mediatek/mt8186/ddp.c +++ b/src/soc/mediatek/mt8186/ddp.c @@ -6,6 +6,7 @@ */ #include <console/console.h> +#include <device/mmio.h> #include <edid.h> #include <soc/addressmap.h> #include <soc/ddp.h> @@ -138,7 +139,7 @@ disp_clock_on(); /* Turn off M4U port */ - write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); + write32p((SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) diff --git a/src/soc/mediatek/mt8186/gic.c b/src/soc/mediatek/mt8186/gic.c index ac07764..f18b918 100644 --- a/src/soc/mediatek/mt8186/gic.c +++ b/src/soc/mediatek/mt8186/gic.c @@ -14,7 +14,7 @@ int i; for (i = 3; i < 15; i++) { - write32((void *)((uintptr_t)MCUSYS_BASE + 0xA600 + i * 4), 0); - write32((void *)((uintptr_t)MCUSYS_BASE + 0xA650 + i * 4), 0xFFFFFFFF); + write32p(((uintptr_t)MCUSYS_BASE + 0xA600 + i * 4), 0); + write32p(((uintptr_t)MCUSYS_BASE + 0xA650 + i * 4), 0xFFFFFFFF); } } diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c index 00e2c27..04680b1 100644 --- a/src/soc/mediatek/mt8186/spm.c +++ b/src/soc/mediatek/mt8186/spm.c @@ -6,6 +6,7 @@ */ #include <assert.h> +#include <device/mmio.h> #include <soc/mcu_common.h> #include <soc/spm.h> @@ -425,10 +426,10 @@ write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); /* Enable Side-Band */ - write32((void *)AP_PLL_CON3, APMIX_CON3_DEF); - write32((void *)AP_PLL_CON4, APMIX_CON4_DEF); - write32((void *)CLK_SCP_CFG_0, SCP_CFG0_DEF); - write32((void *)CLK_SCP_CFG_1, SCP_CFG1_DEF); + write32p(AP_PLL_CON3, APMIX_CON3_DEF); + write32p(AP_PLL_CON4, APMIX_CON4_DEF); + write32p(CLK_SCP_CFG_0, SCP_CFG0_DEF); + write32p(CLK_SCP_CFG_1, SCP_CFG1_DEF); /* Init VCORE DVFS Status */ SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c index f03a902..a8875e85 100644 --- a/src/soc/mediatek/mt8192/ddp.c +++ b/src/soc/mediatek/mt8192/ddp.c @@ -171,7 +171,7 @@ { disp_clock_on(); /* Turn off M4U port. */ - write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); + write32p((SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } void mtk_ddp_mode_set(const struct edid *edid) diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c index 0c8d10f..dc635b4 100644 --- a/src/soc/mediatek/mt8195/apusys_devapc.c +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <console/console.h> +#include <device/mmio.h> #include <soc/apusys_devapc.h> #include <soc/devapc.h> @@ -181,7 +182,7 @@ for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { for (i = 0U; i < reg_num; i++) printk(BIOS_DEBUG, "[NOCDAPC] D%ld_APC_%ld: %#x\n", d, i, - read32((void *)(APUSYS_NOC_DAPC_AO_BASE + d * 0x40 + i * 4))); + read32p((APUSYS_NOC_DAPC_AO_BASE + d * 0x40 + i * 4))); } printk(BIOS_DEBUG, "[NOCDAPC] APC_CON: %#x\n", read32(APUSYS_NOC_DAPC_CON)); } @@ -222,7 +223,7 @@ for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { for (i = 0U; i < reg_num; i++) printk(BIOS_DEBUG, "[APUAPC] D%ld_APC_%ld: %#x\n", d, i, - read32((void *)(APUSYS_APC_AO_BASE + d * 0x40 + i * 4))); + read32p((APUSYS_APC_AO_BASE + d * 0x40 + i * 4))); } printk(BIOS_DEBUG, "[APUAPC] APC_CON: %#x\n", read32(APUSYS_APC_CON)); } diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c index 2bd95a2..0543ef4 100644 --- a/src/soc/mediatek/mt8195/ddp.c +++ b/src/soc/mediatek/mt8195/ddp.c @@ -147,7 +147,7 @@ disp_clock_on(); /* Turn off M4U port. */ - write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); + write32p((SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) diff --git a/src/soc/mediatek/mt8195/hdmi.c b/src/soc/mediatek/mt8195/hdmi.c index 9b343f4..65adee4 100644 --- a/src/soc/mediatek/mt8195/hdmi.c +++ b/src/soc/mediatek/mt8195/hdmi.c @@ -11,15 +11,15 @@ setbits32((void *)HDMI_PROTECT_REG, BIT(0) | BIT(1)); /* HDMI-RX powerdown */ - write32((void *)HDMI_RX_PDN_0_REG, HDMI_RX_PDN_0_VAL); - write32((void *)HDMI_RX_PDN_1_REG, HDMI_RX_PDN_1_VAL); - write32((void *)HDMI_RX_PDN_2_REG, HDMI_RX_PDN_2_VAL); - write32((void *)HDMI_RX_PDN_3_REG, HDMI_RX_PDN_3_VAL); - write32((void *)HDMI_RX_PDN_4_REG, HDMI_RX_PDN_4_VAL); - write32((void *)HDMI_RX_PDN_5_REG, HDMI_RX_PDN_5_VAL); - write32((void *)HDMI_RX_PDN_6_REG, HDMI_RX_PDN_6_VAL); - write32((void *)HDMI_RX_PDN_7_REG, HDMI_RX_PDN_7_VAL); + write32p(HDMI_RX_PDN_0_REG, HDMI_RX_PDN_0_VAL); + write32p(HDMI_RX_PDN_1_REG, HDMI_RX_PDN_1_VAL); + write32p(HDMI_RX_PDN_2_REG, HDMI_RX_PDN_2_VAL); + write32p(HDMI_RX_PDN_3_REG, HDMI_RX_PDN_3_VAL); + write32p(HDMI_RX_PDN_4_REG, HDMI_RX_PDN_4_VAL); + write32p(HDMI_RX_PDN_5_REG, HDMI_RX_PDN_5_VAL); + write32p(HDMI_RX_PDN_6_REG, HDMI_RX_PDN_6_VAL); + write32p(HDMI_RX_PDN_7_REG, HDMI_RX_PDN_7_VAL); /* HDMI-TX powerdown */ - write32((void *)HDMI_TX_PDN_REG, HDMI_TX_PDN_VAL); + write32p(HDMI_TX_PDN_REG, HDMI_TX_PDN_VAL); } diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index 6902bd8..d58071d 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -18,7 +18,7 @@ SET32_BITFIELDS(&phy->u3phyd.phyd_reserved, AUTO_LOAD_DIS, 1); - phy_set_val = read32((void *)USB_PHY_SETTING_REG); + phy_set_val = read32p(USB_PHY_SETTING_REG); /* TX imp */ write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT; diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index bc026c1..8bc443b 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -22,7 +22,7 @@ uintptr_t gp_hidrev= (uintptr_t)TEGRA_APB_MISC_BASE + MISC_GP_HIDREV; uint32_t reg; - reg = read32((void *)(gp_hidrev)); + reg = read32p((gp_hidrev)); id->hid_fam = (reg >> 0) & 0x0f; id->chip_id = (reg >> 8) & 0xff; diff --git a/src/soc/nvidia/tegra124/monotonic_timer.c b/src/soc/nvidia/tegra124/monotonic_timer.c index 52d5335..de90c0b 100644 --- a/src/soc/nvidia/tegra124/monotonic_timer.c +++ b/src/soc/nvidia/tegra124/monotonic_timer.c @@ -6,5 +6,5 @@ void timer_monotonic_get(struct mono_time *mt) { - mono_time_set_usecs(mt, read32((void *)TEGRA_TMRUS_BASE)); + mono_time_set_usecs(mt, read32p(TEGRA_TMRUS_BASE)); } diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index e8c4324..d1f37b0 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -33,9 +33,9 @@ // pick up the ODMDATA word at BCT offset 0x6A8. I could use a BCT // struct header from cbootimage, but it seems like overkill for this. - bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); + bct_offset = read32p((TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { - odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); + odmdata = read32p((bct_offset + ODMDATA_OFFSET_IN_BCT)); write32(&pmc->odmdata, odmdata); } } @@ -130,10 +130,10 @@ val = wa_op->val; break; case OP_OR: - val = read32((void *)wa_op->reg) | wa_op->val; + val = read32p(wa_op->reg) | wa_op->val; break; case OP_AND: - val = read32((void *)wa_op->reg) & wa_op->val; + val = read32p(wa_op->reg) & wa_op->val; break; case OP_UDELAY: udelay(wa_op->val); @@ -141,7 +141,7 @@ default: continue; } - write32((void *)wa_op->reg, val); + write32p(wa_op->reg, val); } } diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 4433d7e..4ff859c 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -576,7 +576,7 @@ CLK_M_DIVISOR_BY_2); /* TIMERUS needs to be adjusted for new 19.2MHz CLK_M rate */ - write32((void *)TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG, + write32p(TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG, TIMERUS_USEC_CFG_19P2_CLK_M); init_pllc(osc); diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c index 338ac8b..cbadeac 100644 --- a/src/soc/nvidia/tegra210/i2c6.c +++ b/src/soc/nvidia/tegra210/i2c6.c @@ -52,9 +52,9 @@ clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE); /* Now we can write the I2C6 mux in DPAUX */ - write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); + write32p(DPAUX_HYBRID_PADCTL, I2C6_PADCTL); /* Finally, power up the pads */ - write32((void *)DPAUX_HYBRID_SPARE, 0); + write32p(DPAUX_HYBRID_SPARE, 0); /* * Delay before turning off Host1X/DPAUX clocks. diff --git a/src/soc/nvidia/tegra210/monotonic_timer.c b/src/soc/nvidia/tegra210/monotonic_timer.c index 52d5335..de90c0b 100644 --- a/src/soc/nvidia/tegra210/monotonic_timer.c +++ b/src/soc/nvidia/tegra210/monotonic_timer.c @@ -6,5 +6,5 @@ void timer_monotonic_get(struct mono_time *mt) { - mono_time_set_usecs(mt, read32((void *)TEGRA_TMRUS_BASE)); + mono_time_set_usecs(mt, read32p(TEGRA_TMRUS_BASE)); } diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 45b221b..e313ef0 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -27,13 +27,13 @@ #define WRAP_TO_INCR_SLAVE1 (0x1 << 28) #define WRAP_TO_INCR_SLAVE2 (0x1 << 29) - reg = read32((void *)TEGRA_MSELECT_CONFIG); + reg = read32p(TEGRA_MSELECT_CONFIG); /* Disable error mechanism */ reg &= ~(ERR_RESP_EN_SLAVE1 | ERR_RESP_EN_SLAVE2); /* Enable WRAP type conversion */ reg |= (WRAP_TO_INCR_SLAVE0 | WRAP_TO_INCR_SLAVE1 | WRAP_TO_INCR_SLAVE2); - write32((void *)TEGRA_MSELECT_CONFIG, reg); + write32p(TEGRA_MSELECT_CONFIG, reg); } /* Tegra-specific entry point, called from assembly in stage_entry.S */ diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c index 636f9b2..c4860f4 100644 --- a/src/soc/qualcomm/common/qupv3_config.c +++ b/src/soc/qualcomm/common/qupv3_config.c @@ -4,6 +4,7 @@ #include <string.h> #include <soc/qupv3_config_common.h> #include <console/console.h> +#include <device/mmio.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> #include <soc/addressmap.h> @@ -215,7 +216,7 @@ for (i = 0; i < gsi_hdr->iep_size_in_items; i++) { /* Check if offset does not exceed GSI address space size */ if (fwIep[i].offset < GSI_REG_BASE_SIZE) - write32((void *)&regs->gsi_cfg + fwIep[i].offset, + write32p(&regs->gsi_cfg + fwIep[i].offset, fwIep[i].value); } diff --git a/src/soc/qualcomm/sc7280/socinfo.c b/src/soc/qualcomm/sc7280/socinfo.c index 8046237..c544464 100644 --- a/src/soc/qualcomm/sc7280/socinfo.c +++ b/src/soc/qualcomm/sc7280/socinfo.c @@ -40,7 +40,7 @@ static uint16_t read_jtagid(void) { - return (read32((void *)(TLMM_TILE_BASE + JTAG_OFFSET)) & DEVICE_ID); + return (read32p((TLMM_TILE_BASE + JTAG_OFFSET)) & DEVICE_ID); } static int match_jtagid(uint16_t jtagid) diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 06c9423..c246853 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -17,7 +17,7 @@ static void set_cpu_id(void) { - cpu_id = read32((void *)EXYNOS5_PRO_ID); + cpu_id = read32p(EXYNOS5_PRO_ID); cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12)); /* diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 7869ab8..bd8e83a 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -18,7 +18,7 @@ static void set_cpu_id(void) { - u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12; + u32 pro_id = (read32p(EXYNOS5_PRO_ID) & 0x00FFF000) >> 12; switch (pro_id) { case 0x200: diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 2d33873..b8e129f 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -33,8 +33,8 @@ #define lread32(a) fradl((void *)(a)) #else -#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) -#define lread32(a) read32((void *)(a)) +#define lwrite32(a,b) write32p((b), (unsigned long)(a)) +#define lread32(a) read32p((a)) #endif static void exynos_dp_enable_video_input(u32 enable) @@ -657,7 +657,7 @@ for (cur_data_idx = 0; cur_data_idx < cur_data_count; cur_data_idx++) { - reg = lread32((void *)((u32)&dp_regs->buf_data0 + + reg = lread32p(((u32)&dp_regs->buf_data0 + 4 * cur_data_idx)); data[start_offset + cur_data_idx] = (unsigned char)reg; } @@ -801,7 +801,7 @@ } for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { - reg = lread32((void *)((u32)&dp_regs->buf_data0 + reg = lread32p(((u32)&dp_regs->buf_data0 + 4 * cur_data_idx)); edid[i + cur_data_idx] = (unsigned char)reg; } diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index bf236d3..4c4f605 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -25,8 +25,8 @@ #define lreadl(a) fradl((void *)(a)) #else -#define lwritel(a,b) write32((void *)(b), (unsigned long)(a)) -#define lreadl(a) read32((void *)(a)) +#define lwritel(a,b) write32p((b), (unsigned long)(a)) +#define lreadl(a) read32p((a)) #endif /* not sure where we want this so ... */ diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 13e9489..f3d9e15 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -262,7 +262,7 @@ * when we want to use SMP inside firmware. */ /* Clear boot reg (hotplug address) in CPU states */ - write32((void *)&exynos_cpu_states->hotplug_address, 0); + write32p(&exynos_cpu_states->hotplug_address, 0); /* set low_power flag and address */ write32(VECTOR_LOW_POWER_ADDRESS, (intptr_t)low_power_start); diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c index 08124d3..7ab5c59 100644 --- a/src/soc/sifive/fu540/clint.c +++ b/src/soc/sifive/fu540/clint.c @@ -14,5 +14,5 @@ void set_msip(int hartid, int val) { - write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val); + write32p((FU540_CLINT + 4 * (uintptr_t)hartid), !!val); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic596fa01c45d2454999b273fcaad11e3e0733f81 Gerrit-Change-Number: 80192 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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