coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/amd: move acpi_add_fsp_tables implementation to common FSP code
by 9elements QA (Code Review) 28 Jan '24

28 Jan '24

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80225?usp=email ) Change subject: soc/amd: move acpi_add_fsp_tables implementation to common FSP code ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/198336 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/198334 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/198333 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/198332 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/198331 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/198330 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/198329 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/198328 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/198327 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/198326 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/198325 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/198324 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/80225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8917a346f586e77b3b3278c73aed8cf61f3c9e6a Gerrit-Change-Number: 80225 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Jan 2024 18:20:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: include/device/device.h: Remove comma from CHIP_NAME() macro
by Felix Singer (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nicholas Sudsgaard, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80228?usp=email ) Change subject: include/device/device.h: Remove comma from CHIP_NAME() macro ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > I agree with removing the macro altogether. Changing the command would be simple as well: […] That issue here annoys me so much, I actually wouldn't care about code alignments 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/80228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Gerrit-Change-Number: 80228 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 28 Jan 2024 14:01:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/*/acpi: drop CRAT TODO
by Felix Held (Code Review) 28 Jan '24

28 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80227?usp=email ) Change subject: soc/amd/*/acpi: drop CRAT TODO ...................................................................... soc/amd/*/acpi: drop CRAT TODO The CRAT (Component Resource Attribute Table) isn't used on the APUs from Renoir on and has also been marked as deprecated in version 6.5 of the ACPI specification. So remove the 'TODO: look into adding CRAT' comment from all SoCs from Renoir/Cezanne on. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80227 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c 4 files changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index c99159a..f60512d 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -58,8 +58,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 8b6031c..eb1d478 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -61,8 +61,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 898e75e..e7f0d96 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -60,8 +60,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index a8be10e..a6482ee 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -61,8 +61,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - /* TODO: look into adding CRAT */ - /* IVRS */ current = acpi_add_ivrs_table(current, rsdp); -- To view, visit https://review.coreboot.org/c/coreboot/+/80227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 Gerrit-Change-Number: 80227 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: include/device/device.h: Remove comma from CHIP_NAME() macro
by Nicholas Sudsgaard (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Felix Singer, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80228?usp=email ) Change subject: include/device/device.h: Remove comma from CHIP_NAME() macro ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > That macro seems to cause just maintenance burden. It doesn't do anything special. […] I agree with removing the macro altogether. Changing the command would be simple as well: `find . \( -type d -name .git -prune \) -o -type f -print0 | xargs -0 sed -ri 's/CHIP_NAME\((.*?)\),*/.name = \1,/'` Me being me, the only thing that would bother me is that it may mess with some code alignments (especially common with structs). -- To view, visit https://review.coreboot.org/c/coreboot/+/80228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Gerrit-Change-Number: 80228 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 28 Jan 2024 12:27:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Jincheng Li (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Martin L Roth, Matt DeVillier, Nico Huber. Jincheng Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78328?usp=email ) Change subject: device/device.h: Drop multiple links ...................................................................... Patch Set 17: Code-Review+1 (1 comment) Patchset: PS10: > > > Per tests on SPR, APIC devices will link under a null attribute bus path_type after adding drop […] It is verified that the patchset 17 fixes the previous issue. Not it could boot centos on spr. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Jan 2024 11:42:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: tree: Use read{64;32;16;8}p and write{64;32;16;8}p
by Elyes Haouas (Code Review) 28 Jan '24

28 Jan '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80192?usp=email ) Change subject: tree: Use read{64;32;16;8}p and write{64;32;16;8}p ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/80192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic596fa01c45d2454999b273fcaad11e3e0733f81 Gerrit-Change-Number: 80192 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: mainboard: Use write{64,32,16,8}p and read{64,32,16,8}p
by Elyes Haouas (Code Review) 28 Jan '24

28 Jan '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80195?usp=email ) Change subject: mainboard: Use write{64,32,16,8}p and read{64,32,16,8}p ...................................................................... mainboard: Use write{64,32,16,8}p and read{64,32,16,8}p Change-Id: I0a4ecd9566e9b715c1209bee26a30f3281548845 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/clint.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/protectli/vault_cml/mainboard.c M src/mainboard/siemens/fa_ehl/romstage_fsp_params.c M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 6 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80195/1 diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 10827fa..3436568 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,5 +14,5 @@ void set_msip(int hartid, int val) { - write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); + write32p((QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); } diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 4d45bce..f510e0b 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -15,5 +15,5 @@ void set_msip(int hartid, int val) { - write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); + write32p((SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); } diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e45ff8f..0dd1360 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -22,7 +22,7 @@ static void configure_sdhci(void) { /* Program eMMC drive strength to 16/10/10 mA */ - write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4); + write32p(SDC1_TLMM_CFG_ADDR, 0x9FE4); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/protectli/vault_cml/mainboard.c b/src/mainboard/protectli/vault_cml/mainboard.c index 1e06fc5..515cb70 100644 --- a/src/mainboard/protectli/vault_cml/mainboard.c +++ b/src/mainboard/protectli/vault_cml/mainboard.c @@ -51,14 +51,14 @@ static bool is_descriptor_writeable(uint8_t *desc) { /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { + if (read32p((desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { printk(BIOS_ERR, "Flash Descriptor is not valid\n"); printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n"); return false; } /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + if (!((read32p((desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); return false; } diff --git a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c index 506bcc6..7337e27 100644 --- a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c @@ -22,7 +22,7 @@ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index d386d75..b74a60e 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -26,7 +26,7 @@ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; -- To view, visit https://review.coreboot.org/c/coreboot/+/80195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a4ecd9566e9b715c1209bee26a30f3281548845 Gerrit-Change-Number: 80195 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
by Elyes Haouas (Code Review) 28 Jan '24

28 Jan '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80194?usp=email ) Change subject: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p ...................................................................... security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p Change-Id: I4bdfcd0cc0e2d9b5f884ea7275659c12488715e0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/intel/txt/romstage.c M src/security/intel/txt/txtlib.c 5 files changed, 57 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/80194/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index b78394a..6fba958 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -100,7 +100,7 @@ void intel_txt_log_spad(void) { - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); printk(BIOS_INFO, "TXT-STS: ACM verification "); @@ -138,8 +138,8 @@ if (!CONFIG(INTEL_TXT)) return false; - ret = (read8((void *)TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || - (read64((void *)TXT_E2STS) & TXT_E2STS_SECRET_STS); + ret = (read8p(TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || + (read64p(TXT_E2STS) & TXT_E2STS_SECRET_STS); if (ret) printk(BIOS_CRIT, "TXT-STS: Secrets in memory!\n"); @@ -154,10 +154,10 @@ * Chapter B.1.7 and B.1.9 * Intel TXT Software Development Guide (Document: 315168-015) */ - uint32_t reg = read32((void *)TXT_VER_FSBIF); + uint32_t reg = read32p(TXT_VER_FSBIF); if (reg == 0 || reg == UINT32_MAX) - reg = read32((void *)TXT_VER_QPIIF); + reg = read32p(TXT_VER_QPIIF); return (reg & TXT_VER_PRODUCTION_FUSED) ? true : false; } @@ -320,11 +320,11 @@ return; /* FIXME: Do we need to program these two? */ - //write32((void *)MCU_BASE_ADDR, 0xffe1a990); - //write32((void *)APINIT_ADDR, 0xfffffff0); + //write32p(MCU_BASE_ADDR, 0xffe1a990); + //write32p(APINIT_ADDR, 0xfffffff0); - write32((void *)BIOACM_ADDR, (uintptr_t)acm_data); - write32((void *)SEMAPHORE, 0); + write32p(BIOACM_ADDR, (uintptr_t)acm_data); + write32p(SEMAPHORE, 0); /* * The time SCLEAN will take depends on the installed RAM size. @@ -364,14 +364,14 @@ cbfs_unmap(acm_data); - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); if (acm_status & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "TEE-TXT: FATAL ACM launch error !\n"); /* * WARNING ! * To clear TXT.BIOSACM.ERRORCODE you must issue a cold reboot! */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); return -1; } @@ -460,7 +460,7 @@ if ((eax & 0x7d) != 0x7d) failure = true; - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) { printk(BIOS_INFO, "TEE-TXT: TXT disabled by BIOS policy in FIT.\n"); diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 6485b86..e1692cf 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -35,7 +35,7 @@ */ static void log_txt_error(const char *phase) { - const uint64_t txt_error = read64((void *)TXT_ERROR); + const uint64_t txt_error = read64p(TXT_ERROR); if (txt_error & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "%s: Error occurred\n", phase); @@ -63,9 +63,9 @@ printk(BIOS_INFO, "TEE-TXT: State of ACM and ucode update:\n"); - bios_acm_error = read32((void *)TXT_BIOSACM_ERRORCODE); - acm_status = read64((void *)TXT_SPAD); - txt_error = read64((void *)TXT_ERROR); + bios_acm_error = read32p(TXT_BIOSACM_ERRORCODE); + acm_status = read64p(TXT_SPAD); + txt_error = read64p(TXT_ERROR); /* Errors by BIOS ACM or FIT */ if ((txt_error & ACMERROR_TXT_VALID) && @@ -81,10 +81,10 @@ } /* Check for fatal ACM error and TXT reset */ - uint8_t error = read8((void *)TXT_ESTS); + uint8_t error = read8p(TXT_ESTS); if (error & TXT_ESTS_TXT_RESET_STS) { printk(BIOS_CRIT, "TXT-STS: Intel TXT reset detected\n"); - intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + intel_txt_log_acm_error(read32p(TXT_ERROR)); } } @@ -178,12 +178,12 @@ { printk(BIOS_INFO, "TEE-TXT: Chipset Key Hash 0x"); for (int i = 0; i < TXT_ACM_KEY_HASH_LEN; i++) { - printk(BIOS_INFO, "%llx", read64((void *)TXT_ACM_KEY_HASH + + printk(BIOS_INFO, "%llx", read64p(TXT_ACM_KEY_HASH + (i * sizeof(uint64_t)))); } printk(BIOS_INFO, "\n"); - printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32((void *)TXT_DIDVID)); + printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32p(TXT_DIDVID)); printk(BIOS_INFO, "TEE-TXT: production fused chipset: %s\n", intel_txt_chipset_is_production_fused() ? "true" : "false"); } @@ -199,18 +199,18 @@ uint64_t reg64; - reg64 = read64((void *)TXT_HEAP_BASE); + reg64 = read64p(TXT_HEAP_BASE); if ((reg64 != 0 && reg64 != ~0UL) && - (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) + (read64p((uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t)); printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx, size %zu MiB\n", tseg_base, tseg_size / MiB); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64((void *)TXT_SINIT_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64((void *)TXT_MSEG_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64((void *)TXT_MSEG_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64p(TXT_HEAP_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64p(TXT_HEAP_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64p(TXT_SINIT_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64p(TXT_SINIT_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64p(TXT_MSEG_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64p(TXT_MSEG_SIZE)); if (bdr) { printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.bios_sinit_size 0x%x\n", diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 8a266a4..5c03da9 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -20,8 +20,8 @@ /* FIXME: Seems to work only on some platforms */ static void log_ibb_measurements(void) { - const uint64_t mseg_size = read64((void *)TXT_MSEG_SIZE); - uint64_t mseg_base = read64((void *)TXT_MSEG_BASE); + const uint64_t mseg_size = read64p(TXT_MSEG_SIZE); + uint64_t mseg_base = read64p(TXT_MSEG_BASE); if (!mseg_size || !mseg_base || mseg_size <= mseg_base) return; @@ -34,14 +34,14 @@ printk(BIOS_INFO, "TEE-TXT: IBB Hash 0x"); for (; mseg_base < mseg_size; mseg_base++) - printk(BIOS_INFO, "%02X", read8((void *)(uintptr_t)mseg_base)); + printk(BIOS_INFO, "%02X", read8p((uintptr_t)mseg_base)); printk(BIOS_INFO, "\n"); } void bootmem_platform_add_ranges(void) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -67,7 +67,7 @@ BM_MEM_RESERVED); const union dpr_register dpr = { - .raw = read32((void *)TXT_DPR), + .raw = read32p(TXT_DPR), }; const uint32_t dpr_base = dpr.top - dpr.size * MiB; @@ -78,13 +78,13 @@ static bool get_wake_error_status(void) { - const uint8_t error = read8((void *)TXT_ESTS); + const uint8_t error = read8p(TXT_ESTS); return !!(error & TXT_ESTS_WAKE_ERROR_STS); } static void check_secrets_txt(void *unused) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -102,7 +102,7 @@ intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); /* Should never reach this point ... */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); die("Waiting for platform reset...\n"); } } @@ -121,7 +121,7 @@ */ static void init_intel_txt(void *unused) { - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -250,10 +250,10 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec); - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, sinit_base, - read64((void *)TXT_SINIT_SIZE)); + read64p(TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -295,9 +295,9 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec); - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); /* Clear SINIT ACM memory */ - memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + memset(sinit_base, 0, read64p(TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -318,7 +318,7 @@ static void txt_initialize_heap(void) { /* Fill TXT.HEAP.BASE with 4 subregions */ - u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); + u8 *heap_struct = (void *)((uintptr_t)read64p(TXT_HEAP_BASE)); /* * Since we may have either BIOS ACM or both BIOS and SINIT ACMs in @@ -365,7 +365,7 @@ if (skip_intel_txt_lockdown()) return; - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); uint32_t txt_feature_flags = 0; uintptr_t tseg_base; @@ -401,7 +401,7 @@ * Chapter 5.5.6.1 DMA Protection Memory Region */ - const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & + const u8 dpr_capable = !!(read64p(TXT_CAPABILITIES) & TXT_CAPABILITIES_DPR); printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); @@ -443,28 +443,28 @@ dpr.prs = 0; dpr.epm = 0; - write64((void *)TXT_DPR, dpr.raw); + write64p(TXT_DPR, dpr.raw); printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", - read32((void *)TXT_DPR)); + read32p(TXT_DPR)); } /* * Document Number: 558294 * Chapter 5.5.6.3 Intel TXT Heap Memory Region */ - write64((void *)TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); - write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); + write64p(TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); + write64p(TXT_HEAP_BASE, + ALIGN_DOWN(tseg_base - read64p(TXT_HEAP_SIZE), 4096)); /* * Document Number: 558294 * Chapter 5.5.6.2 SINIT Memory Region */ - write64((void *)TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); - write64((void *)TXT_SINIT_BASE, - ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - - read64((void *)TXT_SINIT_SIZE), 4096)); + write64p(TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); + write64p(TXT_SINIT_BASE, + ALIGN_DOWN(read64p(TXT_HEAP_BASE) - + read64p(TXT_SINIT_SIZE), 4096)); /* * FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG. @@ -474,8 +474,8 @@ * Chapter 5.10.1 SMM in the Intel TXT for Servers Environment * Disable MSEG. */ - write64((void *)TXT_MSEG_SIZE, 0); - write64((void *)TXT_MSEG_BASE, 0); + write64p(TXT_MSEG_SIZE, 0); + write64p(TXT_MSEG_BASE, 0); /* Only initialize the heap on regular boots */ if (!acpi_is_wakeup_s3()) diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index aa7cc2c..643e7a9 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -63,7 +63,7 @@ return; } - const uint8_t txt_ests = read8((void *)TXT_ESTS); + const uint8_t txt_ests = read8p(TXT_ESTS); const bool establishment = is_establishment_bit_asserted(); const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); diff --git a/src/security/intel/txt/txtlib.c b/src/security/intel/txt/txtlib.c index 5478206..6ce86a3 100644 --- a/src/security/intel/txt/txtlib.c +++ b/src/security/intel/txt/txtlib.c @@ -20,7 +20,7 @@ stopwatch_init_msecs_expire(&timer, 50); while (true) { - access = read8((void *)TPM_ACCESS_REG); + access = read8p(TPM_ACCESS_REG); /* Register returns all ones if TPM is missing */ if (access == 0xff) -- To view, visit https://review.coreboot.org/c/coreboot/+/80194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bdfcd0cc0e2d9b5f884ea7275659c12488715e0 Gerrit-Change-Number: 80194 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
by Elyes Haouas (Code Review) 28 Jan '24

28 Jan '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80193?usp=email ) Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p ...................................................................... soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p Change-Id: I4022e3bbfacf35d0529e46dc82cf303dae9438e4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/meteorlake/crashlog.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 12 files changed, 72 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80193/1 diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 58970e83..ec2a54c 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -204,8 +204,8 @@ community->gpio_to_pad[gpio], gpio); #endif /* Write pad configurations to conf0 and conf1 register */ - write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0); - write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32p((reg + PAD_CONF0_REG), config->pad_conf0); + write32p((reg + PAD_CONF1_REG), config->pad_conf1); } } @@ -215,14 +215,14 @@ #endif /* Wake */ - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); + write32p((community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); /* Wake mask config for communities with 2 regs */ if (community->gpio_count > 32) - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); + write32p((community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); /* Interrupt */ - write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); + write32p((community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); } void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) @@ -233,7 +233,7 @@ * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg * to allow the SW interrupt mask register to be set */ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); + write32p((COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); printk(BIOS_DEBUG, "north\n"); setup_gpios(config->north, &gpnorth_community); diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index d476d5d..15a17b7 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -37,41 +37,41 @@ static void lpc_gpio_config(u32 cycle) { if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_PD20K(1)); } else { /* Resume cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); } } diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 92632d8..d776c6a 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -122,8 +122,8 @@ /* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); } static void lpe_init(struct device *dev) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97c..caa62bc 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -248,7 +248,7 @@ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); /* Use IRQ9 for SCI Interrupt */ - write32((void *)(ilb_base + ACTL), 0); + write32p((ilb_base + ACTL), 0); isa_dma_init(); @@ -256,11 +256,11 @@ /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) - write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); + write8p((pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); /* Set up the per device PIRQ routing base on static config. */ for (i = 0; i < NUM_IR_DEVS; i++) - write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); + write16p((ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..7cabcf64 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -8,6 +8,7 @@ #include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <string.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> @@ -168,7 +169,7 @@ uint64_t vtbar; unsigned long tmp = current; - vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; + vtbar = read64p((DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar); if (!vtbar) return current; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index ea99051..c85a157 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -65,7 +65,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_RXD), reg32); } @@ -77,31 +77,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_TXD), reg32); } // UART0_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_2) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_2 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK), reg32); } // UART0_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_3) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_3 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N), reg32); } @@ -115,7 +115,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_RXD), reg32); } @@ -127,31 +127,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_TXD), reg32); } // UART1_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT), reg32); } // UART1_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT), reg32); } diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 299f950..380e619 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -111,7 +111,7 @@ PadNumber %= 8; Mask = ((1 << 1) | (1 << 0)) << (PadNumber * 4); - PadOwnRegValue = read32((void *)PCH_PCR_ADDRESS( + PadOwnRegValue = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, RegOffset)); *PadOwnVal = (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4)); @@ -379,7 +379,7 @@ // PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; - Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg)); FinalValue = ((Data32 & (~Dw0RegMask)) | Dw0Reg); @@ -408,7 +408,7 @@ ~(uint32_t)Dw0RegMask, (uint32_t)Dw0Reg); } - Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4)); FinalValue = ((Data32 & (~Dw1RegMask)) | Dw1Reg); if (Data32 != FinalValue) { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1e..7eeb3c2 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -320,60 +320,60 @@ config_t *config = config_of(dev); /* Initialize PIRQ Routings */ - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), config->pirqa_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), config->pirqb_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), config->pirqc_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), config->pirqd_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), config->pirqe_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), config->pirqf_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), config->pirqg_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), config->pirqh_routing); /* Initialize device's Interrupt Routings */ - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), config->ir00_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), config->ir01_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), config->ir02_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), config->ir03_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), config->ir04_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), config->ir05_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), config->ir06_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), config->ir07_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), config->ir08_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), config->ir09_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), config->ir10_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), config->ir11_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), config->ir12_routing); /* Initialize device's Interrupt Polarity Control */ - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), config->ipc0); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), config->ipc1); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), config->ipc2); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), config->ipc3); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..20430b8 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -68,7 +68,7 @@ if (silicon_stepping() == SILICON_REV_DENVERTON_B0) { if (!(pci_read_config32(dev, GEN_PMCON_B) & GEN_PMCON_B_RTC_PWR_STS)) { - if (read32((void *)(pwrm_base + 0x124)) + if (read32p((pwrm_base + 0x124)) & ((1 << 11) | (1 << 12))) { /* Performs a global reset */ printk(BIOS_DEBUG, diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 3fb5d75..ee4ef8f 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -39,9 +39,9 @@ printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* Enable AHCI Mode */ - reg32 = read32((void *)(abar + 0x04)); + reg32 = read32p((abar + 0x04)); reg32 |= (1 << 31); - write32((void *)(abar + 0x04), reg32); + write32p((abar + 0x04), reg32); } static void sata_enable(struct device *dev) { /* TODO */ } diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 52d2371..b3159f5 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -5,6 +5,7 @@ #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <delay.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <intelblocks/crashlog.h> #include <intelblocks/pmc_ipc.h> @@ -34,7 +35,7 @@ static u64 get_disc_tab_header(void) { - return read64((void *)disc_tab_addr); + return read64p(disc_tab_addr); } /* Get the SRAM BAR. */ @@ -362,7 +363,7 @@ break; } - cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset)); + cpu_cl_disc_tab.buffers[i].data = read64p((disc_tab_addr + cur_offset)); printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, cpu_cl_disc_tab.buffers[i].fields.offset); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 9d2df2c..0e10ab5 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -32,7 +32,7 @@ { /* PMC controller is hidden - hence PWRMBASE can't be accessbile using PCI cfg space */ uintptr_t pmc_bar = PCH_PWRM_BASE_ADDRESS; - return read32((void *)pmc_bar + PMC_ACPI_CNT); + return read32p(pmc_bar + PMC_ACPI_CNT); } void soc_fill_fadt(acpi_fadt_t *fadt) -- To view, visit https://review.coreboot.org/c/coreboot/+/80193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4022e3bbfacf35d0529e46dc82cf303dae9438e4 Gerrit-Change-Number: 80193 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: include/device/device.h: Remove comma from CHIP_NAME() macro
by Felix Singer (Code Review) 28 Jan '24

28 Jan '24

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nicholas Sudsgaard, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80228?usp=email ) Change subject: include/device/device.h: Remove comma from CHIP_NAME() macro ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: That macro seems to cause just maintenance burden. It doesn't do anything special. I propose that we get rid of the macro instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/80228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6886649760fd719d24d107a737bc6492e3ff994 Gerrit-Change-Number: 80228 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 28 Jan 2024 08:49:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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