coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
by Felix Held (Code Review) 27 Jan '24

27 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80186?usp=email ) Change subject: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1 ...................................................................... mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1 As a result of hardware changes on this board, the PHY previously routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake SoC. This patch changes the device PCI ID in the board's devicetree and accordingly, the GPIO configuration. BUG=none TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE are working, while PSE GbE 1 remains inactive (not listed by 'ip link') . Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c 2 files changed, 38 insertions(+), 38 deletions(-) Approvals: Mario Scheithauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 3f44616..db12aa3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -184,7 +184,7 @@ device pci 1c.4 on end # RP5 device pci 1d.0 off end # Intel PSE IPC (local host to PSE) - device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 # Enable external Marvell PHY 88E1512 chip drivers/net/phy/m88e1512 register "configure_leds" = "true" @@ -195,7 +195,7 @@ # INTn is routed to LED[2] pin register "enable_int" = "true" register "downshift_cnt" = "2" - device mdio 1 on # PHY address + device mdio 0 on # PHY address ops m88e1512_ops end end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c index bd77cdd..cb7b273 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c @@ -20,10 +20,10 @@ PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF2), /* PCHHOT_N */ /* Community 0 - GpioGroup GPP_T */ - PAD_NC(GPP_T4, NONE), /* Not connected */ - PAD_NC(GPP_T5, NONE), /* Not connected */ - PAD_NC(GPP_T6, NONE), /* Not connected */ - PAD_NC(GPP_T7, NONE), /* Not connected */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */ + PAD_CFG_GPO(GPP_T5, 1, DEEP), /* PSE_GBE0_RST_N */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */ @@ -47,10 +47,10 @@ PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */ /* Community 1 - GpioGroup GPP_H */ - PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), /* PSE_GBE1_INT */ - PAD_CFG_GPO(GPP_H1, 1, DEEP), /* PSE_GBE1_RST_N */ - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ + PAD_NC(GPP_H0, NONE), /* Not connected */ + PAD_NC(GPP_H1, NONE), /* Not connected */ + PAD_NC(GPP_H2, NONE), /* Not connected */ + PAD_NC(GPP_H3, NONE), /* Not connected */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* PCIE_CLKREQ4_N */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* PCIE_CLKREQ5_N */ @@ -80,36 +80,36 @@ PAD_NC(GPP_S1, NONE), /* Not connected */ /* Community 3 - GpioGroup GPP_A */ - PAD_NC(GPP_A0, NONE), /* Not connected */ - PAD_NC(GPP_A1, NONE), /* Not connected */ - PAD_NC(GPP_A2, NONE), /* Not connected */ - PAD_NC(GPP_A3, NONE), /* Not connected */ - PAD_NC(GPP_A4, NONE), /* Not connected */ - PAD_NC(GPP_A5, NONE), /* Not connected */ - PAD_NC(GPP_A6, NONE), /* Not connected */ - PAD_NC(GPP_A7, NONE), /* Not connected */ - PAD_NC(GPP_A8, NONE), /* Not connected */ - PAD_NC(GPP_A9, NONE), /* Not connected */ - PAD_NC(GPP_A10, NONE), /* Not connected */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD3 */ - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD2 */ - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD1 */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD0 */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCLK */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCTL */ - PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCLK */ - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCTL */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD3 */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD2 */ - PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD1 */ - PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD0 */ - PAD_NC(GPP_A23, NONE), /* Not connected */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */ + PAD_NC(GPP_A11, NONE), /* Not connected */ + PAD_NC(GPP_A12, NONE), /* Not connected */ + PAD_NC(GPP_A13, NONE), /* Not connected */ + PAD_NC(GPP_A14, NONE), /* Not connected */ + PAD_NC(GPP_A15, NONE), /* Not connected */ + PAD_NC(GPP_A16, NONE), /* Not connected */ + PAD_NC(GPP_A17, NONE), /* Not connected */ + PAD_NC(GPP_A18, NONE), /* Not connected */ + PAD_NC(GPP_A19, NONE), /* Not connected */ + PAD_NC(GPP_A20, NONE), /* Not connected */ + PAD_NC(GPP_A21, NONE), /* Not connected */ + PAD_NC(GPP_A22, NONE), /* Not connected */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */ /* Community 4 - GpioGroup GPP_C */ - PAD_NC(GPP_C3, NONE), /* Not connected */ - PAD_NC(GPP_C4, NONE), /* Not connected */ - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ + PAD_NC(GPP_C6, NONE), /* Not connected */ + PAD_NC(GPP_C7, NONE), /* Not connected */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Gerrit-Change-Number: 80186 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s
by Felix Held (Code Review) 27 Jan '24

27 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80214?usp=email ) Change subject: mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s ...................................................................... mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 s The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. The patch has already been made for mc_ehl3 and serves the purpose of standardization. commit c0221aa980d3 ("mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s") Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Jan Samek: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c index f3c5bd5..0d189a3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c @@ -82,8 +82,8 @@ cfg->t2_delay = 0x01; /* LVDS to backlight active delay: 200 ms */ cfg->t3_timing = 0x04; - /* Minimum re-power delay: 500 ms */ - cfg->t12_timing = 0x0a; + /* Minimum re-power delay: 1 s */ + cfg->t12_timing = 0x14; /* Backlight off to LVDS inactive delay: 200 ms */ cfg->t4_timing = 0x04; /* Enable LVDS to VDD inactive delay. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Gerrit-Change-Number: 80214 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Enable BT audio offload
by Felix Held (Code Review) 27 Jan '24

27 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80001?usp=email ) Change subject: mb/google/nissa/var/anraggar: Enable BT audio offload ...................................................................... mb/google/nissa/var/anraggar: Enable BT audio offload This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:303157827 TEST=Build and boot to anraggar. Verify the config from serial logs. w/o this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 0 [SPEW ] Pin Muxing ``` w/ this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 1 [SPEW ] Pin Muxing ``` Change-Id: I9e6731c8ceaad6ee58b525d4246fa769bfe1b0c7 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80001 Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 21 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 8e0b76b..8bc3f6b 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -69,6 +69,24 @@ PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG), /* R7 : DMIC_DATA_1A ==> NC */ PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index ca9c655..9646f29 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -81,6 +81,9 @@ .configure_ext_fivr = 0, }" + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + # Intel Common SoC Config #+-------------+------------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/80001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e6731c8ceaad6ee58b525d4246fa769bfe1b0c7 Gerrit-Change-Number: 80001 Gerrit-PatchSet: 6 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brya/var/omniknight: Add WIFI SAR table
by Felix Held (Code Review) 27 Jan '24

27 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80152?usp=email ) Change subject: mb/google/brya/var/omniknight: Add WIFI SAR table ...................................................................... mb/google/brya/var/omniknight: Add WIFI SAR table Add WIFI SAR table for omniknight. BUG=b:320172979 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I70e79577612b3d5c4dc0f92211f87cbea0532d5d Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80152 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb M src/mainboard/google/brya/variants/omnigul/variant.c 2 files changed, 11 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 4a3d368..1801672 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -4,6 +4,10 @@ option STORAGE_UFS 1 option STORAGE_NVME 2 end + field WIFI_SAR_TABLE 5 + option OMNIGUL_WIFI_SAR_0 0 + option OMNIKNIGHT_WIFI_SAR_1 1 + end field FINGERPRINT 9 option DISABLE_FP 0 option ENABLE_FP 1 diff --git a/src/mainboard/google/brya/variants/omnigul/variant.c b/src/mainboard/google/brya/variants/omnigul/variant.c index 6a79780..67cef1f 100644 --- a/src/mainboard/google/brya/variants/omnigul/variant.c +++ b/src/mainboard/google/brya/variants/omnigul/variant.c @@ -1,8 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <sar.h> +#include <fw_config.h> const char *get_wifi_sar_cbfs_filename(void) { - return "wifi_sar_0.hex"; + if (fw_config_probe(FW_CONFIG(WIFI_SAR_TABLE, OMNIGUL_WIFI_SAR_0))) + return "wifi_sar_0.hex"; + if (fw_config_probe(FW_CONFIG(WIFI_SAR_TABLE, OMNIKNIGHT_WIFI_SAR_1))) + return "wifi_sar_1.hex"; + + return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/80152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70e79577612b3d5c4dc0f92211f87cbea0532d5d Gerrit-Change-Number: 80152 Gerrit-PatchSet: 11 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: payloads/Kconfig: Add flat binary as payload option
by Maximilian Brune (Code Review) 27 Jan '24

27 Jan '24

Maximilian Brune has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/80191?usp=email ) Change subject: payloads/Kconfig: Add flat binary as payload option ...................................................................... payloads/Kconfig: Add flat binary as payload option This add another choice option for adding a flat binary instead of an ELF or some other payload. It keeps the IS_PAYLOAD_FLAT_BINARY hidden in the menuconfig because it is generally not configurable but dependent on the payload you selected. The patch also guards the PAYLOAD_OPTIONS option since it usually only makes sense to configure it if the payload is a flat binary. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a --- M payloads/Kconfig 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80191/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a Gerrit-Change-Number: 80191 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: payloads/Kconfig: Add flat binary as payload option
by Maximilian Brune (Code Review) 27 Jan '24

27 Jan '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80191?usp=email ) Change subject: payloads/Kconfig: Add flat binary as payload option ...................................................................... payloads/Kconfig: Add flat binary as payload option This add another choice option for adding a flat binary instead of an ELF or some other payload. It keeps the IS_PAYLOAD_FLAT_BINARY hidden in the menuconfig because it is generally not configurable but dependend on the payload you selected. The patch also guards the PAYLOAD_OPTIONS option since it usually only makes sense to configure it if the payload is a flat binary. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a --- M payloads/Kconfig 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80191/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index 9304629..8990aa3 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -38,6 +38,13 @@ You will be able to specify the location and file name of the payload image later. +config PAYLOAD_FLAT_BINARY + bool "Payload is a flat binary" + select PAYLOAD_IS_FLAT_BINARY + help + Add the payload to cbfs as a flat binary type instead of as an + elf payload + source "payloads/external/*/Kconfig.name" endchoice @@ -82,15 +89,13 @@ config PAYLOAD_OPTIONS string "Additional cbfstool options" default "" + depends on PAYLOAD_IS_FLAT_BINARY help Additional cbfstool options for the payload config PAYLOAD_IS_FLAT_BINARY - bool "Payload is a flat binary" + bool default n - help - Add the payload to cbfs as a flat binary type instead of as an - elf payload config PAYLOAD_FIT_SUPPORT bool "FIT support" -- To view, visit https://review.coreboot.org/c/coreboot/+/80191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a Gerrit-Change-Number: 80191 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/ifdtool: Refactor GPR0 Unlock Implemetation
by Subrata Banik (Code Review) 27 Jan '24

27 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80216?usp=email ) Change subject: util/ifdtool: Refactor GPR0 Unlock Implemetation ...................................................................... util/ifdtool: Refactor GPR0 Unlock Implemetation This patch refactors GPR0 unlock function to add few important logic as below 1. Perform GPR0 unlock if GPR0 is locked. 2. While unlocking dump the GPRD PCH strap details 3. Additionally, print the GPR start and end range if GPR0 protection is enabled. TEST=Able to test GPR0 protection on google/rex and google/yahiko. Exp 1: Trying to unlock GPR0 protection for a locked image > ifdtool -p mtl -g image.bin -O image.bin_unlock File image.bin is 33554432 bytes Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff Writing new image to image.bin_unlock Exp 2: Trying to unlock GPR0 protection for a unlocked image > ifdtool -p mtl -g image.bin_unlock -O image.bin_unlock File image.bin_unlock is 33554432 bytes GPR0 protection is already disabled Change-Id: Id35ebdefe83182ad7a3e735bdd2998baa0ec3ed7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80216 Reviewed-by: YH Lin <yueherngl(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M util/ifdtool/ifdtool.c 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: YH Lin: Looks good to me, approved build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 191b321..07cc268 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1577,10 +1577,28 @@ fprintf(stderr, "Disabling GPR0 not supported on this platform\n"); exit(EXIT_FAILURE); } + /* If bit 31 is set then GPR0 protection is enable */ + bool gpr0_status = fpsba->pchstrp[gpr0_offset] & 0x80000000; + if (!gpr0_status) { + printf("GPR0 protection is already disabled\n"); + return; + } + printf("Value at GPRD offset (%d) is 0x%08x\n", gpr0_offset, fpsba->pchstrp[gpr0_offset]); + printf("--------- GPR0 Protected Range --------------\n"); + /* + * Start Address: bit 0-15 of the GPRD represents the protected region start address, + * where bit 0-11 of the start address are assumed to be zero. + */ + printf("Start address = 0x%08x\n", (fpsba->pchstrp[gpr0_offset] & 0xffff) << 12); + /* + * End Address: bit 16-30 of the GPRD represents the protected region end address, + * where bit 0-11 of the end address are assumed to be 0xfff. + */ + printf("End address = 0x%08x\n", + ((fpsba->pchstrp[gpr0_offset] >> 16) & 0x7fff) << 12 | 0xfff); /* 0 means GPR0 protection is disabled */ fpsba->pchstrp[gpr0_offset] = 0; - write_image(filename, image, size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80216?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id35ebdefe83182ad7a3e735bdd2998baa0ec3ed7 Gerrit-Change-Number: 80216 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/rex: Organize models configs alphabetically
by Subrata Banik (Code Review) 27 Jan '24

27 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80206?usp=email ) Change subject: mb/google/rex: Organize models configs alphabetically ...................................................................... mb/google/rex: Organize models configs alphabetically This patch ensures the baseboard and variant configs (inside Kconfig and Kconfig.name) are organized in alphabetic order. TEST=execute make menuconfig and verify the google/rex variants order are alphabetically correct. Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80206 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Jakub Czapiga <czapiga(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name 2 files changed, 60 insertions(+), 60 deletions(-) Approvals: Nick Vaccaro: Looks good to me, approved Jakub Czapiga: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index a253c8c..046f1d9 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -30,6 +30,22 @@ select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 select SOC_INTEL_CSE_SEND_EOP_ASYNC +config BOARD_GOOGLE_BASEBOARD_OVIS + def_bool n + select BOARD_GOOGLE_REX_COMMON + select DRIVERS_INTEL_PMC + select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP + select HAVE_SLP_S0_GATE + select MAINBOARD_HAS_CHROMEOS + select MEMORY_SOLDERDOWN + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SOC_INTEL_IOE_DIE_SUPPORT + select SOC_INTEL_METEORLAKE_U_H + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select TPM_GOOGLE_TI50 + config BOARD_GOOGLE_BASEBOARD_REX def_bool n select BOARD_GOOGLE_REX_COMMON @@ -47,6 +63,19 @@ select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 +config BOARD_GOOGLE_MODEL_DEKU + def_bool n + select BOARD_GOOGLE_BASEBOARD_OVIS + +config BOARD_GOOGLE_MODEL_KARIS + def_bool n + select BOARD_GOOGLE_BASEBOARD_REX + select CHROMEOS_WIFI_SAR if CHROMEOS + +config BOARD_GOOGLE_MODEL_OVIS + def_bool n + select BOARD_GOOGLE_BASEBOARD_OVIS + config BOARD_GOOGLE_MODEL_REX def_bool n select BOARD_GOOGLE_BASEBOARD_REX @@ -70,44 +99,11 @@ select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENESYSLOGIC_GL9750 -config BOARD_GOOGLE_MODEL_KARIS - def_bool n - select BOARD_GOOGLE_BASEBOARD_REX - select CHROMEOS_WIFI_SAR if CHROMEOS +config BOARD_GOOGLE_DEKU + select BOARD_GOOGLE_MODEL_DEKU -config BOARD_GOOGLE_BASEBOARD_OVIS - def_bool n - select BOARD_GOOGLE_REX_COMMON - select DRIVERS_INTEL_PMC - select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP - select HAVE_SLP_S0_GATE - select MAINBOARD_HAS_CHROMEOS - select MEMORY_SOLDERDOWN - select RT8168_GEN_ACPI_POWER_RESOURCE - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE - select SOC_INTEL_IOE_DIE_SUPPORT - select SOC_INTEL_METEORLAKE_U_H - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - select TPM_GOOGLE_TI50 - -config BOARD_GOOGLE_MODEL_OVIS - def_bool n - select BOARD_GOOGLE_BASEBOARD_OVIS - -config BOARD_GOOGLE_MODEL_DEKU - def_bool n - select BOARD_GOOGLE_BASEBOARD_OVIS - -config BOARD_GOOGLE_REX0 - select BOARD_GOOGLE_MODEL_REX - -config BOARD_GOOGLE_SCREEBO - select BOARD_GOOGLE_MODEL_SCREEBO - -config BOARD_GOOGLE_SCREEBO4ES - select BOARD_GOOGLE_MODEL_SCREEBO - select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON +config BOARD_GOOGLE_DEKU4ES + select BOARD_GOOGLE_MODEL_DEKU config BOARD_GOOGLE_KARIS select BOARD_GOOGLE_MODEL_KARIS @@ -116,22 +112,19 @@ select BOARD_GOOGLE_MODEL_KARIS select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON -config BOARD_GOOGLE_REX_EC_ISH - select BOARD_GOOGLE_MODEL_REX_EC_ISH - config BOARD_GOOGLE_OVIS select BOARD_GOOGLE_MODEL_OVIS -config BOARD_GOOGLE_DEKU - select BOARD_GOOGLE_MODEL_DEKU - -config BOARD_GOOGLE_DEKU4ES - select BOARD_GOOGLE_MODEL_DEKU - config BOARD_GOOGLE_OVIS4ES select BOARD_GOOGLE_MODEL_OVIS select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON +config BOARD_GOOGLE_REX0 + select BOARD_GOOGLE_MODEL_REX + +config BOARD_GOOGLE_REX_EC_ISH + select BOARD_GOOGLE_MODEL_REX_EC_ISH + config BOARD_GOOGLE_REX4ES select BOARD_GOOGLE_MODEL_REX select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON @@ -140,6 +133,13 @@ select BOARD_GOOGLE_MODEL_REX_EC_ISH select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON +config BOARD_GOOGLE_SCREEBO + select BOARD_GOOGLE_MODEL_SCREEBO + +config BOARD_GOOGLE_SCREEBO4ES + select BOARD_GOOGLE_MODEL_SCREEBO + select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON + if BOARD_GOOGLE_REX_COMMON config BASEBOARD_DIR diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 7717458..7a17f87 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -1,13 +1,10 @@ comment "Rex" -config BOARD_GOOGLE_REX0 - bool "-> Rex 0" +config BOARD_GOOGLE_DEKU + bool "-> Deku" -config BOARD_GOOGLE_SCREEBO - bool "-> Screebo" - -config BOARD_GOOGLE_SCREEBO4ES - bool "-> Screebo4ES" +config BOARD_GOOGLE_DEKU4ES + bool "-> Deku4ES" config BOARD_GOOGLE_KARIS bool "-> Karis" @@ -15,23 +12,26 @@ config BOARD_GOOGLE_KARIS4ES bool "-> Karis4ES" -config BOARD_GOOGLE_REX_EC_ISH - bool "-> Rex EC ISH" - config BOARD_GOOGLE_OVIS bool "-> Ovis" config BOARD_GOOGLE_OVIS4ES bool "-> Ovis4ES" -config BOARD_GOOGLE_DEKU - bool "-> Deku" +config BOARD_GOOGLE_REX0 + bool "-> Rex 0" -config BOARD_GOOGLE_DEKU4ES - bool "-> Deku4ES" +config BOARD_GOOGLE_REX_EC_ISH + bool "-> Rex EC ISH" config BOARD_GOOGLE_REX4ES bool "-> Rex4ES" config BOARD_GOOGLE_REX4ES_EC_ISH bool "-> Rex4ES EC ISH" + +config BOARD_GOOGLE_SCREEBO + bool "-> Screebo" + +config BOARD_GOOGLE_SCREEBO4ES + bool "-> Screebo4ES" -- To view, visit https://review.coreboot.org/c/coreboot/+/80206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Gerrit-Change-Number: 80206 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by David Ruth (Code Review) 27 Jan '24

27 Jan '24

Attention is currently required from: Arthur Heymans, Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Paul Menzel, Subrata Banik, Subrata Banik, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80170?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Add MTCL function to ACPI SSDT tables The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Adds the mtcl.c file to abstract functionality related to reading the binary file that defines the MTCL, and verifying that the format is one intended to be handled by this implementation. * Reads a binary file called "wifi_mtcl.hex" in cbfs * Verifies that the format matches a supported value * Writes the verified content as appropriate AML. * Adds config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Adds config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Adds config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.hex" * Adds functionality to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for WiFi devices when the above flags are enabled BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.hex blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth(a)chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 --- M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.mk M src/drivers/wifi/generic/acpi.c A src/drivers/wifi/generic/mtcl.c M src/include/device/pci_ids.h A src/include/mtcl.h 6 files changed, 219 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 12 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by David Ruth (Code Review) 27 Jan '24

27 Jan '24

Attention is currently required from: Arthur Heymans, Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Paul Menzel, Subrata Banik, Subrata Banik, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80170?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Add MTCL function to ACPI SSDT tables The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Adds the mtcl.c file to abstract functionality related to reading the binary file that defines the MTCL, and verifying that the format is one intended to be handled by this implementation. * Reads a binary file called "wifi_mtcl.hex" in cbfs * Verifies that the format matches a supported value * Writes the verified content as appropriate AML. * Adds config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Adds config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Adds config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.hex" * Adds functionality to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for WiFi devices when the above flags are enabled BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.hex blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth(a)chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 --- M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.mk M src/drivers/wifi/generic/acpi.c A src/drivers/wifi/generic/mtcl.c M src/include/device/pci_ids.h A src/include/mtcl.h 6 files changed, 219 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 11 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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