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Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
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Change subject: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
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Change subject: malloc/memalign: Return NULL if the request is too large
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Change subject: util/ifdtool: Refactor GPR0 Unlock Implemetation
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Are you saying something in the PSR flow changes the descriptor during factory? Is there a bug with details about this?
you can find some details here https://docs.google.com/document/d/1EdLhzZ-hg0gCrb75cpBzT7e7woYcFFdcLI0ofDd…
>
> The final SI_DESC at the end of the factory flow needs to match the image in the updater, otherwise AP RO verification will fail, so I don't think that will work.
exactly. that was my understanding too. for now, I'm planning to update the descriptor with genesis information directly w/o running into AP RO verification issue.
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Change subject: util/ifdtool: Refactor GPR0 Unlock Implemetation
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Patch Set 2:
(1 comment)
Patchset:
PS2:
> > Just checking, is this purely informational or is something in the factory flow going to rely on t […]
Are you saying something in the PSR flow changes the descriptor during factory? Is there a bug with details about this?
The final SI_DESC at the end of the factory flow needs to match the image in the updater, otherwise AP RO verification will fail, so I don't think that will work.
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Change subject: util/ifdtool: Refactor GPR0 Unlock Implemetation
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Just checking, is this purely informational or is something in the factory flow going to rely on this logging?
at this moment just information @Reka. but I'm planning to craete `lock gpr0` cmdline which can take the input from "Value at GPRD offset (64) is 0x83220004" to override the GPRD w/o need to reflash the SI_DESC (which might override some other fields of the SI_DESC region like genesis information)
WDYT?
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Change subject: malloc/memalign: Return NULL if the request is too large
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Patch Set 2: Code-Review+2
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Hello Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified-1 by build bot (Jenkins)
Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB
......................................................................
cpu/x86: Add 1GiB pages for memory access up to 512GiB
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGETABLES in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/cpu/x86/64bit/Makefile.mk
A src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/Kconfig
3 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80088/5
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Hello Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80088?usp=email
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB
......................................................................
cpu/x86: Add 1GiB pages for memory access up to 512GiB
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGETABLES in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/cpu/x86/64bit/Makefile.mk
A src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/Kconfig
3 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80088/4
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