coreboot-gerrit January 2024

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[M] Change in coreboot[main]: mb/google/puff: Baseboard devicetree clean up #1
by Felix Singer (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80141?usp=email ) Change subject: mb/google/puff: Baseboard devicetree clean up #1 ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/puff/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80141/comment/01c1877f_29b8b266 : PS1, Line 321: device ref p2sb on end AFAIK P2SB is hidden by the FSP, that's why we set it in chipset.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/80141?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a515f13df1252ed2b769a535da22a523c95c359 Gerrit-Change-Number: 80141 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Jan 2024 15:14:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini
by Felix Singer (Code Review) 26 Jan '24

26 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80182?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini ...................................................................... mb/purism/librem_cnl: Set edk2 boot timeout for Librem Mini As with other devices with only an external display, the Librem mini/ mini-v2 need a few extra seconds (vs an internal panel) for display init in order for the edk2 boot splash to be visible before the default boot target is booted. TEST=build/boot Librem Mini v2 w/edk2 payload, verify splash screen shown / user has time to enter setup menu. Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80182 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Jonathon Hall: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index f75f316..1628ec6 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -112,3 +112,7 @@ U81 on the bottom of the board near the front edge; the IC is not populated. TX is pin 14, RX is pin 19. The signals are 3.3V (do NOT connect directly to an RS-232 serial port). + +config EDK2_BOOT_TIMEOUT + int + default 4 if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Gerrit-Change-Number: 80182 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Nico Huber (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78328?usp=email ) Change subject: device/device.h: Drop multiple links ...................................................................... Patch Set 16: Code-Review+1 (2 comments) Patchset: PS16: Read through the whole patch again and only spotted one thing where I believe you removed too much of a comment. File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/78328/comment/22a86fd5_a00bb6f7 : PS16, Line 1734: * +-----------------------------------------------------------------+ We still do this, only for a single bus, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Jan 2024 15:08:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd: use expected function signature for soc_acpi_write_tables
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80218?usp=email to look at the new patch set (#2). Change subject: soc/amd: use expected function signature for soc_acpi_write_tables ...................................................................... soc/amd: use expected function signature for soc_acpi_write_tables A pointer to soc_acpi_write_tables gets assigned to the write_acpi_tables element of the device_operations struct, so make sure that the function has the expected function signature which in this case means using unsigned long as type for both the 'current' parameter and the return value. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iee45badb904fa20c6db146edbc00c40ca09361d1 --- M src/soc/amd/cezanne/agesa_acpi.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/glinda/agesa_acpi.c M src/soc/amd/glinda/include/soc/acpi.h M src/soc/amd/mendocino/agesa_acpi.c M src/soc/amd/mendocino/include/soc/acpi.h M src/soc/amd/phoenix/agesa_acpi.c M src/soc/amd/phoenix/include/soc/acpi.h M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/include/soc/acpi.h 10 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/80218/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee45badb904fa20c6db146edbc00c40ca09361d1 Gerrit-Change-Number: 80218 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tables
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80217?usp=email to look at the new patch set (#2). Change subject: soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tables ...................................................................... soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tables It's not the AGESA code that generates most of the ACPI tables, so rename the function. This also aligns the other SoCs more with Genoa. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827 --- M src/soc/amd/cezanne/agesa_acpi.c M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/glinda/agesa_acpi.c M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/include/soc/acpi.h M src/soc/amd/mendocino/agesa_acpi.c M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/include/soc/acpi.h M src/soc/amd/phoenix/agesa_acpi.c M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/include/soc/acpi.h M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/northbridge.c 16 files changed, 29 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/80217/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827 Gerrit-Change-Number: 80217 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd: move acpi_add_fsp_tables implementation to common FSP code
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

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[M] Change in coreboot[main]: soc/amd: factor out acpi_add_fsp_tables
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

1 0

[XL] Change in coreboot[main]: soc/amd/picasso: factor out CRAT table generation
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80223?usp=email ) Change subject: soc/amd/picasso: factor out CRAT table generation ...................................................................... soc/amd/picasso: factor out CRAT table generation Factor out the code to add the CRAT ACPI table into a separate file and add the acpi_add_crat_table function that can then be called from soc_acpi_write_tables to better isolate all code specific to the CRAT table. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4a7853748512811d3d4e124224fcd459e527522c --- M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/picasso/Makefile.mk A src/soc/amd/picasso/acpi_crat.c M src/soc/amd/picasso/agesa_acpi.c 4 files changed, 558 insertions(+), 540 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/80223/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 8642d0f..2a47c0e 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -62,6 +62,8 @@ unsigned long current); void acpi_log_events(const struct chipset_power_state *ps); + +unsigned long acpi_add_crat_table(unsigned long current, acpi_rsdp_t *rsdp); unsigned long acpi_add_ivrs_table(unsigned long current, acpi_rsdp_t *rsdp); #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk index ba58c91..fe65772 100644 --- a/src/soc/amd/picasso/Makefile.mk +++ b/src/soc/amd/picasso/Makefile.mk @@ -19,6 +19,7 @@ romstage-y += fsp_m_params.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_crat.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c diff --git a/src/soc/amd/picasso/acpi_crat.c b/src/soc/amd/picasso/acpi_crat.c new file mode 100644 index 0000000..e528515 --- /dev/null +++ b/src/soc/amd/picasso/acpi_crat.c @@ -0,0 +1,553 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_crat.h> +#include <acpi/acpi_ivrs.h> +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <amdblocks/cpu.h> +#include <amdblocks/data_fabric.h> +#include <amdblocks/ioapic.h> +#include <cpu/amd/cpuid.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <FspGuids.h> +#include <soc/data_fabric.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static unsigned long gen_crat_hsa_entry(struct acpi_crat_header *crat, unsigned long current) +{ + struct crat_hsa_processing_unit *hsa_entry = (struct crat_hsa_processing_unit *)current; + memset(hsa_entry, 0, sizeof(struct crat_hsa_processing_unit)); + + hsa_entry->flags = CRAT_HSA_PR_FLAG_EN | CRAT_HSA_PR_FLAG_CPU_PRES; + hsa_entry->wave_front_size = 4; + hsa_entry->num_cpu_cores = get_cpu_count(); + hsa_entry->length = sizeof(struct crat_hsa_processing_unit); + crat->total_entries++; + + current += hsa_entry->length; + return current; +} + +static unsigned long create_crat_memory_entry(uint32_t domain, uint64_t region_base, + uint64_t region_size, unsigned long current) +{ + struct crat_memory *mem_affinity = (struct crat_memory *)current; + memset(mem_affinity, 0, sizeof(struct crat_memory)); + + mem_affinity->type = CRAT_MEMORY_TYPE; + mem_affinity->length = sizeof(struct crat_memory); + mem_affinity->proximity_domain = 0; + mem_affinity->base_address_low = region_base & 0xffffffff; + mem_affinity->base_address_high = (region_base >> 32) & 0xffffffff; + mem_affinity->length_low = region_size & 0xffffffff; + mem_affinity->length_high = (region_size >> 32) & 0xffffffff; + mem_affinity->flags = CRAT_MEM_FLAG_EN; + mem_affinity->width = 64; + + current += mem_affinity->length; + return current; +} + +static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, + unsigned long current) +{ + uint32_t dram_base_reg, dram_limit_reg, dram_hole_ctl; + uint64_t memory_length, memory_base, hole_base, size_below_hole; + size_t new_entries = 0; + + for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG; + dram_map_idx++) { + dram_base_reg = + data_fabric_read32(DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); + + if (dram_base_reg & DRAM_BASE_REG_VALID) { + dram_limit_reg = data_fabric_read32(DF_DRAM_LIMIT(dram_map_idx), + IOMS0_FABRIC_ID); + memory_length = + ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 + - ((dram_base_reg & DRAM_BASE_ADDR) >> DRAM_BASE_ADDR_SHFT); + memory_length = memory_length << 28; + memory_base = (uint64_t)(dram_base_reg & DRAM_BASE_ADDR) + << (28 - DRAM_BASE_ADDR_SHFT); + + if (memory_base == 0) { + current = + create_crat_memory_entry(0, 0ull, 0xa0000ull, current); + memory_base = 1 * MiB; + memory_length = memory_base; + new_entries++; + } + + if (dram_base_reg & DRAM_BASE_HOLE_EN) { + dram_hole_ctl = data_fabric_read32(DF_DRAM_HOLE_CTL, + IOMS0_FABRIC_ID); + hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); + size_below_hole = hole_base - memory_base; + current = create_crat_memory_entry(0, memory_base, + size_below_hole, current); + memory_length = (uint64_t)(((dram_limit_reg & DRAM_LIMIT_ADDR) + >> DRAM_LIMIT_ADDR_SHFT) + + 1 - 0x10) + << 28; + memory_base = 0x100000000; + new_entries++; + } + + current = create_crat_memory_entry(0, memory_base, memory_length, + current); + new_entries++; + } + } + crat->total_entries += new_entries; + return current; +} + +static unsigned long add_crat_cache_entry(struct crat_cache **cache_affinity, + unsigned long current) +{ + *cache_affinity = (struct crat_cache *)current; + memset(*cache_affinity, 0, sizeof(struct crat_cache)); + + (*cache_affinity)->type = CRAT_CACHE_TYPE; + (*cache_affinity)->length = sizeof(struct crat_cache); + (*cache_affinity)->flags = CRAT_CACHE_FLAG_EN | CRAT_CACHE_FLAG_CPU_CACHE; + + current += sizeof(struct crat_cache); + return current; +} + +static uint8_t get_associativity(uint32_t encoded_associativity) +{ + uint8_t associativity = 0; + + switch (encoded_associativity) { + case 0: + case 1: + case 2: + case 3: + case 4: + return encoded_associativity; + case 5: + associativity = 6; + break; + case 6: + associativity = 8; + break; + case 8: + associativity = 16; + break; + case 0xA: + associativity = 32; + break; + case 0xB: + associativity = 48; + break; + case 0xC: + associativity = 64; + break; + case 0xD: + associativity = 96; + break; + case 0xE: + associativity = 128; + break; + case 0xF: + associativity = 0xFF; + break; + default: + return 0; + } + + return associativity; +} + +static unsigned long gen_crat_cache_entry(struct acpi_crat_header *crat, unsigned long current) +{ + size_t total_num_threads, num_threads_sharing0, num_threads_sharing1, + num_threads_sharing2, num_threads_sharing3, thread, new_entries; + struct cpuid_result cache_props0, cache_props1, cache_props2, cache_props3; + uint8_t sibling_mask = 0; + uint32_t l1_data_cache_ids, l1_inst_cache_ids, l2_cache_ids, l3_cache_ids; + struct crat_cache *cache_affinity = NULL; + + total_num_threads = get_cpu_count(); + + cache_props0 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_0); + cache_props1 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_1); + cache_props2 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_2); + cache_props3 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_3); + + l1_data_cache_ids = cpuid_ecx(CPUID_L1_TLB_CACHE_IDS); + l1_inst_cache_ids = cpuid_edx(CPUID_L1_TLB_CACHE_IDS); + l2_cache_ids = cpuid_ecx(CPUID_L2_L3_CACHE_L2_TLB_IDS); + l3_cache_ids = cpuid_edx(CPUID_L2_L3_CACHE_L2_TLB_IDS); + + num_threads_sharing0 = + ((cache_props0.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing1 = + ((cache_props1.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing2 = + ((cache_props2.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing3 = + ((cache_props3.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + + new_entries = 0; + for (thread = 0; thread < total_num_threads; thread++) { + /* L1 data cache */ + if (thread % num_threads_sharing0 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= CRAT_CACHE_FLAG_DATA_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing0; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props0.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + (l1_data_cache_ids & L1_DC_SIZE_MASK) >> L1_DC_SIZE_SHFT; + cache_affinity->cache_level = CRAT_L1_CACHE; + cache_affinity->lines_per_tag = + (l1_data_cache_ids & L1_DC_LINE_TAG_MASK) + >> L1_DC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l1_data_cache_ids & L1_DC_LINE_SIZE_MASK) + >> L1_DC_LINE_SIZE_SHFT; + cache_affinity->associativity = + (l1_data_cache_ids & L1_DC_ASSOC_MASK) >> L1_DC_ASSOC_SHFT; + cache_affinity->cache_latency = 1; + } + + /* L1 instruction cache */ + if (thread % num_threads_sharing1 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= CRAT_CACHE_FLAG_INSTR_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing1; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props1.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + (l1_inst_cache_ids & L1_IC_SIZE_MASK) >> L1_IC_SIZE_SHFT; + cache_affinity->cache_level = CRAT_L1_CACHE; + cache_affinity->lines_per_tag = + (l1_inst_cache_ids & L1_IC_LINE_TAG_MASK) + >> L1_IC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l1_inst_cache_ids & L1_IC_LINE_SIZE_MASK) + >> L1_IC_LINE_SIZE_SHFT; + cache_affinity->associativity = + (l1_inst_cache_ids & L1_IC_ASSOC_MASK) >> L1_IC_ASSOC_SHFT; + cache_affinity->cache_latency = 1; + } + + /* L2 cache */ + if (thread % num_threads_sharing2 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= + CRAT_CACHE_FLAG_DATA_CACHE | CRAT_CACHE_FLAG_INSTR_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props2.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + (l2_cache_ids & L2_DC_SIZE_MASK) >> L2_DC_SIZE_SHFT; + cache_affinity->cache_level = CRAT_L2_CACHE; + cache_affinity->lines_per_tag = + (l2_cache_ids & L2_DC_LINE_TAG_MASK) >> L2_DC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l2_cache_ids & L2_DC_LINE_SIZE_MASK) >> L2_DC_LINE_SIZE_SHFT; + cache_affinity->associativity = get_associativity( + (l2_cache_ids & L2_DC_ASSOC_MASK) >> L2_DC_ASSOC_SHFT); + cache_affinity->cache_latency = 1; + } + + /* L3 cache */ + if (thread % num_threads_sharing3 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= + CRAT_CACHE_FLAG_DATA_CACHE | CRAT_CACHE_FLAG_INSTR_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing3; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props0.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + ((l3_cache_ids & L3_DC_SIZE_MASK) >> L3_DC_SIZE_SHFT) * 512; + cache_affinity->cache_level = CRAT_L3_CACHE; + cache_affinity->lines_per_tag = + (l3_cache_ids & L3_DC_LINE_TAG_MASK) >> L3_DC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l3_cache_ids & L3_DC_LINE_SIZE_MASK) >> L3_DC_LINE_SIZE_SHFT; + cache_affinity->associativity = get_associativity( + (l3_cache_ids & L3_DC_ASSOC_MASK) >> L3_DC_ASSOC_SHFT); + cache_affinity->cache_latency = 1; + } + } + crat->total_entries += new_entries; + return current; +} + +static uint8_t get_tlb_size(enum tlb_type type, struct crat_tlb *crat_tlb_entry, + uint16_t raw_assoc_size) +{ + uint8_t tlbsize; + + if (raw_assoc_size >= 256) { + tlbsize = (uint8_t)(raw_assoc_size / 256); + + if (type == tlb_2m) + crat_tlb_entry->flags |= CRAT_TLB_FLAG_2MB_BASE_256; + else if (type == tlb_4k) + crat_tlb_entry->flags |= CRAT_TLB_FLAG_4K_BASE_256; + else if (type == tlb_1g) + crat_tlb_entry->flags |= CRAT_TLB_FLAG_1GB_BASE_256; + } else { + tlbsize = (uint8_t)(raw_assoc_size); + } + return tlbsize; +} + +static unsigned long add_crat_tlb_entry(struct crat_tlb **tlb_affinity, unsigned long current) +{ + *tlb_affinity = (struct crat_tlb *)current; + memset(*tlb_affinity, 0, sizeof(struct crat_tlb)); + + (*tlb_affinity)->type = CRAT_TLB_TYPE; + (*tlb_affinity)->length = sizeof(struct crat_tlb); + (*tlb_affinity)->flags = CRAT_TLB_FLAG_EN | CRAT_TLB_FLAG_CPU_TLB; + + current += sizeof(struct crat_tlb); + return current; +} + +static unsigned long gen_crat_tlb_entry(struct acpi_crat_header *crat, unsigned long current) +{ + size_t total_num_threads, num_threads_sharing0, num_threads_sharing1, + num_threads_sharing2, thread, new_entries; + struct cpuid_result cache_props0, cache_props1, cache_props2; + uint8_t sibling_mask = 0; + uint32_t l1_tlb_2M4M_ids, l1_tlb_4K_ids, l2_tlb_2M4M_ids, l2_tlb_4K_ids, l1_tlb_1G_ids, + l2_tlb_1G_ids; + struct crat_tlb *tlb_affinity = NULL; + + total_num_threads = get_cpu_count(); + cache_props0 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_0); + cache_props1 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_1); + cache_props2 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_2); + + l1_tlb_2M4M_ids = cpuid_eax(CPUID_L1_TLB_CACHE_IDS); + l2_tlb_2M4M_ids = cpuid_eax(CPUID_L2_L3_CACHE_L2_TLB_IDS); + l1_tlb_4K_ids = cpuid_ebx(CPUID_L1_TLB_CACHE_IDS); + l2_tlb_4K_ids = cpuid_ebx(CPUID_L2_L3_CACHE_L2_TLB_IDS); + l1_tlb_1G_ids = cpuid_eax(CPUID_TLB_L1L2_1G_IDS); + l2_tlb_1G_ids = cpuid_ebx(CPUID_TLB_L1L2_1G_IDS); + + num_threads_sharing0 = + ((cache_props0.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing1 = + ((cache_props1.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing2 = + ((cache_props2.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + + new_entries = 0; + for (thread = 0; thread < total_num_threads; thread++) { + + /* L1 data TLB */ + if (thread % num_threads_sharing0 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_DATA_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing0; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L1_CACHE; + + tlb_affinity->data_tlb_2mb_assoc = + (l1_tlb_2M4M_ids & L1_DAT_TLB_2M4M_ASSOC_MASK) + >> L1_DAT_TLB_2M4M_ASSOC_SHFT; + tlb_affinity->data_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l1_tlb_2M4M_ids & L1_DAT_TLB_2M4M_SIZE_MASK) + >> L1_DAT_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->data_tlb_4k_assoc = + (l1_tlb_4K_ids & L1_DAT_TLB_4K_ASSOC_MASK) + >> L1_DAT_TLB_4K_ASSOC_SHFT; + tlb_affinity->data_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l1_tlb_4K_ids & L1_DAT_TLB_4K_SIZE_MASK) + >> L1_DAT_TLB_4K_SIZE_SHFT); + + tlb_affinity->data_tlb_1g_assoc = + (l1_tlb_1G_ids & L1_DAT_TLB_1G_ASSOC_MASK) + >> L1_DAT_TLB_1G_ASSOC_SHFT; + tlb_affinity->data_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l1_tlb_1G_ids & L1_DAT_TLB_1G_SIZE_MASK) + >> L1_DAT_TLB_1G_SIZE_SHFT); + } + + /* L1 instruction TLB */ + if (thread % num_threads_sharing1 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_INSTR_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing1; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L1_CACHE; + tlb_affinity->instr_tlb_2mb_assoc = + (l1_tlb_2M4M_ids & L1_INST_TLB_2M4M_ASSOC_MASK) + >> L1_INST_TLB_2M4M_ASSOC_SHFT; + tlb_affinity->instr_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l1_tlb_2M4M_ids & L1_INST_TLB_2M4M_SIZE_MASK) + >> L1_INST_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->instr_tlb_4k_assoc = + (l1_tlb_4K_ids & L1_INST_TLB_4K_ASSOC_MASK) + >> L1_INST_TLB_4K_ASSOC_SHFT; + tlb_affinity->instr_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l1_tlb_4K_ids & L1_INST_TLB_4K_SIZE_MASK) + >> L1_INST_TLB_4K_SIZE_SHFT); + + tlb_affinity->instr_tlb_1g_assoc = + (l1_tlb_1G_ids & L1_INST_TLB_1G_ASSOC_MASK) + >> L1_INST_TLB_1G_ASSOC_SHFT; + tlb_affinity->instr_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l1_tlb_1G_ids & L1_INST_TLB_1G_SIZE_MASK) + >> L1_INST_TLB_1G_SIZE_SHFT); + } + + /* L2 Data TLB */ + if (thread % num_threads_sharing2 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_DATA_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L2_CACHE; + tlb_affinity->data_tlb_2mb_assoc = + (l2_tlb_2M4M_ids & L2_DAT_TLB_2M4M_ASSOC_MASK) + >> L2_DAT_TLB_2M4M_ASSOC_SHFT; + tlb_affinity->data_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l2_tlb_2M4M_ids & L2_DAT_TLB_2M4M_SIZE_MASK) + >> L2_DAT_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->data_tlb_4k_assoc = + get_associativity((l2_tlb_4K_ids & L2_DAT_TLB_2M4M_ASSOC_MASK) + >> L2_DAT_TLB_4K_ASSOC_SHFT); + tlb_affinity->data_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l2_tlb_2M4M_ids & L2_DAT_TLB_4K_SIZE_MASK) + >> L2_DAT_TLB_4K_SIZE_SHFT); + + tlb_affinity->data_tlb_1g_assoc = + get_associativity((l2_tlb_1G_ids & L2_DAT_TLB_1G_ASSOC_MASK) + >> L2_DAT_TLB_1G_ASSOC_SHFT); + tlb_affinity->data_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l2_tlb_1G_ids & L2_DAT_TLB_1G_SIZE_MASK) + >> L2_DAT_TLB_1G_SIZE_SHFT); + } + + /* L2 Instruction TLB */ + if (thread % num_threads_sharing2 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_INSTR_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L2_CACHE; + tlb_affinity->instr_tlb_2mb_assoc = get_associativity( + (l2_tlb_2M4M_ids & L2_INST_TLB_2M4M_ASSOC_MASK) + >> L2_INST_TLB_2M4M_ASSOC_SHFT); + tlb_affinity->instr_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l2_tlb_2M4M_ids & L2_INST_TLB_2M4M_SIZE_MASK) + >> L2_INST_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->instr_tlb_4k_assoc = + get_associativity((l2_tlb_4K_ids & L2_INST_TLB_4K_ASSOC_MASK) + >> L2_INST_TLB_4K_ASSOC_SHFT); + tlb_affinity->instr_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l2_tlb_4K_ids & L2_INST_TLB_4K_SIZE_MASK) + >> L2_INST_TLB_4K_SIZE_SHFT); + + tlb_affinity->instr_tlb_1g_assoc = + get_associativity((l2_tlb_1G_ids & L2_INST_TLB_1G_ASSOC_MASK) + >> L2_INST_TLB_1G_ASSOC_SHFT); + tlb_affinity->instr_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l2_tlb_1G_ids & L2_INST_TLB_1G_SIZE_MASK) + >> L2_INST_TLB_1G_SIZE_SHFT); + } + } + + crat->total_entries += new_entries; + return current; +} + +static unsigned long acpi_fill_crat(struct acpi_crat_header *crat, unsigned long current) +{ + current = gen_crat_hsa_entry(crat, current); + current = gen_crat_memory_entries(crat, current); + current = gen_crat_cache_entry(crat, current); + current = gen_crat_tlb_entry(crat, current); + crat->num_nodes++; + + return current; +} + +unsigned long acpi_add_crat_table(unsigned long current, acpi_rsdp_t *rsdp) +{ + struct acpi_crat_header *crat; + + /* CRAT */ + current = acpi_align_current(current); + crat = (struct acpi_crat_header *)current; + acpi_create_crat(crat, acpi_fill_crat); + current += crat->header.length; + acpi_add_table(rsdp, crat); + + return current; +} diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 5e1f8e8..8feda80 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1,554 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_crat.h> -#include <acpi/acpi_ivrs.h> #include <acpi/acpi.h> #include <amdblocks/acpi.h> -#include <amdblocks/cpu.h> -#include <amdblocks/data_fabric.h> -#include <amdblocks/ioapic.h> -#include <cpu/amd/cpuid.h> -#include <cpu/cpu.h> #include <device/device.h> -#include <device/mmio.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> #include <FspGuids.h> -#include <soc/data_fabric.h> -#include <soc/pci_devs.h> -#include <stdint.h> - -static unsigned long gen_crat_hsa_entry(struct acpi_crat_header *crat, unsigned long current) -{ - struct crat_hsa_processing_unit *hsa_entry = (struct crat_hsa_processing_unit *)current; - memset(hsa_entry, 0, sizeof(struct crat_hsa_processing_unit)); - - hsa_entry->flags = CRAT_HSA_PR_FLAG_EN | CRAT_HSA_PR_FLAG_CPU_PRES; - hsa_entry->wave_front_size = 4; - hsa_entry->num_cpu_cores = get_cpu_count(); - hsa_entry->length = sizeof(struct crat_hsa_processing_unit); - crat->total_entries++; - - current += hsa_entry->length; - return current; -} - -static unsigned long create_crat_memory_entry(uint32_t domain, uint64_t region_base, - uint64_t region_size, unsigned long current) -{ - struct crat_memory *mem_affinity = (struct crat_memory *)current; - memset(mem_affinity, 0, sizeof(struct crat_memory)); - - mem_affinity->type = CRAT_MEMORY_TYPE; - mem_affinity->length = sizeof(struct crat_memory); - mem_affinity->proximity_domain = 0; - mem_affinity->base_address_low = region_base & 0xffffffff; - mem_affinity->base_address_high = (region_base >> 32) & 0xffffffff; - mem_affinity->length_low = region_size & 0xffffffff; - mem_affinity->length_high = (region_size >> 32) & 0xffffffff; - mem_affinity->flags = CRAT_MEM_FLAG_EN; - mem_affinity->width = 64; - - current += mem_affinity->length; - return current; -} - -static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, - unsigned long current) -{ - uint32_t dram_base_reg, dram_limit_reg, dram_hole_ctl; - uint64_t memory_length, memory_base, hole_base, size_below_hole; - size_t new_entries = 0; - - for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG; - dram_map_idx++) { - dram_base_reg = - data_fabric_read32(DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); - - if (dram_base_reg & DRAM_BASE_REG_VALID) { - dram_limit_reg = data_fabric_read32(DF_DRAM_LIMIT(dram_map_idx), - IOMS0_FABRIC_ID); - memory_length = - ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 - - ((dram_base_reg & DRAM_BASE_ADDR) >> DRAM_BASE_ADDR_SHFT); - memory_length = memory_length << 28; - memory_base = (uint64_t)(dram_base_reg & DRAM_BASE_ADDR) - << (28 - DRAM_BASE_ADDR_SHFT); - - if (memory_base == 0) { - current = - create_crat_memory_entry(0, 0ull, 0xa0000ull, current); - memory_base = 1 * MiB; - memory_length = memory_base; - new_entries++; - } - - if (dram_base_reg & DRAM_BASE_HOLE_EN) { - dram_hole_ctl = data_fabric_read32(DF_DRAM_HOLE_CTL, - IOMS0_FABRIC_ID); - hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); - size_below_hole = hole_base - memory_base; - current = create_crat_memory_entry(0, memory_base, - size_below_hole, current); - memory_length = (uint64_t)(((dram_limit_reg & DRAM_LIMIT_ADDR) - >> DRAM_LIMIT_ADDR_SHFT) - + 1 - 0x10) - << 28; - memory_base = 0x100000000; - new_entries++; - } - - current = create_crat_memory_entry(0, memory_base, memory_length, - current); - new_entries++; - } - } - crat->total_entries += new_entries; - return current; -} - -static unsigned long add_crat_cache_entry(struct crat_cache **cache_affinity, - unsigned long current) -{ - *cache_affinity = (struct crat_cache *)current; - memset(*cache_affinity, 0, sizeof(struct crat_cache)); - - (*cache_affinity)->type = CRAT_CACHE_TYPE; - (*cache_affinity)->length = sizeof(struct crat_cache); - (*cache_affinity)->flags = CRAT_CACHE_FLAG_EN | CRAT_CACHE_FLAG_CPU_CACHE; - - current += sizeof(struct crat_cache); - return current; -} - -static uint8_t get_associativity(uint32_t encoded_associativity) -{ - uint8_t associativity = 0; - - switch (encoded_associativity) { - case 0: - case 1: - case 2: - case 3: - case 4: - return encoded_associativity; - case 5: - associativity = 6; - break; - case 6: - associativity = 8; - break; - case 8: - associativity = 16; - break; - case 0xA: - associativity = 32; - break; - case 0xB: - associativity = 48; - break; - case 0xC: - associativity = 64; - break; - case 0xD: - associativity = 96; - break; - case 0xE: - associativity = 128; - break; - case 0xF: - associativity = 0xFF; - break; - default: - return 0; - } - - return associativity; -} - -static unsigned long gen_crat_cache_entry(struct acpi_crat_header *crat, unsigned long current) -{ - size_t total_num_threads, num_threads_sharing0, num_threads_sharing1, - num_threads_sharing2, num_threads_sharing3, thread, new_entries; - struct cpuid_result cache_props0, cache_props1, cache_props2, cache_props3; - uint8_t sibling_mask = 0; - uint32_t l1_data_cache_ids, l1_inst_cache_ids, l2_cache_ids, l3_cache_ids; - struct crat_cache *cache_affinity = NULL; - - total_num_threads = get_cpu_count(); - - cache_props0 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_0); - cache_props1 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_1); - cache_props2 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_2); - cache_props3 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_3); - - l1_data_cache_ids = cpuid_ecx(CPUID_L1_TLB_CACHE_IDS); - l1_inst_cache_ids = cpuid_edx(CPUID_L1_TLB_CACHE_IDS); - l2_cache_ids = cpuid_ecx(CPUID_L2_L3_CACHE_L2_TLB_IDS); - l3_cache_ids = cpuid_edx(CPUID_L2_L3_CACHE_L2_TLB_IDS); - - num_threads_sharing0 = - ((cache_props0.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - num_threads_sharing1 = - ((cache_props1.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - num_threads_sharing2 = - ((cache_props2.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - num_threads_sharing3 = - ((cache_props3.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - - new_entries = 0; - for (thread = 0; thread < total_num_threads; thread++) { - /* L1 data cache */ - if (thread % num_threads_sharing0 == 0) { - current = add_crat_cache_entry(&cache_affinity, current); - new_entries++; - - cache_affinity->flags |= CRAT_CACHE_FLAG_DATA_CACHE; - cache_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing0; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - cache_affinity->cache_properties = - (cache_props0.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; - cache_affinity->cache_size = - (l1_data_cache_ids & L1_DC_SIZE_MASK) >> L1_DC_SIZE_SHFT; - cache_affinity->cache_level = CRAT_L1_CACHE; - cache_affinity->lines_per_tag = - (l1_data_cache_ids & L1_DC_LINE_TAG_MASK) - >> L1_DC_LINE_TAG_SHFT; - cache_affinity->cache_line_size = - (l1_data_cache_ids & L1_DC_LINE_SIZE_MASK) - >> L1_DC_LINE_SIZE_SHFT; - cache_affinity->associativity = - (l1_data_cache_ids & L1_DC_ASSOC_MASK) >> L1_DC_ASSOC_SHFT; - cache_affinity->cache_latency = 1; - } - - /* L1 instruction cache */ - if (thread % num_threads_sharing1 == 0) { - current = add_crat_cache_entry(&cache_affinity, current); - new_entries++; - - cache_affinity->flags |= CRAT_CACHE_FLAG_INSTR_CACHE; - cache_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing1; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - cache_affinity->cache_properties = - (cache_props1.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; - cache_affinity->cache_size = - (l1_inst_cache_ids & L1_IC_SIZE_MASK) >> L1_IC_SIZE_SHFT; - cache_affinity->cache_level = CRAT_L1_CACHE; - cache_affinity->lines_per_tag = - (l1_inst_cache_ids & L1_IC_LINE_TAG_MASK) - >> L1_IC_LINE_TAG_SHFT; - cache_affinity->cache_line_size = - (l1_inst_cache_ids & L1_IC_LINE_SIZE_MASK) - >> L1_IC_LINE_SIZE_SHFT; - cache_affinity->associativity = - (l1_inst_cache_ids & L1_IC_ASSOC_MASK) >> L1_IC_ASSOC_SHFT; - cache_affinity->cache_latency = 1; - } - - /* L2 cache */ - if (thread % num_threads_sharing2 == 0) { - current = add_crat_cache_entry(&cache_affinity, current); - new_entries++; - - cache_affinity->flags |= - CRAT_CACHE_FLAG_DATA_CACHE | CRAT_CACHE_FLAG_INSTR_CACHE; - cache_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - cache_affinity->cache_properties = - (cache_props2.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; - cache_affinity->cache_size = - (l2_cache_ids & L2_DC_SIZE_MASK) >> L2_DC_SIZE_SHFT; - cache_affinity->cache_level = CRAT_L2_CACHE; - cache_affinity->lines_per_tag = - (l2_cache_ids & L2_DC_LINE_TAG_MASK) >> L2_DC_LINE_TAG_SHFT; - cache_affinity->cache_line_size = - (l2_cache_ids & L2_DC_LINE_SIZE_MASK) >> L2_DC_LINE_SIZE_SHFT; - cache_affinity->associativity = get_associativity( - (l2_cache_ids & L2_DC_ASSOC_MASK) >> L2_DC_ASSOC_SHFT); - cache_affinity->cache_latency = 1; - } - - /* L3 cache */ - if (thread % num_threads_sharing3 == 0) { - current = add_crat_cache_entry(&cache_affinity, current); - new_entries++; - - cache_affinity->flags |= - CRAT_CACHE_FLAG_DATA_CACHE | CRAT_CACHE_FLAG_INSTR_CACHE; - cache_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing3; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - cache_affinity->cache_properties = - (cache_props0.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; - cache_affinity->cache_size = - ((l3_cache_ids & L3_DC_SIZE_MASK) >> L3_DC_SIZE_SHFT) * 512; - cache_affinity->cache_level = CRAT_L3_CACHE; - cache_affinity->lines_per_tag = - (l3_cache_ids & L3_DC_LINE_TAG_MASK) >> L3_DC_LINE_TAG_SHFT; - cache_affinity->cache_line_size = - (l3_cache_ids & L3_DC_LINE_SIZE_MASK) >> L3_DC_LINE_SIZE_SHFT; - cache_affinity->associativity = get_associativity( - (l3_cache_ids & L3_DC_ASSOC_MASK) >> L3_DC_ASSOC_SHFT); - cache_affinity->cache_latency = 1; - } - } - crat->total_entries += new_entries; - return current; -} - -static uint8_t get_tlb_size(enum tlb_type type, struct crat_tlb *crat_tlb_entry, - uint16_t raw_assoc_size) -{ - uint8_t tlbsize; - - if (raw_assoc_size >= 256) { - tlbsize = (uint8_t)(raw_assoc_size / 256); - - if (type == tlb_2m) - crat_tlb_entry->flags |= CRAT_TLB_FLAG_2MB_BASE_256; - else if (type == tlb_4k) - crat_tlb_entry->flags |= CRAT_TLB_FLAG_4K_BASE_256; - else if (type == tlb_1g) - crat_tlb_entry->flags |= CRAT_TLB_FLAG_1GB_BASE_256; - } else { - tlbsize = (uint8_t)(raw_assoc_size); - } - return tlbsize; -} - -static unsigned long add_crat_tlb_entry(struct crat_tlb **tlb_affinity, unsigned long current) -{ - *tlb_affinity = (struct crat_tlb *)current; - memset(*tlb_affinity, 0, sizeof(struct crat_tlb)); - - (*tlb_affinity)->type = CRAT_TLB_TYPE; - (*tlb_affinity)->length = sizeof(struct crat_tlb); - (*tlb_affinity)->flags = CRAT_TLB_FLAG_EN | CRAT_TLB_FLAG_CPU_TLB; - - current += sizeof(struct crat_tlb); - return current; -} - -static unsigned long gen_crat_tlb_entry(struct acpi_crat_header *crat, unsigned long current) -{ - size_t total_num_threads, num_threads_sharing0, num_threads_sharing1, - num_threads_sharing2, thread, new_entries; - struct cpuid_result cache_props0, cache_props1, cache_props2; - uint8_t sibling_mask = 0; - uint32_t l1_tlb_2M4M_ids, l1_tlb_4K_ids, l2_tlb_2M4M_ids, l2_tlb_4K_ids, l1_tlb_1G_ids, - l2_tlb_1G_ids; - struct crat_tlb *tlb_affinity = NULL; - - total_num_threads = get_cpu_count(); - cache_props0 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_0); - cache_props1 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_1); - cache_props2 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_2); - - l1_tlb_2M4M_ids = cpuid_eax(CPUID_L1_TLB_CACHE_IDS); - l2_tlb_2M4M_ids = cpuid_eax(CPUID_L2_L3_CACHE_L2_TLB_IDS); - l1_tlb_4K_ids = cpuid_ebx(CPUID_L1_TLB_CACHE_IDS); - l2_tlb_4K_ids = cpuid_ebx(CPUID_L2_L3_CACHE_L2_TLB_IDS); - l1_tlb_1G_ids = cpuid_eax(CPUID_TLB_L1L2_1G_IDS); - l2_tlb_1G_ids = cpuid_ebx(CPUID_TLB_L1L2_1G_IDS); - - num_threads_sharing0 = - ((cache_props0.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - num_threads_sharing1 = - ((cache_props1.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - num_threads_sharing2 = - ((cache_props2.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; - - new_entries = 0; - for (thread = 0; thread < total_num_threads; thread++) { - - /* L1 data TLB */ - if (thread % num_threads_sharing0 == 0) { - current = add_crat_tlb_entry(&tlb_affinity, current); - new_entries++; - - tlb_affinity->flags |= CRAT_TLB_FLAG_DATA_TLB; - tlb_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing0; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - tlb_affinity->tlb_level = CRAT_L1_CACHE; - - tlb_affinity->data_tlb_2mb_assoc = - (l1_tlb_2M4M_ids & L1_DAT_TLB_2M4M_ASSOC_MASK) - >> L1_DAT_TLB_2M4M_ASSOC_SHFT; - tlb_affinity->data_tlb_2mb_size = - get_tlb_size(tlb_2m, tlb_affinity, - (l1_tlb_2M4M_ids & L1_DAT_TLB_2M4M_SIZE_MASK) - >> L1_DAT_TLB_2M4M_SIZE_SHFT); - - tlb_affinity->data_tlb_4k_assoc = - (l1_tlb_4K_ids & L1_DAT_TLB_4K_ASSOC_MASK) - >> L1_DAT_TLB_4K_ASSOC_SHFT; - tlb_affinity->data_tlb_4k_size = - get_tlb_size(tlb_4k, tlb_affinity, - (l1_tlb_4K_ids & L1_DAT_TLB_4K_SIZE_MASK) - >> L1_DAT_TLB_4K_SIZE_SHFT); - - tlb_affinity->data_tlb_1g_assoc = - (l1_tlb_1G_ids & L1_DAT_TLB_1G_ASSOC_MASK) - >> L1_DAT_TLB_1G_ASSOC_SHFT; - tlb_affinity->data_tlb_1g_size = - get_tlb_size(tlb_1g, tlb_affinity, - (l1_tlb_1G_ids & L1_DAT_TLB_1G_SIZE_MASK) - >> L1_DAT_TLB_1G_SIZE_SHFT); - } - - /* L1 instruction TLB */ - if (thread % num_threads_sharing1 == 0) { - current = add_crat_tlb_entry(&tlb_affinity, current); - new_entries++; - - tlb_affinity->flags |= CRAT_TLB_FLAG_INSTR_TLB; - tlb_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing1; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - tlb_affinity->tlb_level = CRAT_L1_CACHE; - tlb_affinity->instr_tlb_2mb_assoc = - (l1_tlb_2M4M_ids & L1_INST_TLB_2M4M_ASSOC_MASK) - >> L1_INST_TLB_2M4M_ASSOC_SHFT; - tlb_affinity->instr_tlb_2mb_size = - get_tlb_size(tlb_2m, tlb_affinity, - (l1_tlb_2M4M_ids & L1_INST_TLB_2M4M_SIZE_MASK) - >> L1_INST_TLB_2M4M_SIZE_SHFT); - - tlb_affinity->instr_tlb_4k_assoc = - (l1_tlb_4K_ids & L1_INST_TLB_4K_ASSOC_MASK) - >> L1_INST_TLB_4K_ASSOC_SHFT; - tlb_affinity->instr_tlb_4k_size = - get_tlb_size(tlb_4k, tlb_affinity, - (l1_tlb_4K_ids & L1_INST_TLB_4K_SIZE_MASK) - >> L1_INST_TLB_4K_SIZE_SHFT); - - tlb_affinity->instr_tlb_1g_assoc = - (l1_tlb_1G_ids & L1_INST_TLB_1G_ASSOC_MASK) - >> L1_INST_TLB_1G_ASSOC_SHFT; - tlb_affinity->instr_tlb_1g_size = - get_tlb_size(tlb_1g, tlb_affinity, - (l1_tlb_1G_ids & L1_INST_TLB_1G_SIZE_MASK) - >> L1_INST_TLB_1G_SIZE_SHFT); - } - - /* L2 Data TLB */ - if (thread % num_threads_sharing2 == 0) { - current = add_crat_tlb_entry(&tlb_affinity, current); - new_entries++; - - tlb_affinity->flags |= CRAT_TLB_FLAG_DATA_TLB; - tlb_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - tlb_affinity->tlb_level = CRAT_L2_CACHE; - tlb_affinity->data_tlb_2mb_assoc = - (l2_tlb_2M4M_ids & L2_DAT_TLB_2M4M_ASSOC_MASK) - >> L2_DAT_TLB_2M4M_ASSOC_SHFT; - tlb_affinity->data_tlb_2mb_size = - get_tlb_size(tlb_2m, tlb_affinity, - (l2_tlb_2M4M_ids & L2_DAT_TLB_2M4M_SIZE_MASK) - >> L2_DAT_TLB_2M4M_SIZE_SHFT); - - tlb_affinity->data_tlb_4k_assoc = - get_associativity((l2_tlb_4K_ids & L2_DAT_TLB_2M4M_ASSOC_MASK) - >> L2_DAT_TLB_4K_ASSOC_SHFT); - tlb_affinity->data_tlb_4k_size = - get_tlb_size(tlb_4k, tlb_affinity, - (l2_tlb_2M4M_ids & L2_DAT_TLB_4K_SIZE_MASK) - >> L2_DAT_TLB_4K_SIZE_SHFT); - - tlb_affinity->data_tlb_1g_assoc = - get_associativity((l2_tlb_1G_ids & L2_DAT_TLB_1G_ASSOC_MASK) - >> L2_DAT_TLB_1G_ASSOC_SHFT); - tlb_affinity->data_tlb_1g_size = - get_tlb_size(tlb_1g, tlb_affinity, - (l2_tlb_1G_ids & L2_DAT_TLB_1G_SIZE_MASK) - >> L2_DAT_TLB_1G_SIZE_SHFT); - } - - /* L2 Instruction TLB */ - if (thread % num_threads_sharing2 == 0) { - current = add_crat_tlb_entry(&tlb_affinity, current); - new_entries++; - - tlb_affinity->flags |= CRAT_TLB_FLAG_INSTR_TLB; - tlb_affinity->proc_id_low = thread; - sibling_mask = 1; - for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) - sibling_mask = (sibling_mask << 1) + 1; - tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); - tlb_affinity->tlb_level = CRAT_L2_CACHE; - tlb_affinity->instr_tlb_2mb_assoc = get_associativity( - (l2_tlb_2M4M_ids & L2_INST_TLB_2M4M_ASSOC_MASK) - >> L2_INST_TLB_2M4M_ASSOC_SHFT); - tlb_affinity->instr_tlb_2mb_size = - get_tlb_size(tlb_2m, tlb_affinity, - (l2_tlb_2M4M_ids & L2_INST_TLB_2M4M_SIZE_MASK) - >> L2_INST_TLB_2M4M_SIZE_SHFT); - - tlb_affinity->instr_tlb_4k_assoc = - get_associativity((l2_tlb_4K_ids & L2_INST_TLB_4K_ASSOC_MASK) - >> L2_INST_TLB_4K_ASSOC_SHFT); - tlb_affinity->instr_tlb_4k_size = - get_tlb_size(tlb_4k, tlb_affinity, - (l2_tlb_4K_ids & L2_INST_TLB_4K_SIZE_MASK) - >> L2_INST_TLB_4K_SIZE_SHFT); - - tlb_affinity->instr_tlb_1g_assoc = - get_associativity((l2_tlb_1G_ids & L2_INST_TLB_1G_ASSOC_MASK) - >> L2_INST_TLB_1G_ASSOC_SHFT); - tlb_affinity->instr_tlb_1g_size = - get_tlb_size(tlb_1g, tlb_affinity, - (l2_tlb_1G_ids & L2_INST_TLB_1G_SIZE_MASK) - >> L2_INST_TLB_1G_SIZE_SHFT); - } - } - - crat->total_entries += new_entries; - return current; -} - -static unsigned long acpi_fill_crat(struct acpi_crat_header *crat, unsigned long current) -{ - current = gen_crat_hsa_entry(crat, current); - current = gen_crat_memory_entries(crat, current); - current = gen_crat_cache_entry(crat, current); - current = gen_crat_tlb_entry(crat, current); - crat->num_nodes++; - - return current; -} +#include <types.h> unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - struct acpi_crat_header *crat; - /* CRAT */ - current = acpi_align_current(current); - crat = (struct acpi_crat_header *)current; - acpi_create_crat(crat, acpi_fill_crat); - current += crat->header.length; - acpi_add_table(rsdp, crat); + current = acpi_add_crat_table(current, rsdp); /* add ALIB SSDT from HOB */ current = acpi_align_current(current); -- To view, visit https://review.coreboot.org/c/coreboot/+/80223?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a7853748512811d3d4e124224fcd459e527522c Gerrit-Change-Number: 80223 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/amd: use common ACPI_SCI_IRQ definition
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80222?usp=email ) Change subject: soc/amd: use common ACPI_SCI_IRQ definition ...................................................................... soc/amd: use common ACPI_SCI_IRQ definition ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/chausie/mainboard.c M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/majolica/mainboard.c M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/amd/mayan/mainboard.c M src/mainboard/amd/onyx_poc/mainboard.c M src/mainboard/amd/pademelon/mainboard.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/myst/mainboard.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/zork/mainboard.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/agesa_acpi.c D src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/acpi/pm_state.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/genoa_poc/fch.c D src/soc/amd/genoa_poc/include/soc/acpi.h M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/agesa_acpi.c D src/soc/amd/glinda/include/soc/acpi.h M src/soc/amd/mendocino/acpi.c M src/soc/amd/mendocino/agesa_acpi.c D src/soc/amd/mendocino/include/soc/acpi.h M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/agesa_acpi.c D src/soc/amd/phoenix/include/soc/acpi.h M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/fch.c D src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/include/soc/acpi.h 38 files changed, 16 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/80222/1 diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index 5e20946..ed4e706 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -2,10 +2,10 @@ #include <console/console.h> #include <device/device.h> +#include <amdblocks/acpi.h> #include <amdblocks/amd_pci_util.h> #include <FspsUpd.h> #include <gpio.h> -#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index e97bb31..0deba67 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> #include <device/device.h> -#include <soc/acpi.h> #include <types.h> #include "gpio.h" diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c index 41e314a..c3eb70a 100644 --- a/src/mainboard/amd/chausie/mainboard.c +++ b/src/mainboard/amd/chausie/mainboard.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> #include <device/device.h> -#include <soc/acpi.h> #include <types.h> #include "gpio.h" diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index d89449f..8353d820 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <device/device.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 9dbd4e4..5f5a90c 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> #include <device/device.h> -#include <soc/acpi.h> #include <types.h> /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index d3b79e6..7975c10 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <console/console.h> #include <device/device.h> #include <amdblocks/amd_pci_util.h> #include <FspsUpd.h> -#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/amd/mayan/mainboard.c b/src/mainboard/amd/mayan/mainboard.c index 0785366..427c085 100644 --- a/src/mainboard/amd/mayan/mainboard.c +++ b/src/mainboard/amd/mayan/mainboard.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> #include <device/device.h> -#include <soc/acpi.h> #include <types.h> #include "gpio.h" diff --git a/src/mainboard/amd/onyx_poc/mainboard.c b/src/mainboard/amd/onyx_poc/mainboard.c index af89e14..bc181ce 100644 --- a/src/mainboard/amd/onyx_poc/mainboard.c +++ b/src/mainboard/amd/onyx_poc/mainboard.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/acpi.h> +#include <amdblocks/acpi.h> #include <soc/amd_pci_int_defs.h> #include <amdblocks/amd_pci_util.h> #include <types.h> diff --git a/src/mainboard/amd/pademelon/mainboard.c b/src/mainboard/amd/pademelon/mainboard.c index 8be12f1..f4d5be9 100644 --- a/src/mainboard/amd/pademelon/mainboard.c +++ b/src/mainboard/amd/pademelon/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <device/device.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index af79a5e..18d5e8f 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/psp.h> @@ -12,7 +13,6 @@ #include <device/device.h> #include <drivers/i2c/tpm/chip.h> #include <gpio.h> -#include <soc/acpi.h> #include <variant/ec.h> #define BACKLIGHT_GPIO GPIO_129 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 5ddc5ae..5ecc52e 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <string.h> #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index 36f5bab..e5d2858 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/xhci.h> @@ -8,7 +9,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> -#include <soc/acpi.h> #include <variant/ec.h> /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 125bebb..8a395a8 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/psp.h> @@ -9,7 +10,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> -#include <soc/acpi.h> #include <variant/ec.h> /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 74ed679..4aa0c58 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/acpi.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -11,7 +12,6 @@ #include <boardid.h> #include <gpio.h> #include <smbios.h> -#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/platform_descriptors.h> diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index ea895c9..7a5fdf0 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -13,7 +13,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c index e22cc08..96ff0f0 100644 --- a/src/soc/amd/cezanne/agesa_acpi.c +++ b/src/soc/amd/cezanne/agesa_acpi.c @@ -4,7 +4,6 @@ #include <amdblocks/acpi.h> #include <device/device.h> #include <FspGuids.h> -#include <soc/acpi.h> #include <types.h> unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h deleted file mode 100644 index c709b78..0000000 --- a/src/soc/amd/cezanne/include/soc/acpi.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef AMD_CEZANNE_ACPI_H -#define AMD_CEZANNE_ACPI_H - -#define ACPI_SCI_IRQ 9 - -#endif /* AMD_CEZANNE_ACPI_H */ diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 547163c..9d0ece1 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -12,7 +12,6 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <soc/acpi.h> #include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c index ccfef0a..23a7d45 100644 --- a/src/soc/amd/common/block/acpi/pm_state.c +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -4,7 +4,6 @@ #include <acpi/acpi_pm.h> #include <amdblocks/acpi.h> #include <bootstate.h> -#include <soc/acpi.h> #include <soc/nvs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 2a29f37..8642d0f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -8,6 +8,8 @@ #include <device/device.h> #include <types.h> +#define ACPI_SCI_IRQ 9 + /* ACPI MMIO registers 0xfed80800 */ #define MMIO_ACPI_PM1_EVT_BLK 0x00 #define MMIO_ACPI_PM1_STS 0x00 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 96b9a2c..4e81316 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -17,7 +17,6 @@ #include <amdblocks/ioapic.h> #include <amdblocks/iomap.h> #include <amdblocks/lpc.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index cadf8db..8f842f9 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -9,7 +9,6 @@ #include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> -#include <soc/acpi.h> #include <vendorcode/amd/opensil/genoa_poc/opensil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/soc/amd/genoa_poc/fch.c b/src/soc/amd/genoa_poc/fch.c index f340d82..3af741c 100644 --- a/src/soc/amd/genoa_poc/fch.c +++ b/src/soc/amd/genoa_poc/fch.c @@ -7,7 +7,6 @@ #include <amdblocks/smi.h> #include <bootstate.h> #include <cpu/x86/smm.h> -#include <soc/acpi.h> #include <soc/amd_pci_int_defs.h> #include <soc/smi.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/genoa_poc/include/soc/acpi.h b/src/soc/amd/genoa_poc/include/soc/acpi.h deleted file mode 100644 index a2a9f39..0000000 --- a/src/soc/amd/genoa_poc/include/soc/acpi.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef AMD_GENOA_POC_ACPI_H -#define AMD_GENOA_POC_ACPI_H - -#define ACPI_SCI_IRQ 9 - -#endif /* AMD_GENOA_POC_ACPI_H */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index a927f8b..8cca10d 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -16,7 +16,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/glinda/agesa_acpi.c b/src/soc/amd/glinda/agesa_acpi.c index e04f7cb..68273d1 100644 --- a/src/soc/amd/glinda/agesa_acpi.c +++ b/src/soc/amd/glinda/agesa_acpi.c @@ -6,7 +6,6 @@ #include <amdblocks/acpi.h> #include <device/device.h> #include <FspGuids.h> -#include <soc/acpi.h> #include <types.h> unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, diff --git a/src/soc/amd/glinda/include/soc/acpi.h b/src/soc/amd/glinda/include/soc/acpi.h deleted file mode 100644 index 891b658..0000000 --- a/src/soc/amd/glinda/include/soc/acpi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* TODO: Move to common */ - -#ifndef AMD_GLINDA_ACPI_H -#define AMD_GLINDA_ACPI_H - -#define ACPI_SCI_IRQ 9 - -#endif /* AMD_GLINDA_ACPI_H */ diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 80d407c..11261db 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -15,7 +15,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/mendocino/agesa_acpi.c b/src/soc/amd/mendocino/agesa_acpi.c index 8866fc4..7ff8403 100644 --- a/src/soc/amd/mendocino/agesa_acpi.c +++ b/src/soc/amd/mendocino/agesa_acpi.c @@ -6,7 +6,6 @@ #include <amdblocks/acpi.h> #include <device/device.h> #include <FspGuids.h> -#include <soc/acpi.h> #include <types.h> unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, diff --git a/src/soc/amd/mendocino/include/soc/acpi.h b/src/soc/amd/mendocino/include/soc/acpi.h deleted file mode 100644 index 25f9234..0000000 --- a/src/soc/amd/mendocino/include/soc/acpi.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef AMD_MENDOCINO_ACPI_H -#define AMD_MENDOCINO_ACPI_H - -#define ACPI_SCI_IRQ 9 - -#endif /* AMD_MENDOCINO_ACPI_H */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index ce727a8..76de7a0 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -16,7 +16,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/phoenix/agesa_acpi.c b/src/soc/amd/phoenix/agesa_acpi.c index e4fa2bf..4ebe814 100644 --- a/src/soc/amd/phoenix/agesa_acpi.c +++ b/src/soc/amd/phoenix/agesa_acpi.c @@ -7,7 +7,6 @@ #include <commonlib/bsd/helpers.h> #include <device/device.h> #include <FspGuids.h> -#include <soc/acpi.h> #include <types.h> unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, diff --git a/src/soc/amd/phoenix/include/soc/acpi.h b/src/soc/amd/phoenix/include/soc/acpi.h deleted file mode 100644 index 3fea5cc..0000000 --- a/src/soc/amd/phoenix/include/soc/acpi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* TODO: Move to common */ - -#ifndef AMD_PHOENIX_ACPI_H -#define AMD_PHOENIX_ACPI_H - -#define ACPI_SCI_IRQ 9 - -#endif /* AMD_PHOENIX_ACPI_H */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 92f48df..d864053 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -19,7 +19,6 @@ #include <amdblocks/chip.h> #include <amdblocks/cpu.h> #include <amdblocks/ioapic.h> -#include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include "chip.h" diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index bde9543..5e1f8e8 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -14,7 +14,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <FspGuids.h> -#include <soc/acpi.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <stdint.h> diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index a1eef6f..bfe65a2 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -13,7 +13,6 @@ #include <amdblocks/gpio.h> #include <amdblocks/i2c.h> #include <amdblocks/smi.h> -#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> #include <soc/iomap.h> diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h deleted file mode 100644 index 8dee91d..0000000 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef AMD_PICASSO_ACPI_H -#define AMD_PICASSO_ACPI_H - -#define ACPI_SCI_IRQ 9 - -#endif /* AMD_PICASSO_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 0065d6e..f0c35c0 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -6,8 +6,6 @@ #include <acpi/acpi.h> #include <amdblocks/acpi.h> -#define ACPI_SCI_IRQ 9 - #if CONFIG(STONEYRIDGE_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else -- To view, visit https://review.coreboot.org/c/coreboot/+/80222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Gerrit-Change-Number: 80222 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/*/acpi: use common soc_acpi_write_tables prototype
by Felix Held (Code Review) 26 Jan '24

26 Jan '24

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