coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

[S] Change in coreboot[main]: northbridge/intel/sandybridge: Enable x86_64 for mrc.bin
by Felix Held (Code Review) 05 Jan '24

05 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79754?usp=email ) Change subject: northbridge/intel/sandybridge: Enable x86_64 for mrc.bin ...................................................................... northbridge/intel/sandybridge: Enable x86_64 for mrc.bin Enable x86_64 support for MRC.bin: - Add a wrapper function for console printing that calls into long mode to call native do_putchar - Remove Kconfig guard for x86_64 when MRC is being used Tested: Booted Lenovo X220 using mrc.bin under x86_64 and MRC is able to print to the console. Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79754 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/mrc_wrapper.S M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 20 insertions(+), 3 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 10c0ae3..649ef4e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,7 +1,7 @@ config CPU_INTEL_MODEL_206AX bool select ARCH_X86 - select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT + select HAVE_EXP_X86_64_SUPPORT select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/sandybridge/mrc_wrapper.S b/src/northbridge/intel/sandybridge/mrc_wrapper.S index 860526b..d68ce09 100644 --- a/src/northbridge/intel/sandybridge/mrc_wrapper.S +++ b/src/northbridge/intel/sandybridge/mrc_wrapper.S @@ -25,3 +25,13 @@ mov %ebp, %esp popal ret + + /* + * Callback for MRC to print a character on the console. + * As MRC is x86_32 call into long mode and use the x86_64 + * function do_putchar to print to console. + */ + +#include <src/cpu/x86/64bit/prot2long.inc> + +prot2lm_wrapper do_putchar diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index d59aa86..dde5742 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -52,6 +52,7 @@ /* Assembly functions: */ void mrc_wrapper(void *func_ptr, uint32_t arg1); +void __prot2lm_do_putchar(uint8_t byte); static void save_mrc_data(struct pei_data *pei_data) { @@ -154,8 +155,14 @@ system_reset(); } - /* Pass console handler in pei_data */ - pei_data->tx_byte_ptr = (uintptr_t)do_putchar; + /* + * Pass console handler in pei_data. On x86_64 provide a wrapper around + * do_putchar that switches to long mode before calling do_putchar. + */ + if (ENV_X86_64) + pei_data->tx_byte_ptr = (uintptr_t)__prot2lm_do_putchar; + else + pei_data->tx_byte_ptr = (uintptr_t)do_putchar; /* Locate and call UEFI System Agent binary. */ entry = cbfs_map("mrc.bin", NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/79754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Gerrit-Change-Number: 79754 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: cpu/x86/64bit/mode_switch2: The reverse function to mode_switch
by Felix Held (Code Review) 05 Jan '24

05 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79753?usp=email ) Change subject: cpu/x86/64bit/mode_switch2: The reverse function to mode_switch ...................................................................... cpu/x86/64bit/mode_switch2: The reverse function to mode_switch Add another mode_switch assembly function to call x86_64 code from x86_32 code. This is particullary useful for BLOBs like mrc.bin or FSP that calls back into coreboot. The user must first wrap all functions that are to be called from x86_32 using the macro prot2lm_wrapper. Instead of using the original function the wrapped functions must be passed to the x86_32 BLOBs. The assembly code assume that 0-3 32bit arguments are passed to the wrapped function. Tested: - Called x86_64 code from x86_32 code in qemu. - Booted Lenovo X220 using x86_32 MRC using x86_64 console. Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79753 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/64bit/Makefile.inc A src/cpu/x86/64bit/mode_switch2.S A src/cpu/x86/64bit/prot2long.inc 3 files changed, 76 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/x86/64bit/Makefile.inc b/src/cpu/x86/64bit/Makefile.inc index e1cf743..24a5a96 100644 --- a/src/cpu/x86/64bit/Makefile.inc +++ b/src/cpu/x86/64bit/Makefile.inc @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only all_x86-y += mode_switch.S +all_x86-y += mode_switch2.S # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/pt.S $(obj)/config.h diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S new file mode 100644 index 0000000..65e9d94 --- /dev/null +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Calls a x86_64 function from x86_32 context. + * Must not be directly invoked from C code! + */ + +.text +.code32 + .section ".text.long_mode_call_3arg", "ax", @progbits + .global long_mode_call_3arg +long_mode_call_3arg: + + /* Function to call is passed in EAX. */ + + /* Backup registers */ + pushal + + /* Backup stack pointer */ + mov %esp, %ebp + + /* Enter long mode, preserves ebx */ + #include <cpu/x86/64bit/entry64.inc> + + /* Align stack */ + movabs $0xfffffffffffffff0, %rax + andq %rax, %rsp + + movl 28(%rbp), %ebx /* Function to call */ + movl 36(%rbp), %edi /* 1st arg */ + movl 40(%rbp), %esi /* 2nd arg */ + movl 44(%rbp), %edx /* 3rd arg */ + + call *%rbx + + /* Store return value on stack. popal will fetch it. */ + mov %eax, 28(%rbp) + shr $32, %rax + movl %eax, 24(%rbp) + + #include <cpu/x86/64bit/exit32.inc> + + /* Restore stack pointer */ + mov %ebp, %esp + + /* Restore registers */ + popal + + ret diff --git a/src/cpu/x86/64bit/prot2long.inc b/src/cpu/x86/64bit/prot2long.inc new file mode 100644 index 0000000..96c44a86 --- /dev/null +++ b/src/cpu/x86/64bit/prot2long.inc @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.text +.code32 +/* + * Macro to wrap a x86_64 function to be called from x86_32 code. + * This assumes that 0-3 32bit arguments are passed to the + * calling function. + * + * In order to preserve ESP without setting up a stack frame + * pass the function to call in EAX. The macro prepends "__prot2lm_" + * to the wrapped function name. + */ +.macro prot2lm_wrapper func2call:req + .global __prot2lm_\func2call +__prot2lm_\func2call : + /* Get function to call */ + mov $\func2call, %eax + + /* + * Jump to function instead of call. + * It will return directly to caller. + */ + jmp long_mode_call_3arg + + /* Not reachable */ +.endm -- To view, visit https://review.coreboot.org/c/coreboot/+/79753?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Gerrit-Change-Number: 79753 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Nico Huber, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 11: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/15a5b81a_eb254710 : PS11, Line 630: root->max_payload_set = 1; > That's a good catch, Krystian! This means we couldn't avoid walking the tree […] Exactly. Ad.1. This happens right now in patchset 11 AFAIU. Ad.2. Yes, that's the solution I proposed and intend to incorporate. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Jan 2024 13:17:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Nico Huber (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 11: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/11d90c44_04e59b8f : PS11, Line 630: root->max_payload_set = 1; > This would also work, and is much easier than what I suggested. […] That's a good catch, Krystian! This means we couldn't avoid walking the tree a second time. TBH, to fix this, I would start from scratch, as all the designs we had so far tried to avoid exactly this. When walking the tree a second time, it becomes much simpler, I believe: 1. On the way down, set every device to its own maximum. On the way up, propagate the minimum from the endpoints up to the root port (making sure that we use the minimum of what a bridge was configured and the value from the child, to avoid problems with multiple children and different MPS). i.e. bridge mps = MIN(bridge mps, child mps) 2. Walk a second time, this time we have the minimum configured at the root port and have to propagate that down to all bridges and the endpoints. i.e. simply, child mps = parent mps. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Jan 2024 13:10:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: drivers/mipi: Add support for BOE_NV110WUM_L60 panel
by Yidi Lin (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Ruihai Zhou, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78956?usp=email ) Change subject: drivers/mipi: Add support for BOE_NV110WUM_L60 panel ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Gerrit-Change-Number: 78956 Gerrit-PatchSet: 8 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 13:02:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > So I looked into the spec again and the reasons why we handled this (badly) […] Thanks for the insights Nico. Indeed, leveling all the Max Payload Size to 0 (128B) would work too. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Jan 2024 12:49:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Nico Huber (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Michał Żygowski, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: So I looked into the spec again and the reasons why we handled this (badly) in coreboot in the first place. This seems to be much more of a thing to be configured by the OS. It was only introduced into coreboot as a workaround for a broken FSP: https://ticket.coreboot.org/issues/218 So maybe before we go deeper down this rabbit hole, should we test if dis- abling the code would allow the OS to do its job properly? Or alternatively, to fix any potential damage done by FSP, simply reset all settings to the default 128B. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Jan 2024 12:36:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Krystian Hebel (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Michał Żygowski, Nico Huber, Patrick Rudolph. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 11: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/d2756151_5cb1c09c : PS11, Line 630: root->max_payload_set = 1; > So basically, at the end of root port scanning, we need to set the root port's Max Payload Size to a […] This would also work, and is much easier than what I suggested. The problem with testing is that this code only limits _max_ payload size. If higher layers only use smaller packages, a potential misconfiguration won't show problems anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Jan 2024 12:04:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Nico Huber, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 11: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/8c92ecea_3f49965d : PS11, Line 630: root->max_payload_set = 1; > I think this still doesn't catch case where two endpoints have different max payload sizes, for exam […] So basically, at the end of root port scanning, we need to set the root port's Max Payload Size to all children, and children's children, etc. No need to restart the scan loop. Unfortunately I am not sure we have a configuration like that. Maybe if there is a PCIe WIFI card with Max Payload Size of 128B then yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Jan 2024 09:41:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/apollolake: Create IBB, IBBL and OBB
by Sean Rhodes (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Andrey Petrov, Angel Pons, Michał Żygowski. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65680?usp=email ) Change subject: soc/intel/apollolake: Create IBB, IBBL and OBB ...................................................................... Patch Set 26: (1 comment) Patchset: PS25: > You use it to stitch the image in CB:61922 Ah - the capitals confused me 😊 Yup, FIT and MEU required - gets everything working apart from verified boot as that needs the bootblock to be relocatable -- To view, visit https://review.coreboot.org/c/coreboot/+/65680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5 Gerrit-Change-Number: 65680 Gerrit-PatchSet: 26 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 09:38:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2024