coreboot-gerrit January 2024

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[M] Change in coreboot[main]: mb/google/guybrush: Update DDI descriptor definition
by Raul Rangel (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79793?usp=email ) Change subject: mb/google/guybrush: Update DDI descriptor definition ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/79793/comment/cf7d4400_12071830 : PS2, Line 36: .connector_type = DDI_EDP, : .aux_index = DDI_AUX1, : .hdp_index = DDI_HDP1 Optional: Can we `#define` these like we did for the DXIO descriptors? We could then make the variants implement `variant_get_ddi_descriptors` instead of having the `variant_has_hdmi` function. -- To view, visit https://review.coreboot.org/c/coreboot/+/79793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4ecbaaab5a21c30a67777a4522dc579cc9fa7e6 Gerrit-Change-Number: 79793 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 16:51:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/guybrush: Update DDI descriptor definition
by Jon Murphy (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth. Hello Jason Nien, Martin Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79793?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/guybrush: Update DDI descriptor definition ...................................................................... mb/google/guybrush: Update DDI descriptor definition Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ib4ecbaaab5a21c30a67777a4522dc579cc9fa7e6 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/guybrush/port_descriptors.c M src/mainboard/google/guybrush/variants/baseboard/Makefile.inc M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c A src/mainboard/google/guybrush/variants/baseboard/variant.c M src/mainboard/google/guybrush/variants/dewatt/variant.c M src/mainboard/google/guybrush/variants/guybrush/variant.c 7 files changed, 67 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/79793/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4ecbaaab5a21c30a67777a4522dc579cc9fa7e6 Gerrit-Change-Number: 79793 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/google/guybrush: Update DXIO descriptor definition
by Jon Murphy (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Jason Nien, Martin Roth. Hello Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79792?usp=email to look at the new patch set (#2). Change subject: mb/google/guybrush: Update DXIO descriptor definition ...................................................................... mb/google/guybrush: Update DXIO descriptor definition Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: I6a61d6561304782de847f6b99c9a73292e12b33f Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/guybrush/port_descriptors.c M src/mainboard/google/guybrush/variants/baseboard/Makefile.inc A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c 5 files changed, 143 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79792/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a61d6561304782de847f6b99c9a73292e12b33f Gerrit-Change-Number: 79792 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/skyrim: Update DDI descriptor definition
by Jon Murphy (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Jason Nien, Martin Roth. Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79793?usp=email ) Change subject: mb/google/skyrim: Update DDI descriptor definition ...................................................................... mb/google/skyrim: Update DDI descriptor definition Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ib4ecbaaab5a21c30a67777a4522dc579cc9fa7e6 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/guybrush/port_descriptors.c M src/mainboard/google/guybrush/variants/baseboard/Makefile.inc M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c A src/mainboard/google/guybrush/variants/baseboard/variant.c M src/mainboard/google/guybrush/variants/dewatt/variant.c M src/mainboard/google/guybrush/variants/guybrush/variant.c 7 files changed, 68 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/79793/1 diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index ea59103..2a636f5 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -7,45 +7,10 @@ #include <soc/platform_descriptors.h> #include <types.h> -static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { - { /* DDI0 - eDP */ - .connector_type = DDI_EDP, - .aux_index = DDI_AUX1, - .hdp_index = DDI_HDP1 - }, - { /* DDI1 - HDMI */ - .connector_type = DDI_HDMI, - .aux_index = DDI_AUX2, - .hdp_index = DDI_HDP2 - }, - { /* DDI2 */ - .connector_type = DDI_UNUSED_TYPE, - .aux_index = DDI_AUX3, - .hdp_index = DDI_HDP3, - }, - { /* DDI3 - DP (type C) */ - .connector_type = DDI_DP, - .aux_index = DDI_AUX3, - .hdp_index = DDI_HDP3, - }, - { /* DDI4 - DP (type C) */ - .connector_type = DDI_DP, - .aux_index = DDI_AUX4, - .hdp_index = DDI_HDP4, - } -}; - -void __weak variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) -{ -} - void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { variant_get_dxio_descriptors(dxio_descs, dxio_num); - variant_update_ddi_descriptors(guybrush_czn_ddi_descriptors); - - *ddi_descs = guybrush_czn_ddi_descriptors; - *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); + variant_get_ddi_descriptors(ddi_descs, ddi_num); } diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc index 014dfd6..40d871f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -6,10 +6,12 @@ romstage-y += gpio.c romstage-y += helpers.c romstage-y += port_descriptors.c +romstage-y += variant.c ramstage-y += gpio.c ramstage-y += helpers.c ramstage-y += port_descriptors.c +ramstage-y += variant.c verstage-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 9b39003..a945f9d 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -35,7 +35,10 @@ bool variant_has_pcie_wwan(void); -void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors); +/* + * This function allows a variant to override ddi descriptors passed to the FSP. + */ +void variant_get_ddi_descriptors(const fsp_ddi_descriptor **ddi_descriptors, size_t *num); /* * This function allows a variant to override dxio descriptors passed to the FSP. @@ -46,4 +49,7 @@ uint8_t variant_sd_aux_reset_gpio(void); void variant_devtree_update(void); + +bool variant_has_hdmi(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c b/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c index b2bea12..bdea910 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c +++ b/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c @@ -23,6 +23,51 @@ [BASEBOARD_DXIO_DUMMY_2] = DUMMY_2_DXIO_DESCRIPTOR, }; +enum baseboard_ddi_port_id { + BASEBOARD_DDI_EDP, + BASEBOARD_DDI_HDMI, + BASEBOARD_DDI_UNUSED, + BASEBOARD_DDI_DP1, + BASEBOARD_DDI_DP2, +}; + +static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { + [BASEBOARD_DDI_EDP] = { + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + [BASEBOARD_DDI_HDMI] = { + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + [BASEBOARD_DDI_UNUSED] = { + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + [BASEBOARD_DDI_DP1] = { + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + [BASEBOARD_DDI_DP2] = { + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } +}; + +__weak void variant_get_ddi_descriptors(const fsp_ddi_descriptor **ddi_descriptors, size_t *num) +{ + if (!variant_has_hdmi()) + guybrush_czn_ddi_descriptors[BASEBOARD_DDI_HDMI].connector_type = DDI_UNUSED_TYPE; + + *ddi_descriptors = guybrush_czn_ddi_descriptors; + *num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); +} + __weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) { /* Get Variant specific SD AUX Reset GPIO */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/variant.c b/src/mainboard/google/guybrush/variants/baseboard/variant.c new file mode 100644 index 0000000..ead29b6 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +__weak bool variant_has_hdmi(void) +{ + return true; +} diff --git a/src/mainboard/google/guybrush/variants/dewatt/variant.c b/src/mainboard/google/guybrush/variants/dewatt/variant.c index a985b05..610e493 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/variant.c +++ b/src/mainboard/google/guybrush/variants/dewatt/variant.c @@ -3,8 +3,7 @@ #include <baseboard/variants.h> #include <amdblocks/cpu.h> -void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) +bool variant_has_hdmi(void) { - if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) - ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; -} + return ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2); +} \ No newline at end of file diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c index 394270c..bbc9d11 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/variant.c +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -16,8 +16,7 @@ return board_id() == 1 ? GPIO_70 : GPIO_69; } -void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) +bool variant_has_hdmi(void) { - if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) - ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; + return ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4ecbaaab5a21c30a67777a4522dc579cc9fa7e6 Gerrit-Change-Number: 79793 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/google/skyrim: Update DXIO descriptor definition
by Jon Murphy (Code Review) 05 Jan '24

05 Jan '24

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79792?usp=email ) Change subject: mb/google/skyrim: Update DXIO descriptor definition ...................................................................... mb/google/skyrim: Update DXIO descriptor definition Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: I6a61d6561304782de847f6b99c9a73292e12b33f Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/guybrush/port_descriptors.c M src/mainboard/google/guybrush/variants/baseboard/Makefile.inc A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c 5 files changed, 143 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79792/1 diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index fc6ccb8..ea59103 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -7,93 +7,6 @@ #include <soc/platform_descriptors.h> #include <types.h> -/* All PCIe Resets are handled in coreboot */ -static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { - { /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = false, - .link_aspm_L1_2 = false, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - .gpio_group_id = GPIO_69, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* WWAN */ - .engine_type = UNUSED_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 2, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(WWAN_DEVFN), - .function_number = PCI_FUNC(WWAN_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* NVME */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 4, - .end_logical_lane = 7, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* Dummy Device */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 11, - .device_number = PCIE_GPP_BRIDGE_2_DEV, - .function_number = PCIE_GPP_2_4_FUNC, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* Dummy Device */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 23, - .device_number = PCIE_GPP_BRIDGE_1_DEV, - .function_number = PCIE_GPP_1_0_FUNC, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - } -}; - static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, @@ -122,10 +35,6 @@ } }; -void __weak variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) -{ -} - void __weak variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) { } @@ -134,23 +43,9 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - /* Get Variant specific SD AUX Reset GPIO */ - guybrush_czn_dxio_descriptors[SD].gpio_group_id = variant_sd_aux_reset_gpio(); - - /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it - is enabled. */ - if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) - guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; - - if (variant_has_pcie_wwan()) - guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; - - variant_update_dxio_descriptors(guybrush_czn_dxio_descriptors); + variant_get_dxio_descriptors(dxio_descs, dxio_num); variant_update_ddi_descriptors(guybrush_czn_ddi_descriptors); - *dxio_descs = guybrush_czn_dxio_descriptors; - *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); - *ddi_descs = guybrush_czn_ddi_descriptors; *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); } diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc index 74d030d..014dfd6 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -3,11 +3,13 @@ bootblock-y += gpio.c bootblock-y += helpers.c -romstage-y += helpers.c romstage-y += gpio.c +romstage-y += helpers.c +romstage-y += port_descriptors.c ramstage-y += gpio.c ramstage-y += helpers.c +ramstage-y += port_descriptors.c verstage-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h new file mode 100644 index 0000000..528e2a9 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h @@ -0,0 +1,93 @@ +#ifndef __BASEBOARD_PORT_DESCRIPTORS_H__ +#define __BASEBOARD_PORT_DESCRIPTORS_H__ + +#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN +#define SD_DEVFN PCIE_GPP_2_1_DEVFN +#define WWAN_DEVFN PCIE_GPP_2_2_DEVFN +#define NVME_DEVFN PCIE_GPP_2_3_DEVFN + +#define WLAN_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = 0, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(WLAN_DEVFN), \ + .function_number = PCI_FUNC(WLAN_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = false, \ + .link_aspm_L1_2 = false, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define SD_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 1, \ + .end_logical_lane = 1, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(SD_DEVFN), \ + .function_number = PCI_FUNC(SD_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ1, \ + .gpio_group_id = GPIO_69, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define WWAN_DXIO_DESCRIPTOR { \ + .engine_type = UNUSED_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 2, \ + .end_logical_lane = 2, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(WWAN_DEVFN), \ + .function_number = PCI_FUNC(WWAN_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define NVME_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 4, \ + .end_logical_lane = 7, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(NVME_DEVFN), \ + .function_number = PCI_FUNC(NVME_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ3, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define DUMMY_1_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 11, \ + .device_number = PCIE_GPP_BRIDGE_2_DEV, \ + .function_number = PCIE_GPP_2_4_FUNC, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ5, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define DUMMY_2_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 23, \ + .device_number = PCIE_GPP_BRIDGE_1_DEV, \ + .function_number = PCIE_GPP_1_0_FUNC, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ6, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} + +#endif //__BASEBOARD_PORT_DESCRIPTORS_H__ diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 9f99b9f..9b39003 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -7,11 +7,6 @@ #include <soc/pci_devs.h> #include <platform_descriptors.h> -#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN -#define SD_DEVFN PCIE_GPP_2_1_DEVFN -#define WWAN_DEVFN PCIE_GPP_2_2_DEVFN -#define NVME_DEVFN PCIE_GPP_2_3_DEVFN - /* This function provides base GPIO configuration table. */ const struct soc_amd_gpio *baseboard_gpio_table(size_t *size); /* @@ -40,15 +35,13 @@ bool variant_has_pcie_wwan(void); -void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors); -enum dxio_port_id { - WLAN, - SD, - WWAN_NVME, - NVME -}; +/* + * This function allows a variant to override dxio descriptors passed to the FSP. + */ +void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, + size_t *num); uint8_t variant_sd_aux_reset_gpio(void); diff --git a/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c b/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c new file mode 100644 index 0000000..b2bea12 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <baseboard/port_descriptors.h> +#include <device/device.h> +#include <soc/platform_descriptors.h> + +enum baseboard_dxio_port_id { + BASEBOARD_DXIO_WLAN, + BASEBOARD_DXIO_SD, + BASEBOARD_DXIO_WWAN_NVME, + BASEBOARD_DXIO_NVME, + BASEBOARD_DXIO_DUMMY_1, + BASEBOARD_DXIO_DUMMY_2, +}; + +static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { + [BASEBOARD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_SD] = SD_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_WWAN_NVME] = WWAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_NVME] = NVME_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_DUMMY_1] = DUMMY_1_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_DUMMY_2] = DUMMY_2_DXIO_DESCRIPTOR, +}; + +__weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) +{ + /* Get Variant specific SD AUX Reset GPIO */ + guybrush_czn_dxio_descriptors[BASEBOARD_DXIO_SD].gpio_group_id = variant_sd_aux_reset_gpio(); + + /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it + is enabled. */ + if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) + guybrush_czn_dxio_descriptors[BASEBOARD_DXIO_WWAN_NVME].engine_type = PCIE_ENGINE; + + if (variant_has_pcie_wwan()) + guybrush_czn_dxio_descriptors[BASEBOARD_DXIO_WWAN_NVME].gpio_group_id = GPIO_18; + + *dxio_descriptor = guybrush_czn_dxio_descriptors; + *num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a61d6561304782de847f6b99c9a73292e12b33f Gerrit-Change-Number: 79792 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/ibm/sbp1: Set FSP loglevel
by Patrick Rudolph (Code Review) 05 Jan '24

05 Jan '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79791?usp=email ) Change subject: mb/ibm/sbp1: Set FSP loglevel ...................................................................... mb/ibm/sbp1: Set FSP loglevel Change-Id: Ia97dbda30f657f0b1568364d712eaea8d134b3b0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ibm/sbp1/romstage.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/79791/1 diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c index f5b081b..5cda689 100644 --- a/src/mainboard/ibm/sbp1/romstage.c +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -279,8 +279,13 @@ /* Determines if warnings are promoted to system level. */ mupd->FspmConfig.promoteWarnings = 0x0; - /* Set FSP debug message to Disable */ - mupd->FspmConfig.serialDebugMsgLvl = 0x0; + if (CONFIG(DEFAULT_CONSOLE_LOGLEVEL_7) || + CONFIG(DEFAULT_CONSOLE_LOGLEVEL_8)) + mupd->FspmConfig.serialDebugMsgLvl = 3; + else if (CONFIG(DEFAULT_CONSOLE_LOGLEVEL_6)) + mupd->FspmConfig.serialDebugMsgLvl = 1; + else + mupd->FspmConfig.serialDebugMsgLvl = 0; /* Force 256MiB MMCONF (Segment0) only */ mupd->FspmConfig.mmCfgSize = 0x2; -- To view, visit https://review.coreboot.org/c/coreboot/+/79791?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia97dbda30f657f0b1568364d712eaea8d134b3b0 Gerrit-Change-Number: 79791 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel: Add config to use S3 over S0ix
by Jakub Czapiga (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun, Tim Crawford. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79631?usp=email ) Change subject: soc/intel: Add config to use S3 over S0ix ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife98166338c5457fb2c7dad81a30e54f487495f6 Gerrit-Change-Number: 79631 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 14:50:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/glinda: Update the maximum CPU threads for glinda
by Felix Held (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Anand Vaikar, Fred Reitberger, Paul Menzel, ritul guru. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79509?usp=email ) Change subject: soc/amd/glinda: Update the maximum CPU threads for glinda ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/glinda/Kconfig: https://review.coreboot.org/c/coreboot/+/79509/comment/7138f096_9a5dddf5 : PS6, Line 243: default 8 if SOC_AMD_GLINDA : default 16 > Also background in the commit message, why there were two different values before would be nice. that was due to glinda starting as a copy of mendocino -- To view, visit https://review.coreboot.org/c/coreboot/+/79509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Gerrit-Change-Number: 79509 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 14:38:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86/include/mode_switch: Add more wrapper functions
by Felix Held (Code Review) 05 Jan '24

05 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79756?usp=email ) Change subject: arch/x86/include/mode_switch: Add more wrapper functions ...................................................................... arch/x86/include/mode_switch: Add more wrapper functions Add a protected mode wrapper function that takes three arguments. This is already supported by the called assembly code. Change-Id: Ia8c91eebae17e4ca27e391454c2d130a71c4c9f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79756 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/mode_switch.h M src/cpu/x86/64bit/mode_switch.S 2 files changed, 31 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/arch/x86/include/mode_switch.h b/src/arch/x86/include/mode_switch.h index 4235db9..54969b2 100644 --- a/src/arch/x86/include/mode_switch.h +++ b/src/arch/x86/include/mode_switch.h @@ -11,10 +11,10 @@ * * The called function has 0-3 arguments and returns an int. */ -int protected_mode_call_3arg(uint32_t func_ptr, - uint32_t opt_arg1, - uint32_t opt_arg2, - uint32_t opt_arg3); +int protected_mode_call_wrapper(uint32_t func_ptr, + uint32_t opt_arg1, + uint32_t opt_arg2, + uint32_t opt_arg3); /* * Drops into protected mode and calls the function, which must have been compiled for x86_32. @@ -25,7 +25,7 @@ */ static inline int protected_mode_call(void *func) { - return protected_mode_call_3arg((uintptr_t)func, 0, 0, 0); + return protected_mode_call_wrapper((uintptr_t)func, 0, 0, 0); } /* @@ -38,7 +38,7 @@ */ static inline int protected_mode_call_1arg(void *func, uint32_t arg1) { - return protected_mode_call_3arg((uintptr_t)func, arg1, 0, 0); + return protected_mode_call_wrapper((uintptr_t)func, arg1, 0, 0); } /* @@ -51,7 +51,21 @@ */ static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) { - return protected_mode_call_3arg((uintptr_t)func, arg1, arg2, 0); + return protected_mode_call_wrapper((uintptr_t)func, arg1, arg2, 0); +} + +/* + * Drops into protected mode and calls the function, which must have been compiled for x86_32. + * After the function returns it enters long mode again. + * The function pointer destination must be below 4GiB in physical memory. + * Only the lower 32bits of the argument are passed to the called function. + * + * The called function has two arguments and returns an int. + */ +static inline int protected_mode_call_3arg(void *func, uint32_t arg1, uint32_t arg2, + uint32_t arg3) +{ + return protected_mode_call_wrapper((uintptr_t)func, arg1, arg2, arg3); } #else static inline int protected_mode_call(void *func) @@ -74,4 +88,12 @@ return doit(arg1, arg2); } + +static inline int protected_mode_call_3arg(void *func, uint32_t arg1, uint32_t arg2, + uint32_t arg3) +{ + int (*doit)(uint32_t arg1, uint32_t arg2, uint32_t arg3) = func; + + return doit(arg1, arg2, arg3); +} #endif diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index f9f784e..c4198f3 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -4,8 +4,8 @@ .text .code64 .section ".text.protected_mode_call", "ax", @progbits - .globl protected_mode_call_3arg -protected_mode_call_3arg: + .globl protected_mode_call_wrapper +protected_mode_call_wrapper: /* Preserve registers */ push %rbp push %rbx -- To view, visit https://review.coreboot.org/c/coreboot/+/79756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8c91eebae17e4ca27e391454c2d130a71c4c9f3 Gerrit-Change-Number: 79756 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: northbridge/intel/sandybridge: Enable x86_64 for mrc.bin
by Felix Held (Code Review) 05 Jan '24

05 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79754?usp=email ) Change subject: northbridge/intel/sandybridge: Enable x86_64 for mrc.bin ...................................................................... northbridge/intel/sandybridge: Enable x86_64 for mrc.bin Enable x86_64 support for MRC.bin: - Add a wrapper function for console printing that calls into long mode to call native do_putchar - Remove Kconfig guard for x86_64 when MRC is being used Tested: Booted Lenovo X220 using mrc.bin under x86_64 and MRC is able to print to the console. Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79754 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/mrc_wrapper.S M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 20 insertions(+), 3 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 10c0ae3..649ef4e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,7 +1,7 @@ config CPU_INTEL_MODEL_206AX bool select ARCH_X86 - select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT + select HAVE_EXP_X86_64_SUPPORT select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/sandybridge/mrc_wrapper.S b/src/northbridge/intel/sandybridge/mrc_wrapper.S index 860526b..d68ce09 100644 --- a/src/northbridge/intel/sandybridge/mrc_wrapper.S +++ b/src/northbridge/intel/sandybridge/mrc_wrapper.S @@ -25,3 +25,13 @@ mov %ebp, %esp popal ret + + /* + * Callback for MRC to print a character on the console. + * As MRC is x86_32 call into long mode and use the x86_64 + * function do_putchar to print to console. + */ + +#include <src/cpu/x86/64bit/prot2long.inc> + +prot2lm_wrapper do_putchar diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index d59aa86..dde5742 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -52,6 +52,7 @@ /* Assembly functions: */ void mrc_wrapper(void *func_ptr, uint32_t arg1); +void __prot2lm_do_putchar(uint8_t byte); static void save_mrc_data(struct pei_data *pei_data) { @@ -154,8 +155,14 @@ system_reset(); } - /* Pass console handler in pei_data */ - pei_data->tx_byte_ptr = (uintptr_t)do_putchar; + /* + * Pass console handler in pei_data. On x86_64 provide a wrapper around + * do_putchar that switches to long mode before calling do_putchar. + */ + if (ENV_X86_64) + pei_data->tx_byte_ptr = (uintptr_t)__prot2lm_do_putchar; + else + pei_data->tx_byte_ptr = (uintptr_t)do_putchar; /* Locate and call UEFI System Agent binary. */ entry = cbfs_map("mrc.bin", NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/79754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Gerrit-Change-Number: 79754 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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