coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3043 discussions

[S] Change in coreboot[main]: soc/intel/apollolake: Create IBB, IBBL and OBB
by Michał Żygowski (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Andrey Petrov, Angel Pons, Sean Rhodes. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65680?usp=email ) Change subject: soc/intel/apollolake: Create IBB, IBBL and OBB ...................................................................... Patch Set 26: (1 comment) Patchset: PS25: > MEU? Manifest Extension Utility? -- To view, visit https://review.coreboot.org/c/coreboot/+/65680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5 Gerrit-Change-Number: 65680 Gerrit-PatchSet: 26 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 09:35:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Use unsigned int for "factory_config"
by Subrata Banik (Code Review) 05 Jan '24

05 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79769?usp=email ) Change subject: vendorcode/google/chromeos: Use unsigned int for "factory_config" ...................................................................... vendorcode/google/chromeos: Use unsigned int for "factory_config" This patch ensures `chromeos_get_factory_config()` returns an unsigned integer value because factory config represents bit-fields to determine the Chromebook Plus branding. Additionally, introduced safety measures to catch future "factory_config" bit-field exhaustion. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79769 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/tpm_factory_config.c 2 files changed, 15 insertions(+), 10 deletions(-) Approvals: Eric Lai: Looks good to me, approved Julius Werner: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 0c5e4f7..a4315c3 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -17,6 +17,8 @@ static inline void reboot_from_watchdog(void) { return; } #endif /* CONFIG_CHROMEOS */ +#define UNDEFINED_FACTORY_CONFIG ~((uint64_t)0) + /** * Perform any platform specific actions required prior to resetting the Cr50. * Defined as weak function in cr50_enable_update.c @@ -29,9 +31,9 @@ /* * The factory config space is a one-time programmable info page. * For the unprovisioned one, the read will be 0x0. - * Return `-1` in case of error. + * Return "UNDEFINED_FACTORY_CONFIG" in case of error. */ -int64_t chromeos_get_factory_config(void); +uint64_t chromeos_get_factory_config(void); /* * Determines whether a ChromeOS device is branded as a Chromebook Plus * based on specific bit flags: diff --git a/src/vendorcode/google/chromeos/tpm_factory_config.c b/src/vendorcode/google/chromeos/tpm_factory_config.c index 4f8801a..44fb9f0 100644 --- a/src/vendorcode/google/chromeos/tpm_factory_config.c +++ b/src/vendorcode/google/chromeos/tpm_factory_config.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <console/console.h> #include <security/tpm/tss.h> #include <types.h> @@ -9,11 +10,11 @@ #define CHROMEBOOK_PLUS_SOFT_BRANDED BIT(0) #define CHROMEBOOK_PLUS_DEVICE (CHROMEBOOK_PLUS_HARD_BRANDED | CHROMEBOOK_PLUS_SOFT_BRANDED) -int64_t chromeos_get_factory_config(void) +uint64_t chromeos_get_factory_config(void) { - static int64_t factory_config = -1; + static uint64_t factory_config = UNDEFINED_FACTORY_CONFIG; - if (factory_config >= 0) + if (factory_config != UNDEFINED_FACTORY_CONFIG) return factory_config; /* Initialize TPM driver. */ @@ -21,17 +22,19 @@ if (rc != TPM_SUCCESS) { printk(BIOS_ERR, "%s:%d - tlcl_lib_init() failed: %#x\n", __func__, __LINE__, rc); - return -1; + return UNDEFINED_FACTORY_CONFIG; } - rc = tlcl_cr50_get_factory_config((uint64_t *)&factory_config); + rc = tlcl_cr50_get_factory_config(&factory_config); if (rc != TPM_SUCCESS) { printk(BIOS_ERR, "%s:%d - tlcl_cr50_get_factory_config() failed: %#x\n", __func__, __LINE__, rc); - return -1; + return UNDEFINED_FACTORY_CONFIG; } + assert(factory_config != UNDEFINED_FACTORY_CONFIG); + return factory_config; } @@ -48,9 +51,9 @@ */ bool chromeos_device_branded_plus(void) { - int64_t factory_config = chromeos_get_factory_config(); + uint64_t factory_config = chromeos_get_factory_config(); - if (factory_config < 0) + if (factory_config == UNDEFINED_FACTORY_CONFIG) return false; return factory_config & CHROMEBOOK_PLUS_DEVICE; -- To view, visit https://review.coreboot.org/c/coreboot/+/79769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0 Gerrit-Change-Number: 79769 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size fo...
by Anand Vaikar (Code Review) 05 Jan '24

05 Jan '24

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79832?usp=email ) Change subject: src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size for glinda ...................................................................... src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size for glinda The PCIE MMCONFIG base address value and size is updated correctly to access the PCIE config space registers. TEST=Verified that PCIE enumeration takes place in boot log and config space registers are accessible. Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/soc/amd/glinda/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79832/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a3b0ea6..dd362e0 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -233,10 +233,10 @@ default "apu/amdfw" config ECAM_MMCONF_BASE_ADDRESS - default 0xF8000000 + default 0xE0000000 config ECAM_MMCONF_BUS_NUMBER - default 64 + default 256 config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/79832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Gerrit-Change-Number: 79832 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Use unsigned int for "factory_config"
by Kapil Porwal (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Shelley Chen, Subrata Banik, Tim Van Patten. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79769?usp=email ) Change subject: vendorcode/google/chromeos: Use unsigned int for "factory_config" ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0 Gerrit-Change-Number: 79769 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 08:59:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/dedede/var/metaknight:Add fw_config probe for multi codec a...
by Morris Hsu (Code Review) 05 Jan '24

05 Jan '24

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79831?usp=email ) Change subject: mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier ...................................................................... mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:183305590 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/79831/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index e01dee9..3337f6a 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 49 51 + option AUDIO_CODEC_RT5682 0 + option AUDIO_CODEC_ALC5682I_VS 1 + end +end + chip soc/intel/jasperlake # USB Port Configuration @@ -247,7 +254,22 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_RT5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end chip drivers/i2c/generic register "hid" = ""10EC1015"" -- To view, visit https://review.coreboot.org/c/coreboot/+/79831?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad Gerrit-Change-Number: 79831 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/apollolake: Create IBB, IBBL and OBB
by Sean Rhodes (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Andrey Petrov, Angel Pons, Michał Żygowski. Hello Andrey Petrov, Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65680?usp=email to look at the new patch set (#26). Change subject: soc/intel/apollolake: Create IBB, IBBL and OBB ...................................................................... soc/intel/apollolake: Create IBB, IBBL and OBB coreboot's method of creating IFWI is to modify an existing IFWI images by deleting the IBB, replacing the IBBL with the bootblock and everything else is put in the OBB. This poses a problem when using Intel's FIT or technologies such as Boot Guard. The main problem is that the IBB is never verified by the CSE or copied from SRAM to CAR, so the CSE cannot complete BUP and stays in recovery mode. The vast majority of the stages in Apollolake's Secure Boot flow is not met using this method (Intel document number 597827 summarizes these steps). This patch series is based on the principles of a patch from Brenton Dong (CB:17064) creates an IBBL, IBB and OBB binaries with the correct functions to complete the Secure Boot flow. This is to copy the IBB from SRAM using the CSE's Ring Buffer Protocol. These binaries can then be used by FIT or coreboot's existing method of hacking IFWI together (IFWI_STITCH) via IFWITOOL. If it is the latter and Boot Guard is enabled, the hashes for IFWI and "ibb+obb" must be recreated. Whilst this option doesn't form a complete image, the components it builds will work as Intel intended them to once stitched correctly into an IFWI image. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5 --- M src/soc/intel/apollolake/Makefile.inc M src/southbridge/intel/common/firmware/Makefile.inc 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/65680/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/65680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5 Gerrit-Change-Number: 65680 Gerrit-PatchSet: 26 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/apollolake: Create IBB, IBBL and OBB
by Sean Rhodes (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Andrey Petrov, Angel Pons, Michał Żygowski. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65680?usp=email ) Change subject: soc/intel/apollolake: Create IBB, IBBL and OBB ...................................................................... Patch Set 25: (1 comment) Patchset: PS25: > It looks like I won't be able to boot with IBB loading via CSE/TXE unless I make use of the MEU and […] MEU? -- To view, visit https://review.coreboot.org/c/coreboot/+/65680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5 Gerrit-Change-Number: 65680 Gerrit-PatchSet: 25 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 08:49:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324 dr...
by Robert Chen (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Paul Menzel, Shawn Ku, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Shawn Ku, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79724?usp=email to look at the new patch set (#6). Change subject: mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324 driver ...................................................................... mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324 driver Since DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER value on dedede cannot meet DRIVERS_I2C_SX9324 on nissa, need to update the tuning value. Update proximity sensor fine tune value with quandiso EVT machine. BUG=b:314550601 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and verify p-sensor watch 'cat /sys/bus/iio/devices/iio:device*/*raw' Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/quandiso/overridetree.cb 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/79724/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Gerrit-Change-Number: 79724 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324 dr...
by Robert Chen (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Paul Menzel, Shawn Ku, Subrata Banik. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79724?usp=email ) Change subject: mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324 driver ...................................................................... Patch Set 5: (2 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/79724/comment/d7f98040_23815403 : PS3, Line 9: Update proximity sensor tuning value from SX9324ICSTRT schematic. > Please update the commit message accordingly. Done Commit Message: https://review.coreboot.org/c/coreboot/+/79724/comment/de1dda20_69c4b497 : PS4, Line 12: nissa,need > Please add a space after the comma. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Gerrit-Change-Number: 79724 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Jan 2024 07:53:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF compo...
by Anand Vaikar (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Nikolai Vyssotski, ritul guru. Hello Felix Held, Fred Reitberger, Nikolai Vyssotski, ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79830?usp=email to look at the new patch set (#2). Change subject: soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF component ...................................................................... soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF component The IOHUBS0 is a data fabric component which has a fabric id value specific to SOC. Updated the fabric id for glinda SOC. TEST=Verified that fabric ID is programmed correctly in boot logs. Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/soc/amd/glinda/include/soc/data_fabric.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79830/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Gerrit-Change-Number: 79830 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2024