coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF compo...
by Anand Vaikar (Code Review) 05 Jan '24

05 Jan '24

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79830?usp=email ) Change subject: soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF component ...................................................................... soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF component The IOHUBS0 is a data fabric component which has a fabric id value specific to SOC. Updated the fabric id for glinda SOC. TEST=Verified that fabric ID is programmed correctly in boot logs. Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/soc/amd/glinda/include/soc/data_fabric.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79830/1 diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 345702f..cf91c0a 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -6,7 +6,7 @@ #include <amdblocks/data_fabric_defs.h> #include <types.h> -#define IOMS0_FABRIC_ID 15 +#define IOMS0_FABRIC_ID 0x14 #define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) #define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) -- To view, visit https://review.coreboot.org/c/coreboot/+/79830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Gerrit-Change-Number: 79830 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: enable external shared SPI config
by Deepti Deshatty (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Balaji Manigandan, Eric Lai, Krishna P Bhat D, Subrata Banik, Vijay P Hiremath. Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79824?usp=email ) Change subject: mb/intel/mtlrvp: enable external shared SPI config ...................................................................... Patch Set 1: (1 comment) File src/mainboard/intel/mtlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/79824/comment/94fd25bf_264f2a03 : PS1, Line 112: help > CL:79211 introduces the new config and this CL enables it. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I462c34c5adaefa37c652de293152243c58bad7c5 Gerrit-Change-Number: 79824 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 07:02:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/mipi: Add support for BOE_NV110WUM_L60 panel
by Ruihai Zhou (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78956?usp=email ) Change subject: drivers/mipi: Add support for BOE_NV110WUM_L60 panel ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78956/comment/ab5980d6_ff1365ef : PS7, Line 10: > Please also add the panel datasheet to the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Gerrit-Change-Number: 78956 Gerrit-PatchSet: 8 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 06:00:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/mipi: Add support for BOE_NV110WUM_L60 panel
by Ruihai Zhou (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Ruihai Zhou, Yu-Ping Wu. Hello Yidi Lin, Yu-Ping Wu, build bot (Jenkins), cong yang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78956?usp=email to look at the new patch set (#8). Change subject: drivers/mipi: Add support for BOE_NV110WUM_L60 panel ...................................................................... drivers/mipi: Add support for BOE_NV110WUM_L60 panel Add BOE_NV110WUM_L60 serializable data to CBFS. Datasheet: B5NV110WUM-L60 V5.0Product SpecificationRev.P0 BUG=b:308968270 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> --- M src/drivers/mipi/Kconfig M src/drivers/mipi/Makefile.inc A src/drivers/mipi/panel-BOE_NV110WUM_L60.c 3 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/78956/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Gerrit-Change-Number: 78956 Gerrit-PatchSet: 8 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: util/lint: Remove the extra `\` in lint-stable-003-whitespace
by Ruihai Zhou (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Martin L Roth, Yidi Lin, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79782?usp=email ) Change subject: util/lint: Remove the extra `\` in lint-stable-003-whitespace ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79782/comment/94e20bfb_75a3b3da : PS3, Line 9: the extra `\` : is unnecessary. > the extra `\` after `\. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Gerrit-Change-Number: 79782 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 05:56:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/lint: Remove the extra `\` in lint-stable-003-whitespace
by Ruihai Zhou (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Martin L Roth, Ruihai Zhou, Yu-Ping Wu. Hello Martin L Roth, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), cong yang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79782?usp=email to look at the new patch set (#4). Change subject: util/lint: Remove the extra `\` in lint-stable-003-whitespace ...................................................................... util/lint: Remove the extra `\` in lint-stable-003-whitespace A following error occurred when I commit, it seems that the extra `\` after `\.md$` is unnecessary. File Binary file src/mainboard/google/guybrush/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/skyrim/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/zork/data.apcb matches has lines ending with whitespace. test failed Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/79782/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Gerrit-Change-Number: 79782 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85
by Name of user not set (Code Review) 05 Jan '24

05 Jan '24

srinivas.kulkarni(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79829?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85 ...................................................................... vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85 Update header files for FSP for Meteor Lake platform to version 3471_85, previous version being 3424_88. FSPM: 1. Add 'DisplayGpioPinMux' UPDs BUG=b:318772151 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/79829/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index 1ac6ef8..d8daacc 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -926,9 +926,12 @@ **/ UINT8 DdiPort4Ddc; -/** Offset 0x02BE - Reserved +/** Offset 0x02BE - GPIO PIN MUX to choose between GPP_SA and GPP_SD Group. + Default will be 0 for each Display PIN Mux which is GPP_SA Group. (0 = SA GROUP, + 1 = SD GROUP). BIT0 - EDP VDDEN, BIT1 - EDP BKLTEN, BIT2 - EDP BKLTCTRL, BIT3 + - DDI-A, BIT4 - DDI-1/HPD1, BIT5 - DDI-2/HPD2, BIT6 - DDI-3/HPD3, BIT7 - DDI-4/HPD4 **/ - UINT8 Reserved16[18]; + UINT8 DisplayGpioPinMux; /** Offset 0x02D0 - Per-core HT Disable Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, -- To view, visit https://review.coreboot.org/c/coreboot/+/79829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Gerrit-Change-Number: 79829 Gerrit-PatchSet: 1 Gerrit-Owner: srinivas.kulkarni(a)intel.com Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: util/ifdtool: Add support for extended region read/write access
by Subrata Banik (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Krishna P Bhat D, Reka Norman, Stefan Reinauer. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79790?usp=email ) Change subject: util/ifdtool: Add support for extended region read/write access ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa43524d91c399a996ade56f2f613b4110a44aad Gerrit-Change-Number: 79790 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 05:14:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: util/ifdtool: Add support for disabling GPR0
by Subrata Banik (Code Review) 05 Jan '24

05 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79788?usp=email ) Change subject: util/ifdtool: Add support for disabling GPR0 ...................................................................... util/ifdtool: Add support for disabling GPR0 On ChromeOS devices with updateable CSE firmware, the GPR0 (Global Protected Range) register is used to ensure the CSE RO is write protected even when the FLMSTR-based protection is temporarily disabled by coreboot to allow updating the CSE RW. For more details see Documentation/soc/intel/cse_fw_update/cse_fw_update.md Therefore to allow modifying the CSE firmware from the CPU, the descriptor must have both the FLMSTR-based protection disabled (which can be done using ifdtool --unlock), and GPR0 disabled. Add an ifdtool option for disabling GPR0. For now I've added support for all platforms for which I have the SPI programming guide. Support for more platforms can be added in the future if needed. BUG=b:270275115 TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked craask image, check the GPR0 field is set to 0. Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/ifdtool/ifdtool.c 1 file changed, 47 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 43451b1..7d69bcf 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1497,6 +1497,39 @@ write_image(filename, image, size); } +static void disable_gpr0(const char *filename, char *image, int size) +{ + struct fpsba *fpsba = find_fpsba(image, size); + if (!fpsba) + exit(EXIT_FAILURE); + + /* Offset expressed as number of 32-bit fields from FPSBA */ + uint32_t gpr0_offset; + switch (platform) { + case PLATFORM_CNL: + gpr0_offset = 0x10; + break; + case PLATFORM_JSL: + gpr0_offset = 0x12; + break; + case PLATFORM_TGL: + case PLATFORM_ADL: + gpr0_offset = 0x15; + break; + case PLATFORM_MTL: + gpr0_offset = 0x40; + break; + default: + fprintf(stderr, "Disabling GPR0 not supported on this platform\n"); + exit(EXIT_FAILURE); + } + + /* 0 means GPR0 protection is disabled */ + fpsba->pchstrp[gpr0_offset] = 0; + + write_image(filename, image, size); +} + static void set_pchstrap(struct fpsba *fpsba, const struct fdbar *fdb, const int strap, const unsigned int value) { @@ -1836,6 +1869,7 @@ " -l | --lock Lock firmware descriptor and ME region\n" " -r | --read Enable CPU/BIOS read access for ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" + " -g | --gpr0-disable Disable GPR0 (Global Protected Range) register\n" " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" " bits to disable ME\n" " -p | --platform Add platform-specific quirks\n" @@ -1869,6 +1903,7 @@ int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; + int mode_gpr0_disable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; char *new_filename = NULL; @@ -1894,6 +1929,7 @@ {"lock", 0, NULL, 'l'}, {"read", 0, NULL, 'r'}, {"unlock", 0, NULL, 'u'}, + {"gpr0-disable", 0, NULL, 'g'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, {"platform", 0, NULL, 'p'}, @@ -1903,7 +1939,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:elruvth?", + while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:elrugvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -2106,6 +2142,9 @@ exit(EXIT_FAILURE); } break; + case 'g': + mode_gpr0_disable = 1; + break; case 'p': if (!strcmp(optarg, "aplk")) { platform = PLATFORM_APL; @@ -2158,7 +2197,8 @@ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | - mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) { + mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + + mode_gpr0_disable) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); @@ -2166,7 +2206,8 @@ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + - mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) { + mode_locked + mode_unlocked + mode_density + mode_altmedisable + + mode_validate + mode_gpr0_disable) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); @@ -2263,6 +2304,9 @@ if (mode_unlocked) unlock_descriptor(new_filename, image, size); + if (mode_gpr0_disable) + disable_gpr0(new_filename, image, size); + if (mode_setstrap) { struct fpsba *fpsba = find_fpsba(image, size); const struct fdbar *fdb = find_fd(image, size); -- To view, visit https://review.coreboot.org/c/coreboot/+/79788?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Gerrit-Change-Number: 79788 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: drivers/mipi: Add support for BOE_NV110WUM_L60 panel
by Yidi Lin (Code Review) 05 Jan '24

05 Jan '24

Attention is currently required from: Ruihai Zhou, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78956?usp=email ) Change subject: drivers/mipi: Add support for BOE_NV110WUM_L60 panel ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78956/comment/25eab14a_c4f8610b : PS7, Line 10: Please also add the panel datasheet to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/78956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Gerrit-Change-Number: 78956 Gerrit-PatchSet: 7 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 05 Jan 2024 04:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2024