coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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3043 discussions

[S] Change in coreboot[main]: mb/google/byra/var/*: Set WLAN device type back to pci
by Matt DeVillier (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: David Ruth, Eric Lai, Nick Vaccaro, Paul Menzel, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79794?usp=email ) Change subject: mb/google/byra/var/*: Set WLAN device type back to pci ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I'm having difficulty verifying that this change doesn't introduce the same problem. […] I'm on the road for the next week so wouldn't be able to retest until I get back home, so go ahead and revert this and I'll worry about the PEP/LPI part later on -- To view, visit https://review.coreboot.org/c/coreboot/+/79794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5dad9deb040c8cb0c507e11726f0ba44ccb2909 Gerrit-Change-Number: 79794 Gerrit-PatchSet: 1 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Jan 2024 02:51:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Ruth <druth(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi camera
by Weimin Wu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79802?usp=email ) Change subject: mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi camera ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/anraggar/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79802/comment/ef03d024_f2bbb204 : PS1, Line 4: option UF_1080P 1 > why add the field you don't use? I just list all bit define for Camera field in Anraggar. -- To view, visit https://review.coreboot.org/c/coreboot/+/79802?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a Gerrit-Change-Number: 79802 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Jan 2024 02:30:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

1 0

[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 17: (5 comments) Patchset: PS17: Tested and revised for ArcherCity CRB (SPR-XCC) P.S. SPR has different IOAT configs. SPR-XCC presents 3 accelerators per each IOAT stack. SPR-MCC presents 5 accelerators per each IOAT stack. Revised the codes to adapt both. Points checked: 1. IOAT domains are created and scanned. 2. DPRs are configured for each IOAT domain. 3. IOAT resources are assigned by coreboot and reused by LinuxBoot. Logs: [0m[DEBUG] DOMAIN: 0000 enabled[0m [0m[DEBUG] DOMAIN: 0001 enabled[0m [0m[DEBUG] DOMAIN: 0002 enabled[0m [0m[DEBUG] DOMAIN: 0003 enabled[0m [0m[DEBUG] DOMAIN: 0120 enabled[0m [0m[DEBUG] DOMAIN: 0122 enabled[0m [0m[DEBUG] DOMAIN: 011f enabled[0m [0m[DEBUG] DOMAIN: 0125 enabled[0m [0m[DEBUG] DOMAIN: 0127 enabled[0m [0m[DEBUG] DOMAIN: 0124 enabled[0m [0m[DEBUG] DOMAIN: 012a enabled[0m [0m[DEBUG] DOMAIN: 012c enabled[0m [0m[DEBUG] DOMAIN: 0129 enabled[0m [0m[DEBUG] DOMAIN: 012f enabled[0m [0m[DEBUG] DOMAIN: 0131 enabled[0m [0m[DEBUG] DOMAIN: 012e enabled[0m [0m[DEBUG] DOMAIN: 0120 scanning...[0m [0m[DEBUG] PCI: pci_scan_bus for bus e8[0m [0m[DEBUG] scan_bus: bus DOMAIN: 0120 finished in 4 msecs[0m [0m[DEBUG] DOMAIN: 0122 scanning...[0m [0m[DEBUG] PCI: pci_scan_bus for bus ea[0m [0m[DEBUG] scan_bus: bus DOMAIN: 0122 finished in 4 msecs[0m [0m[DEBUG] DOMAIN: 011f scanning...[0m [0m[DEBUG] PCI: pci_scan_bus for bus e7[0m [0m[SPEW ] PCI: e7:00.0 [8086/0000] ops[0m [0m[DEBUG] PCI: e7:00.0 [8086/09a2] enabled[0m [0m[DEBUG] PCI: e7:00.1 [8086/09a4] enabled[0m [0m[DEBUG] PCI: e7:00.2 [8086/09a3] enabled[0m [0m[DEBUG] PCI: e7:00.3 [8086/09a5] enabled[0m [0m[SPEW ] PCI: e7:00.4 [8086/0000] ops[0m [0m[DEBUG] PCI: e7:00.4 [8086/0b23] enabled[0m [0m[DEBUG] PCI: e7:01.0 [8086/0b25] enabled[0m [0m[DEBUG] PCI: e7:02.0 [8086/0cfe] enabled[0m [0m[DEBUG] PCI: e7:03.0 [8086/09a6] enabled[0m [0m[DEBUG] PCI: e7:03.1 [8086/09a7] enabled[0m [0m[DEBUG] PCI: e7:03.2 [8086/09a8] enabled[0m [0m[DEBUG] scan_bus: bus DOMAIN: 011f finished in 63 msecs[0m [0m[DEBUG] DOMAIN: 0120[0m [0m[SPEW ] DOMAIN: 0120 resource base 0 size 0 align 0 gran 0 limit ffffffffffffffff flags 40000200 index 0[0m [0m[SPEW ] DOMAIN: 0120 resource base 204000000000 size 100000000 align 0 gran 0 limit 2040ffffffff flags 40000200 index 1[0m [0m[DEBUG] DOMAIN: 0122[0m [0m[SPEW ] DOMAIN: 0122 resource base 0 size 0 align 0 gran 0 limit ffffffffffffffff flags 40000200 index 0[0m [0m[SPEW ] DOMAIN: 0122 resource base 204100000000 size 400000000 align 0 gran 0 limit 2044ffffffff flags 40000200 index 1[0m [0m[DEBUG] DOMAIN: 011f child on link 0 PCI: e7:00.0[0m [0m[SPEW ] DOMAIN: 011f resource base f9800000 size 800000 align 0 gran 0 limit f9ffffff flags 40000200 index 0[0m [0m[SPEW ] DOMAIN: 011f resource base 204a00000000 size 600000000 align 0 gran 0 limit 204fffffffff flags 40000200 index 1[0m [0m[DEBUG] PCI: e7:00.0[0m [0m[DEBUG] PCI: e7:00.1[0m [0m[DEBUG] PCI: e7:00.2[0m [0m[DEBUG] PCI: e7:00.3[0m [0m[DEBUG] PCI: e7:00.4[0m [0m[DEBUG] PCI: e7:01.0[0m [0m[SPEW ] PCI: e7:01.0 resource base 204ffffb0000 size 10000 align 16 gran 16 limit 204ffffbffff flags 60001201 index 10[0m [0m[SPEW ] PCI: e7:01.0 resource base 204ffffe0000 size 20000 align 17 gran 17 limit 204fffffffff flags 60001201 index 18[0m [0m[DEBUG] PCI: e7:02.0[0m [0m[SPEW ] PCI: e7:02.0 resource base 204ffffa0000 size 10000 align 16 gran 16 limit 204ffffaffff flags 60001201 index 10[0m [0m[SPEW ] PCI: e7:02.0 resource base 204ffffc0000 size 20000 align 17 gran 17 limit 204ffffdffff flags 60001201 index 18[0m [0m[DEBUG] PCI: e7:03.0[0m [0m[SPEW ] PCI: e7:03.0 resource base f9f00000 size 100000 align 20 gran 20 limit f9ffffff flags 60000200 index 10[0m [0m[DEBUG] PCI: e7:03.1[0m [0m[SPEW ] PCI: e7:03.1 resource base f9dbe000 size 2000 align 13 gran 13 limit f9dbffff flags 60000200 index 10[0m [0m[SPEW ] PCI: e7:03.1 resource base f9dc0000 size 40000 align 18 gran 18 limit f9dfffff flags 60000200 index 14[0m [0m[DEBUG] PCI: e7:03.2[0m [0m[SPEW ] PCI: e7:03.2 resource base f9e00000 size 100000 align 20 gran 20 limit f9efffff flags 60000200 index 10[0m [7m[ERROR] configure_dpr for PCI: e7:00.0[0m [0m[SPEW ] <null> read_resources bus 231 link: 0 done[0m [0m[SPEW ] <null> read_resources bus 237 link: 0[0m [0m[SPEW ] <null> read_resources bus 237 link: 0 done[0m [0m[SPEW ] <null> read_resources bus 239 link: 0[0m [0m[SPEW ] <null> read_resources bus 239 link: 0 done[0m [0m[SPEW ] <null> read_resources bus 236 link: 0[0m PCI host bridge to bus 0000:e7 pci_bus 0000:e7: root bus resource [mem 0xf9800000-0xf9ffffff window] pci_bus 0000:e7: root bus resource [mem 0x204a00000000-0x204fffffffff window] pci_bus 0000:e7: root bus resource [bus e7] pci 0000:e7:00.0: [8086:09a2] type 00 class 0x088000 pci 0000:e7:00.1: [8086:09a4] type 00 class 0x088000 pci 0000:e7:00.2: [8086:09a3] type 00 class 0x088000 pci 0000:e7:00.3: [8086:09a5] type 00 class 0x088000 pci 0000:e7:00.4: [8086:0b23] type 00 class 0x080700 pci 0000:e7:01.0: [8086:0b25] type 00 class 0x088000 pci 0000:e7:01.0: reg 0x10: [mem 0x204ffffb0000-0x204ffffbffff 64bit pref] pci 0000:e7:01.0: reg 0x18: [mem 0x204ffffe0000-0x204fffffffff 64bit pref] pci 0000:e7:02.0: [8086:0cfe] type 00 class 0x088000 pci 0000:e7:02.0: reg 0x10: [mem 0x204ffffa0000-0x204ffffaffff 64bit pref] pci 0000:e7:02.0: reg 0x18: [mem 0x204ffffc0000-0x204ffffdffff 64bit pref] pci 0000:e7:03.0: [8086:09a6] type 00 class 0x088000 pci 0000:e7:03.0: reg 0x10: [mem 0xf9f00000-0xf9ffffff] pci 0000:e7:03.1: [8086:09a7] type 00 class 0x088000 pci 0000:e7:03.1: reg 0x10: [mem 0xf9dbe000-0xf9dbffff] pci 0000:e7:03.1: reg 0x14: [mem 0xf9dc0000-0xf9dfffff] pci 0000:e7:03.2: [8086:09a8] type 00 class 0x088000 pci 0000:e7:03.2: reg 0x10: [mem 0xf9e00000-0xf9efffff] ACPI: PCI Root Bridge [PM08] (domain 0000 [bus e8-e9]) acpi PNP0A08:07: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] acpi PNP0A08:07: PCIe port services disabled; not requesting _OSC control PCI host bridge to bus 0000:e8 pci_bus 0000:e8: root bus resource [mem 0x204000000000-0x2040ffffffff window] pci_bus 0000:e8: root bus resource [bus e8-e9] ACPI: PCI Root Bridge [HQ08] (domain 0000 [bus ea-eb]) acpi PNP0A08:08: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] acpi PNP0A08:08: PCIe port services disabled; not requesting _OSC control PCI host bridge to bus 0000:ea pci_bus 0000:ea: root bus resource [mem 0x204100000000-0x2044ffffffff window] pci_bus 0000:ea: root bus resource [bus ea-eb] pci_bus 0000:e7: resource 4 [mem 0xf9800000-0xf9ffffff window] pci_bus 0000:e7: resource 5 [mem 0x204a00000000-0x204fffffffff window] pci_bus 0000:e8: resource 4 [mem 0x204000000000-0x2040ffffffff window] pci_bus 0000:ea: resource 4 [mem 0x204100000000-0x2044ffffffff window] File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/78327/comment/4f2327a2_e1809bad : PS14, Line 73: const unsigned int domain_base = MAX_SOCKET * MAX_LOGIC_IIO_STACK; > I decided to simply add the bus number on top of this. We could also […] From debug experience, using leading bus ID as domain ID would be more straightforward, which could be addressed in later patches. This patch is already quite large and let us merge it first if no opens :) File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/78327/comment/77a08960_b5d627d5 : PS17, Line 50: bus->max_subordinate = bus_limit; each domain will own 2 busses instead of 1. https://review.coreboot.org/c/coreboot/+/78327/comment/f0760eb4_f3df0282 : PS17, Line 109: create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit); Make CPM1 and HQM1 optional on 3 accelerator SKUs where smaller bus range is provided. P.S. Our test is fulfilled on 3 accelerator SKU. File src/soc/intel/xeon_sp/spr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/78327/comment/e5b30708_e3a0a567 : PS17, Line 254: to review -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 09 Jan 2024 02:27:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Shuo Liu has uploaded a new patch set (#17) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... soc/intel/xeon_sp: Redesign resource allocation The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/chip.c A src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 17 files changed, 260 insertions(+), 531 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allocate resources above 4G
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Nico Huber, Paul Menzel, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79058?usp=email ) Change subject: soc/intel/xeon_sp: Allocate resources above 4G ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79058?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Gerrit-Change-Number: 79058 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 09 Jan 2024 01:39:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Shuo Liu has uploaded a new patch set (#16) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... soc/intel/xeon_sp: Redesign resource allocation The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/chip.c A src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 17 files changed, 259 insertions(+), 531 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allocate resources above 4G
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Nico Huber, Paul Menzel, Shuo Liu, Tim Chu. Shuo Liu has uploaded a new patch set (#10) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/79058?usp=email ) Change subject: soc/intel/xeon_sp: Allocate resources above 4G ...................................................................... soc/intel/xeon_sp: Allocate resources above 4G This makes sure that prefetchable mem64 memory gets allocated above 4G which allows non prefetchable resources to be allocated in the tight window below 4G. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79058/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/79058?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Gerrit-Change-Number: 79058 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: device/Kconfig: Add an option to allocate above 4G by default
by Shuo Liu (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Jincheng Li, Nico Huber, Paul Menzel. Shuo Liu has uploaded a new patch set (#16) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78331?usp=email ) Change subject: device/Kconfig: Add an option to allocate above 4G by default ...................................................................... device/Kconfig: Add an option to allocate above 4G by default TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f --- M src/device/Kconfig M src/device/resource_allocator_v4.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78331/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/78331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Gerrit-Change-Number: 78331 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

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