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Change subject: mb/google/brox: Set up FW_CONFIG
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79854/comment/116e6363_283c61e2 :
PS2, Line 10: making
Imperative mood: make
https://review.coreboot.org/c/coreboot/+/79854/comment/3d9cb535_22e7a2f3 :
PS2, Line 11: moving
move
https://review.coreboot.org/c/coreboot/+/79854/comment/dfbd7efa_770c2948 :
PS2, Line 11: Also, moving the storage devices to brox
: overridetree.cb as they are specific to this board.
A separate commit would be nice.
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Change subject: mb/google/brox: Disable package c state demotion
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79855/comment/f1e324b4_ffc00853 :
PS2, Line 7: Disable package c state demotion
… unsupported on RPL
https://review.coreboot.org/c/coreboot/+/79855/comment/f1752210_9a750f60 :
PS2, Line 11: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c',
: line 1066
Maybe also describe, what that assertion checks, and why it’s there.
https://review.coreboot.org/c/coreboot/+/79855/comment/b4062e09_45e4e037 :
PS2, Line 11: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c',
: line 1066
I’d put it in one line and indent it with four spaces.
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Change subject: mb/google/brox: Disable package c state demotion
......................................................................
mb/google/brox: Disable package c state demotion
This needs to be disabled for RPL otherwise we'll hit the assertion:
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c',
line 1066
BUG=b:311450057,b:300690448
BRANCH=None
TEST=Tested that we didn't hit this assertion on the device after this
change
Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79855/2
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Change subject: mb/google/brox: Disable package c state demotion
......................................................................
mb/google/brox: Disable package c state demotion
This needs to be disabled for RPL otherwise we'll hit the assertion:
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066
BUG=b:311450057,b:300690448
BRANCH=None
TEST=Tested that we didn't hit this assertion on the device after this
change
Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79855/1
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index 23db754..552164a 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -14,6 +14,10 @@
# S0ix enable
register "s0ix_enable" = "1"
+ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues
+ # seen on J0 and Q0 SKUs
+ register "disable_package_c_state_demotion" = "1"
+
# DPTF enable
register "dptf_enable" = "1"
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Change subject: mb/google/brox: Set up FW_CONFIG
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brox/variants/brox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79854/comment/0e46292a_ecfdc4bb :
PS1, Line 8: option STORAGE_UFS 0
If you think emmc might be added later, might be better to make this
field STORAGE 2 3
option STORAGE_UNKNOWN 0
option STORAGE_UFS 1
option STORAGE_NVME 2
https://review.coreboot.org/c/coreboot/+/79854/comment/b4994f70_637ed23f :
PS1, Line 11: end
1) It will likely need a field for WiFi Device (not sure if kernel will need a field for WLAN type and/or WLAN interface), I guess it could have a lookup table to get device and then determine what the WLAN type is from there, might want to ask kernel folks what they want / need).
2) add field for AUDIO_CODEC (right now, only 1 will be defined, but that list will likely grow)
3) maybe add field for USB_SENSOR to indicate camera used
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Change subject: mb/google/brox: Set up FW_CONFIG
......................................................................
mb/google/brox: Set up FW_CONFIG
Brox project has FW_CONFIG bits already set up in the project file for
the retimer and for storage, so making sure that the brox device tree
matches those settings. Also, moving the storage devices to brox
overridetree.cb as they are specific to this board.
BUG=b:311450057,b:300690448
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
will check if this helps detect the storage device in the factory
Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
M src/mainboard/google/brox/variants/brox/overridetree.cb
2 files changed, 31 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79854/1
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index 23db754..c1c561b 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -173,21 +173,6 @@
end
device ref heci1 on end
device ref sata on end
- device ref pcie4_0 on
- # Enable CPU PCIE RP 1 using CLK 3
- register "cpu_pcie_rp[CPU_RP(1)]" = "{
- .clk_req = 3,
- .clk_src = 3,
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
- }"
- end
- device ref ish on
- chip drivers/intel/ish
- register "add_acpi_dma_property" = "true"
- device generic 0 on end
- end
- end
- device ref ufs on end
device ref uart0 on end
device ref gspi1 on end
device ref pch_espi on
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index c9767bc..c0d5c2c 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -1,3 +1,15 @@
+fw_config
+ field RETIMER 0 1
+ option RETIMER_UNKNOWN 0
+ option RETIMER_BYPASS 1
+ option RETIMER_JHL8040 2
+ end
+ field STORAGE 2
+ option STORAGE_UFS 0
+ option STORAGE_NVME 1
+ end
+end
+
chip soc/intel/alderlake
device domain 0 on
device ref igpu on
@@ -147,5 +159,24 @@
device generic 0 on end
end
end
+ device ref pcie4_0 on
+ # Enable CPU PCIE RP 1 using CLK 3
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 3,
+ .clk_src = 3,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ probe STORAGE STORAGE_NVME
+ end
+ device ref ish on
+ chip drivers/intel/ish
+ register "add_acpi_dma_property" = "true"
+ device generic 0 on end
+ end
+ probe STORAGE STORAGE_UFS
+ end
+ device ref ufs on
+ probe STORAGE STORAGE_UFS
+ end
end
end
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Attention is currently required from: Alexander Couzens, Elyes Haouas, Felix Singer, Nicholas Chin, Stefan Ott.
Felix Singer has uploaded a new patch set (#6) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77738?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: sb/intel/i82801{i;j}x/chip.h: Use boolean where appropriate
......................................................................
sb/intel/i82801{i;j}x/chip.h: Use boolean where appropriate
Use the boolean type instead of integers for appropriate attributes and
replace 0's and 1's with false and true in devicetrees for affected
options.
Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/acer/g43t-am3/devicetree.cb
M src/mainboard/dell/e6400/devicetree.cb
M src/mainboard/intel/dg43gt/devicetree.cb
M src/mainboard/lenovo/t400/devicetree.cb
M src/mainboard/lenovo/t400/variants/r500/overridetree.cb
M src/mainboard/lenovo/x200/devicetree.cb
M src/mainboard/lenovo/x200/variants/x200/overridetree.cb
M src/mainboard/lenovo/x200/variants/x301/overridetree.cb
M src/mainboard/roda/rk9/devicetree.cb
M src/southbridge/intel/i82801ix/chip.h
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/chip.h
M src/southbridge/intel/i82801jx/lpc.c
13 files changed, 38 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77738/6
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Change subject: southbridge: Remove last dummy SOUTH_BRIDGE_OPTIONS Kconfig symbol
......................................................................
Patch Set 8: Code-Review+2
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Change subject: 3rdparty/vboot: Update submodule to upstream main
......................................................................
3rdparty/vboot: Update submodule to upstream main
Updating from commit id 7c3b60bb:
2023-12-21 20:34:49 +0000 - (firmware/2lib: Use SSE2 to speed-up Montgomery multiplication)
to commit id 32402941:
2024-01-08 19:53:43 +0000 - (treewide: Put the static keyword at the beginning of declarations)
This brings in 4 new commits:
32402941 treewide: Put the static keyword at the beginning of declarations
242d198b crossystem: Use external tool the clear the TPM
c8a0802f tests: Remove unnecessary vb2_verify_fw.c from TEST20_NAMES list
706088b8 tests: Test HW crypto RSA signature verification
Change-Id: I667376dfc3021fa6d213e3d89917ee228fd14a28
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/79853/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 7c3b60b..3240294 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 7c3b60bb667f917525b5472f6a34df6402d7fa58
+Subproject commit 32402941c0afdb5bf50d6e3c11548ecb1ac80544
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Change subject: nb/amd/pi/00730F01/state_machine: re-enable LPC decodes
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Another way to do it is to set FCH_RESET_DATA_BLOCK->LegacyFree to 0 in
board_FCH_InitReset(), if HAS_AGESA_FCH_OEM_CALLOUT is enabled. That way
one can debug AGESA state machine without a gap in the output.
I'm not strongly opposed to this approach, just leaving this comment as
another option.
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