coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
by Jianeng Ceng (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Jianeng Ceng, Nick Vaccaro, Subrata Banik, Weimin Wu. Hello Eric Lai, Nick Vaccaro, Subrata Banik, Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79858?usp=email to look at the new patch set (#5). Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar ...................................................................... mb/google/nissa/var/anraggar: add FW config to apply the wifi sar 1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb M src/mainboard/google/brya/variants/anraggar/variant.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79858/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Gerrit-Change-Number: 79858 Gerrit-PatchSet: 5 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/geralt: Support setting FB orientation for variants
by Ruihai Zhou (Code Review) 11 Jan '24

11 Jan '24

Ruihai Zhou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78959?usp=email ) Change subject: mb/google/geralt: Support setting FB orientation for variants ...................................................................... Abandoned obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/78959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74031c14e5daac2815e170e93141e3d5b1a06cdc Gerrit-Change-Number: 78959 Gerrit-PatchSet: 7 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: soc/amd/common/acpi: factor out common MADT code
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79861?usp=email ) Change subject: soc/amd/common/acpi: factor out common MADT code ...................................................................... soc/amd/common/acpi: factor out common MADT code The acpi_fill_madt implementation from the Genoa PoC also works for the other AMD SoCs that select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN, so factor out this function to the common AMD ACPI code and change those other SoCs to use the new common functionality instead of having their own implementations. The old code on the single-domain SoCs used the GNB_IO_APIC_ADDR base address to create the MADT entry for the additional IOAPIC in the root complex. The new code iterates over all domains and looks for a resource with the IOMMU_IOAPIC_IDX index in each domain and if it finds it, it creates an MADT entry for that IOAPIC. This resource is created earlier in the boot process when the non-PCI resources are read from the IOHC registers and reported to the allocator. TEST=The resulting MADT doesn't change on Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79861 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/madt.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi.c 15 files changed, 33 insertions(+), 58 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 9c15dd9..42a7bf3 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -35,6 +35,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 4d2482d..ea895c9 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -18,15 +18,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 9355f7d..0f0a371 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -30,6 +30,12 @@ config SOC_AMD_COMMON_BLOCK_ACPI_IVRS bool +config SOC_AMD_COMMON_BLOCK_ACPI_MADT + bool + help + Select this to add the common AMD acpi_fill_madt implementation to + the build which adds the MADT entries for all non-FCH IOAPICs. + config ACPI_SSDT_PSD_INDEPENDENT bool "Allow core p-state independent transitions" default y diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index a0d9290..763a3bc 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -12,6 +12,7 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE) += cpu_power_state.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS) += ivrs.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_MADT) += madt.c romstage-y += elog.c ramstage-y += elog.c diff --git a/src/soc/amd/common/block/acpi/madt.c b/src/soc/amd/common/block/acpi/madt.c new file mode 100644 index 0000000..14fab74b --- /dev/null +++ b/src/soc/amd/common/block/acpi/madt.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/data_fabric.h> +#include <device/device.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { + struct resource *res = probe_resource(dev, IOMMU_IOAPIC_IDX); + if (!res) + continue; + + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + res->base); + } + + return current; +} diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 19ffe6c..09e04f3 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -17,6 +17,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index d9b934f..7762e9d 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -6,29 +6,12 @@ #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/cpu.h> -#include <amdblocks/data_fabric.h> #include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> #include <soc/acpi.h> #include <vendorcode/amd/opensil/genoa_poc/opensil.h> -/* TODO: this can go in a common place */ -unsigned long acpi_fill_madt(unsigned long current) -{ - struct device *dev = NULL; - while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { - struct resource *res = probe_resource(dev, IOMMU_IOAPIC_IDX); - if (!res) - continue; - - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - res->base); - } - - return current; -} - void acpi_fill_fadt(acpi_fadt_t *fadt) { /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */ diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 50cd88d..ac0c96b 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -36,6 +36,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 88cf688..a927f8b 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -21,14 +21,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d5aae52..7192106 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -38,6 +38,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 07f4d3e..80d407c 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -20,14 +20,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index d35ecc2..cd28725 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -38,6 +38,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 9ed1159b..ce727a8 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -21,14 +21,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ee5e130..f501398 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -30,6 +30,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c6aa83f..92f48df 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -24,14 +24,6 @@ #include <soc/southbridge.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/79861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258 Gerrit-Change-Number: 79861 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: device: Add support for multiple PCI segments
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79877?usp=email ) Change subject: device: Add support for multiple PCI segments ...................................................................... Patch Set 1: (4 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79877/comment/8a895c69_33d863c1 : PS1, Line 157: i * CONFIG_ECAM_MMCONF_BUS_NUMBER > Shouldn't this still be 0? In each segment group we start from 0, I guess. that's also my understanding here https://review.coreboot.org/c/coreboot/+/79877/comment/0e6ee3ab_9b60ce2d : PS1, Line 158: CONFIG_ECAM_MMCONF_BUS_NUMBER hm, CONFIG_ECAM_SEGMENT_COUNT > 1 and CONFIG_ECAM_MMCONF_BUS_NUMBER != 256 will be odd, but still valid, right? File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/79877/comment/3ebe8b44_61836c4f : PS1, Line 559: config ECAM_SEGMENT_COUNT i first also added a kconfig option for this, but ended up removing it again, since just using 512 or 1024 for ECAM_MMCONF_BUS_NUMBER both needs one kconfig symbol less and makes the code a bit simpler. that requires the assumption that the ecam mmio regions are continuous, but that's like an assumption that can be made File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/79877/comment/be77d2f1_e1c36735 : PS1, Line 89: uint8_t segment; /* PCI segment */ > We also discussed lately if it wouldn't be easier to make it part of […] Nico and i discussed this topic on irc some weeks ago and we ended up with the conclusion that using the upper 8 bits of secondary and subordinate would probably be the better option. sure, it requires some macros and also some sanity checks that all busses from the same pci root need to have the same segment number, but requires less changes that either affect a larger part of the tree or would introduce additional functions that do similar things as existing functions, but with an additional segment parameter i have local patches that implement this as discussed, but haven't gotten around to clean up, test and push those; mainly waited with that for the xeon sp resource patch to finally get ready and into upstream and now we have duplicate efforts :/ -- To view, visit https://review.coreboot.org/c/coreboot/+/79877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab2c97a71a650e1ceadce4f985147ce05d4e8c86 Gerrit-Change-Number: 79877 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 01:53:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Support setting FB orientation for variants
by Yidi Lin (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Hung-Te Lin, Ruihai Zhou, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78959?usp=email ) Change subject: mb/google/geralt: Support setting FB orientation for variants ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: no longer needed -- To view, visit https://review.coreboot.org/c/coreboot/+/78959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74031c14e5daac2815e170e93141e3d5b1a06cdc Gerrit-Change-Number: 78959 Gerrit-PatchSet: 7 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 01:39:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by Yidi Lin (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Hung-Te Lin, Ruihai Zhou. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78957?usp=email ) Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/geralt/panel_ciri.c: https://review.coreboot.org/c/coreboot/+/78957/comment/24967cb1_edc45ffb : PS9, Line 17: power_on_mipi_boe_tv110wum_ll0 > Sounds good. You can do like this to keep `.power_on` prototype. […] please rebase onto coreboot ToT -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 9 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 01:39:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
by Jianeng Ceng (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Jianeng Ceng, Nick Vaccaro, Subrata Banik, Weimin Wu. Hello Eric Lai, Nick Vaccaro, Subrata Banik, Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79858?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Weimin Wu, Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar ...................................................................... mb/google/nissa/var/anraggar: add FW config to apply the wifi sar 1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb M src/mainboard/google/brya/variants/anraggar/variant.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79858/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Gerrit-Change-Number: 79858 Gerrit-PatchSet: 4 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms
by Casper Chang (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Nick Vaccaro, Paul Menzel. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79891?usp=email ) Change subject: mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79891/comment/70c31c61_bbc58530 : PS1, Line 9: Set touchscreen reset time back to 30ms for Goodix touchscreen to : match resume time requirement (0.5s). > Eldrid device use 30ms from the first shipment till now and there's no touchscreen failure report. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/79891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88432629d82ce0aee670f84cf0a3e65f4052b503 Gerrit-Change-Number: 79891 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Jan 2024 01:28:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms
by Casper Chang (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Nick Vaccaro, Paul Menzel. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79891?usp=email ) Change subject: mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79891/comment/dc9d62c4_7fbda75a : PS1, Line 7: Set > Decrease Done https://review.coreboot.org/c/coreboot/+/79891/comment/87e6fb9e_dc30c5b1 : PS1, Line 9: Set touchscreen reset time back to 30ms for Goodix touchscreen to : match resume time requirement (0.5s). > Why do you think that it will work always with the smaller value? Where is the delay happening. […] Eldrid device use 30ms from the first shipment till now and there's no touchscreen failure report. https://review.coreboot.org/c/coreboot/+/79891/comment/622f2f7d_7206c82e : PS1, Line 11: > Please mention the commit you are reverting here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88432629d82ce0aee670f84cf0a3e65f4052b503 Gerrit-Change-Number: 79891 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Jan 2024 01:28:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms
by Casper Chang (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Casper Chang, Nick Vaccaro. Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79891?usp=email to look at the new patch set (#3). Change subject: mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms ...................................................................... mb/google/volteer/eldrid: Decrease touchsreen reset time back to 30ms Set touchscreen reset time back to 30ms for Goodix touchscreen to match resume time requirement (0.5s). This reverts commit b575397c7fb349d69854d6cca26154cf2f0477c5. Reason for revert: not meet resume time requirement. TEST=verify Goodix touchscreen functional on Eldrid Change-Id: I88432629d82ce0aee670f84cf0a3e65f4052b503 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/79891/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88432629d82ce0aee670f84cf0a3e65f4052b503 Gerrit-Change-Number: 79891 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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