Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79859?usp=email )
Change subject: soc/intel/meteorlake: Enable FSP logo support by default
......................................................................
soc/intel/meteorlake: Enable FSP logo support by default
Enables FSP logo support for Meteor Lake SoC config, covering
both Intel Meteor Lake RVP and ChromeOS devices.
Applies HAVE_FSP_LOGO_SUPPORT configuration only for platforms
with native FSP support.
Ensures successful builds and boots for google/rex and intel/mtlrvp.
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot google/rex and intel/mtlrvp
Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79859
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Jakub Czapiga <czapiga(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
build bot (Jenkins): Verified
Jakub Czapiga: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 298bb83..6dd6273 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -23,6 +23,7 @@
select GENERIC_GPIO_LIB
select HAVE_DEBUG_RAM_SETUP
select HAVE_FSP_GOP
+ select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
select HAVE_HYPERTHREADING
select HAVE_INTEL_COMPLIANCE_TEST_MODE
select HAVE_SMI_HANDLER
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email )
Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 17:
(3 comments)
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/b60a0961_4ea07f5c :
PS14, Line 75: if (sr->BusLimit - sr->BusBase + 1 < HQM1_BUS_OFFSET + HQM_RESERVED_BUS) {
> I believe we still should check […]
Acknowledged
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/e90a4a6a_f2632425 :
PS17, Line 92: assert(bus_limit <= sr->BusLimit)
> We are dealing with input from another program, hence using assert() […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/78327/comment/34e94f56_e428d82d :
PS17, Line 95: CPM1
> This is HQM.
Acknowledged
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 17:
(2 comments)
File src/soc/intel/xeon_sp/include/soc/chip_common.h:
https://review.coreboot.org/c/coreboot/+/78327/comment/04a0e1c8_59395e7f :
PS17, Line 12: void soc_create_ioat_domains(struct bus * const bus, const STACK_RES * const sr);
> No space after the asterisk, please. And the added `const` is not part of the […]
Acknowledged
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/ed0f28af_4f483fa5 :
PS17, Line 254:
> Doesn't `stack_enabled` cover this? Looking at the code below it seems to me […]
stack_enabled decides whether the whole stack is enabled.
Bus comparison decides whether an accelerator is enabled in a stack.
To get together both, it seems confusing. Let me check if we could do some simplification.
As to 'we always have the decide nodes in DSDT even if they are not active'.
Yes, this is how it works. OS will parse ACPI table and check if the specific object exists, or if the resource of specific object effective, if no, OS will ignore the reported object or resource.
SPR has DSDT based on static ASL template (the template defines the max possible resource layout across all SKUs, 1S and 2S), and hence the ineffective object case doesn't only occurs in this code, but also in some defined but not existing host bridge objects. In GNR, we take fully dynamically generated AML for all SSDT/DSDT objects to further improve.
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Change subject: soc/intel/common/tcss: Rename tcss_mux_init
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Patch Set 6: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
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Patch Set 5: Code-Review+1
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Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/tcss/Kconfig:
https://review.coreboot.org/c/coreboot/+/79882/comment/48605593_6e96370c :
PS5, Line 8: Enable USB-C MUX operations via the EC
this sounds like EC is driving the USB-C mode entry. Ideally in such case, AP FW don't need to do anything like sending HPD request etc.
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Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
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Patch Set 5: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/79858/comment/0d8c6b38_85aaa981 :
PS3, Line 9: if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6E))) {
> please use get_wifi_sar_fw_config_filename
Done
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Change subject: mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324 driver
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Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
> Hi ericllai(a)google.com, […]
Do you confirm the value is okay now? Since the value is very different with first patch.
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