coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 04:58:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allocate resources above 4G
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Nico Huber, Paul Menzel, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79058?usp=email ) Change subject: soc/intel/xeon_sp: Allocate resources above 4G ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79058?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Gerrit-Change-Number: 79058 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 04:58:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/Kconfig: Add an option to allocate above 4G by default
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Annie Chen, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Shuo Liu has uploaded a new patch set (#18) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... soc/intel/xeon_sp: Redesign resource allocation The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/chip.c A src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 17 files changed, 278 insertions(+), 553 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allocate resources above 4G
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Nico Huber, Paul Menzel, Shuo Liu, Tim Chu. Shuo Liu has uploaded a new patch set (#11) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/79058?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Allocate resources above 4G ...................................................................... soc/intel/xeon_sp: Allocate resources above 4G This makes sure that prefetchable mem64 memory gets allocated above 4G which allows non prefetchable resources to be allocated in the tight window below 4G. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79058/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/79058?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Gerrit-Change-Number: 79058 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: device/Kconfig: Add an option to allocate above 4G by default
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Jincheng Li, Nico Huber, Paul Menzel, Shuo Liu. Shuo Liu has uploaded a new patch set (#17) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78331?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+1 by Paul Menzel, Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: device/Kconfig: Add an option to allocate above 4G by default ...................................................................... device/Kconfig: Add an option to allocate above 4G by default TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f --- M src/device/Kconfig M src/device/resource_allocator_v4.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78331/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/78331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Gerrit-Change-Number: 78331 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: device/Kconfig: Add an option to allocate above 4G by default
by Shuo Liu (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Jincheng Li, Nico Huber, Paul Menzel. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78331?usp=email ) Change subject: device/Kconfig: Add an option to allocate above 4G by default ...................................................................... Patch Set 16: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78331/comment/243d9813_a75ad20c : PS13, Line 8: > Sometimes, a PCIe host bridge will provide MMIO32 (below 4G) and MMIO64 (above 4G) windows, the opti […] Done File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/78331/comment/9473d5c7_f58787ad : PS16, Line 1012: config RESOURCE_IGNORE_FLAG_IORESOURCE_ABOVE_4G > I think this deserves a more positive naming. e.g. `ALWAYS_ALLOW_ABOVE_4G_ALLOCATION`. Acknowledged https://review.coreboot.org/c/coreboot/+/78331/comment/6ca02944_946920db : PS16, Line 1019: 32bit mode > Technically the incompatible mode is "flat protected mode", or we could […] Since resource allocation will be programmed into PCI BARs, which provides 64bit BAR register if needed, hence a 32bit bootloader can actually allocate 64bit resources, as long as coreboot will load a driver for this device. To allocate 64bit resource in a 32bit bootloader but not using it is actually a requirement in various cases. E.g, some device will have >4G BAR preference, but if allocated in <4G space, OS will not modify it any more. Hence, we even think we could just simply the help message as, help Don't limit mem resources to 4G, but to their actual limit. (This can break ... -> to be removed) -- To view, visit https://review.coreboot.org/c/coreboot/+/78331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Gerrit-Change-Number: 78331 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 03:58:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Enable PIXA touchpad
by Subrata Banik (Code Review) 11 Jan '24

11 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79872?usp=email ) Change subject: mb/google/nissa/var/craaskov: Enable PIXA touchpad ...................................................................... mb/google/nissa/var/craaskov: Enable PIXA touchpad Add PIXA touchpad for variants of craaskov. BUG=b:289962540 TEST=build craaskov firmware and test with PIXA touchpad Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79872 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index c9299de..cc4ce53 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -284,6 +284,15 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2303"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x68 on end + end end device ref pcie_rp7 off end device ref emmc on end -- To view, visit https://review.coreboot.org/c/coreboot/+/79872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Gerrit-Change-Number: 79872 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vc/google: Show different logos for different ChromeOS devices
by Subrata Banik (Code Review) 11 Jan '24

11 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79775?usp=email ) Change subject: vc/google: Show different logos for different ChromeOS devices ...................................................................... vc/google: Show different logos for different ChromeOS devices This commit adds support for showing different logos on the ChromeOS firmware splash screen based on the device model (between Chromebook-Plus and regular ChromeOS devices like Chromebook and Chromebox). This allows OEMs to customize the branding on their devices. This patch also introduces three new Kconfigs: - CHROMEOS_FW_SPLASH_SCREEN - CHROMEOS_LOGO_PATH - CHROMEBOOK_PLUS_LOGO_PATH which allow users to enable the fw splash screen feature in the vendorcode. Previously, we were using the BMP_LOGO Kconfig in drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be located inside the architecture specific files. BUG=b:317880956 BRANCH=None TEST=emerge-rex coreboot chromeos-bootimage verify that FW splash screen appears Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79775 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/drivers/intel/fsp2_0/Makefile.inc M src/include/bootsplash.h M src/lib/Kconfig M src/lib/bmp_logo.c M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/splash.c 7 files changed, 67 insertions(+), 2 deletions(-) Approvals: Shelley Chen: Looks good to me, approved Kapil Porwal: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 5463405..4cb24ff 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -127,6 +127,7 @@ endif # Add logo to the cbfs image +ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y) cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME)) logo.bmp-type := raw @@ -135,6 +136,7 @@ else ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZ4),y) logo.bmp-compression := LZ4 endif +endif ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index 9d1bae3..86048a4 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -15,7 +15,11 @@ unsigned int y_resolution, unsigned int bytes_per_line, unsigned int fb_resolution); - +/* + * Allow platform-specific BMP logo overrides via HAVE_CUSTOM_BMP_LOGO config. + * For example: Introduce configurable BMP logo for customization on platforms like ChromeOS + */ +const char *bmp_logo_filename(void); void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size); void bmp_release_logo(void); diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 80efe75..d11bf59 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -149,3 +149,7 @@ help When enabled it will be possible to detect usable RAM using probe_ram function. + +config HAVE_CUSTOM_BMP_LOGO + def_bool n + depends on BMP_LOGO diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c index 330ed6f..2888777 100644 --- a/src/lib/bmp_logo.c +++ b/src/lib/bmp_logo.c @@ -5,9 +5,17 @@ #include <cbfs.h> #include <cbmem.h> #include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> static const struct cbmem_entry *logo_entry; +#if !CONFIG(HAVE_CUSTOM_BMP_LOGO) +const char *bmp_logo_filename(void) +{ + return "logo.bmp"; +} +#endif + void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size) { void *logo_buffer; @@ -24,7 +32,7 @@ if (!logo_buffer) return; - *logo_size = cbfs_load("logo.bmp", logo_buffer, 1 * MiB); + *logo_size = cbfs_load(bmp_logo_filename(), logo_buffer, 1 * MiB); if (*logo_size) *logo_ptr = (uintptr_t)logo_buffer; } diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 0979652..74f23d6 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -79,5 +79,28 @@ bool depends on ACPI_SOC_NVS +config CHROMEOS_FW_SPLASH_SCREEN + bool "Display Splash Screen in firmware" + default n + select BMP_LOGO + select HAVE_CUSTOM_BMP_LOGO + help + Select this option to display the manufacturer's logo or + custom image (OEM splash screen) early in the boot process. + This can enhance the user experience by providing visual + feedback while the system starts up. For example, ChromeOS + devices use this option to show their logo before the operating + system loads. + +config CHROMEOS_LOGO_PATH + string "Path to ChromeOS logo file" + depends on CHROMEOS_FW_SPLASH_SCREEN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" + +config CHROMEBOOK_PLUS_LOGO_PATH + string "Path to Chromebook Plus logo file" + depends on CHROMEOS_FW_SPLASH_SCREEN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index dce4d9c..af37a09 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -20,3 +20,15 @@ ramstage-y += watchdog.c romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += dram_part_num_override.c +ramstage-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += splash.c + +# Add logo to the cbfs image +cbfs-files-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += cb_logo.bmp +cb_logo.bmp-file := $(call strip_quotes,$(CONFIG_CHROMEOS_LOGO_PATH)) +cb_logo.bmp-type := raw +cb_logo.bmp-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += cb_plus_logo.bmp +cb_plus_logo.bmp-file := $(call strip_quotes,$(CONFIG_CHROMEBOOK_PLUS_LOGO_PATH)) +cb_plus_logo.bmp-type := raw +cb_plus_logo.bmp-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c new file mode 100644 index 0000000..3532fb8 --- /dev/null +++ b/src/vendorcode/google/chromeos/splash.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootsplash.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const char *bmp_logo_filename(void) +{ + if (chromeos_device_branded_plus()) + return "cb_plus_logo.bmp"; + else + return "cb_logo.bmp"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Gerrit-Change-Number: 79775 Gerrit-PatchSet: 11 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT config
by Subrata Banik (Code Review) 11 Jan '24

11 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79860?usp=email ) Change subject: mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT config ...................................................................... mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT config Removes unnecessary HAVE_FSP_LOGO_SUPPORT config from google/rex baseboard. Intel Meteor Lake SoC now selects this config automatically for supported platforms. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp. Change-Id: I89bdd54cb73b11f74db2927a5eb86ab826c60517 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79860 Reviewed-by: Jakub Czapiga <czapiga(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Jakub Czapiga: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index a7f7b06..a253c8c 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -19,7 +19,6 @@ select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select I2C_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_DISABLE_STAGE_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/79860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89bdd54cb73b11f74db2927a5eb86ab826c60517 Gerrit-Change-Number: 79860 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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