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Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/tcss/Kconfig:
https://review.coreboot.org/c/coreboot/+/79882/comment/4d21af78_04b3444c :
PS3, Line 8: to set MUX to a disconnected state
> I'd leave this for the help below, and just leave this as "Enable USB-C MUX operations via the EC" o […]
Done
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Hello Iru Cai, Iru Cai, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79881?usp=email
to look at the new patch set (#8).
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Change subject: mb/hp/(elitebook_820_g2|folio_9480m): Add HP Sure Start workaround
......................................................................
mb/hp/(elitebook_820_g2|folio_9480m): Add HP Sure Start workaround
To work around HP Sure Start the top of flash needs to contain a vendor
provided image that the EC verifies before releasing the X86 from reset.
Instead of using the wrong flash size and padding the image with dd, add
an fmap layout and use cbfstool memory map arguments to achieve the
same.
UNTESTED.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I0e59d035ce9281062272aeef92f50f2bbf3a9c5f
---
M Documentation/mainboard/hp/elitebook_820_g2.md
M Documentation/mainboard/hp/folio_9480m.md
M src/mainboard/hp/elitebook_820_g2/Kconfig
M src/mainboard/hp/elitebook_820_g2/Makefile.inc
A src/mainboard/hp/elitebook_820_g2/board.fmd
M src/mainboard/hp/folio_9480m/Kconfig
M src/mainboard/hp/folio_9480m/Makefile.inc
A src/mainboard/hp/folio_9480m/board.fmd
8 files changed, 81 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/79881/8
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Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/tcss/Kconfig:
https://review.coreboot.org/c/coreboot/+/79882/comment/b1b7a84c_524c0d4f :
PS5, Line 8: Enable USB-C MUX operations via the EC
> this sounds like EC is driving the USB-C mode entry. […]
Right - that's what ours do. Is it right to have default y for the Google devices though?
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Change subject: device: Add support for multiple PCI segments
......................................................................
Patch Set 1:
(2 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/79877/comment/8046d6a4_46124f15 :
PS1, Line 559: config ECAM_SEGMENT_COUNT
> i first also added a kconfig option for this, but ended up removing it again, since just using 512 o […]
My impression was that ECAM_MMCONF_BUS_NUMBER == 256 would be the better choice for the subordinate and max_subordinate handling.
File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/79877/comment/863e1fd5_6a6d3190 :
PS1, Line 89: uint8_t segment; /* PCI segment */
> Nico and i discussed this topic on irc some weeks ago and we ended up with the conclusion that using […]
I'd be happy to test those to not have duplicate effort.
My first try was to use the upper 8 bit of `secondary`, but this was discarded in order to reuse existing code in src/device/pci_device.c. The code really doesn't care about the segment group as long as the pci_*_config functions access the right segment.
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