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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
Tested on ibm/sbp1 (SPR 4S): Boots fine to ubuntu 22.04.
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Change subject: soc/intel/xeon_sp: Allocate resources above 4G
......................................................................
Patch Set 12: Code-Review+1
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Change subject: device/Kconfig: Add an option to allocate above 4G by default
......................................................................
Patch Set 19: Code-Review+1
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/78331/comment/50d330ce_64fefbe5 :
PS16, Line 1019: 32bit mode
> Since resource allocation will be programmed into PCI BARs, which provides 64bit BAR register if nee […]
I guess that's ok, as it doesn't have a prompt.
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Change subject: device/Kconfig: Add an option to allocate above 4G by default
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78331/comment/cf40ad84_78635955 :
PS13, Line 8:
> Could you add this info to the commit message?
Done
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Hello Chen, Gang C, Jincheng Li, Lean Sheng Tan, Nico Huber, Paul Menzel, Shuo Liu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78331?usp=email
to look at the new patch set (#19).
Change subject: device/Kconfig: Add an option to allocate above 4G by default
......................................................................
device/Kconfig: Add an option to allocate above 4G by default
Historically resource allocation in coreboot was 32bit x86 thing. To
remain compatible with this behavior (e.g. to keep 32bit payloads
happy), resource allocation limits resources to 32 bits unless
explicitly overridden. However this behavior is not always appropriate:
e.g. on non x86 platforms the PCIe mem decode window could be above 4G.
Another case on x86 is where the decode window(s) below 4G are not
adequate for fitting all resources and the payload is 64bit
capable (e.g. Linux).
This adds a Kconfig flag to override the behavior to limit resources to
32bit by default and to allocate resources according to the real
hardware limits.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f
---
M src/device/Kconfig
M src/device/resource_allocator_v4.c
2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78331/19
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 19:
(1 comment)
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/9343f8c9_bfab1049 :
PS17, Line 254:
> I would prefer to discuss this in a separate patch.
ACPI is outside the scope of this patch, which just deals with resource allocation.
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Change subject: device/Kconfig: Add an option to allocate above 4G by default
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78331/comment/2e2fb8ae_72161760 :
PS13, Line 8:
> Done
Could you add this info to the commit message?
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79020?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
......................................................................
mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
Update the VBT version from 249 to 251.
It is the same VBT settings as the previous one, but update it
based on ADL-P MR5 FSP so it will work with MR5 GOP driver to fix
the error "no graphic HOB found".
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79020
Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/prodrive/atlas/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
Maximilian Brune: Looks good to me, but someone else must approve
diff --git a/src/mainboard/prodrive/atlas/data.vbt b/src/mainboard/prodrive/atlas/data.vbt
index da78bfc..3aea1fd 100644
--- a/src/mainboard/prodrive/atlas/data.vbt
+++ b/src/mainboard/prodrive/atlas/data.vbt
Binary files differ
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59874?usp=email )
Change subject: arch/x86/c_start.S: Add proper x86_64 code
......................................................................
arch/x86/c_start.S: Add proper x86_64 code
Don't truncate upper bits in assembly code and thus allow loading
of ramstage above 4GiB.
Tested on qemu with cbmem_top set to TOUUD.
Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Co-authored-by: Benjamin Doron <benjamin.doron(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59874
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/arch/x86/c_start.S
1 file changed, 24 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 02ddf75..6bea8db 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -59,6 +59,24 @@
leal _stack, %edi
#endif
+#if ENV_X86_64
+ /** poison the stack. Code should not count on the
+ * stack being full of zeros. This stack poisoning
+ * recently uncovered a bug in the broadcast SIPI
+ * code.
+ */
+ movabs $_estack, %rcx
+ sub %rdi, %rcx
+ shr $3, %rcx /* it is 64 bit aligned, right? */
+ movq $0xDEADBEEFDEADBEEF, %rax
+ rep
+ stosq
+
+ /* Set new stack with enforced alignment. */
+ movabs $_estack, %rsp
+ movq $(0xfffffffffffffff0), %rax
+ and %rax, %rsp
+#else
/** poison the stack. Code should not count on the
* stack being full of zeros. This stack poisoning
* recently uncovered a bug in the broadcast SIPI
@@ -74,6 +92,7 @@
/* Set new stack with enforced alignment. */
movl $_estack, %esp
andl $(0xfffffff0), %esp
+#endif
/*
* Now we are finished. Memory is up, data is copied and
@@ -82,7 +101,12 @@
*/
post_code(POSTCODE_PRE_HARDWAREMAIN) /* post 6e */
+#if ENV_X86_64
+ movq $0xFFFFFFFFFFFFFFF0, %rax
+ and %rax, %rsp
+#else
andl $0xFFFFFFF0, %esp
+#endif
#if CONFIG(ASAN_IN_RAMSTAGE)
call asan_init
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79058?usp=email )
Change subject: soc/intel/xeon_sp: Allocate resources above 4G
......................................................................
Patch Set 12: Code-Review+2
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