coreboot-gerrit January 2024

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[S] Change in coreboot[main]: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
by Matt DeVillier (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Kapil Porwal, Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79882?usp=email ) Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/tcss/Kconfig: https://review.coreboot.org/c/coreboot/+/79882/comment/6e2ae1c5_22b0321e : PS6, Line 10: default n I don't think you want `default n` here since it will prevent other Kconfigs from selecting it later. Leaving it undefined results in it being set to N if not explicitly selected elsewhere -- To view, visit https://review.coreboot.org/c/coreboot/+/79882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Gerrit-Change-Number: 79882 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 15:45:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
by Sean Rhodes (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Kapil Porwal, Matt DeVillier, Subrata Banik. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79882?usp=email ) Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/tcss/Kconfig: https://review.coreboot.org/c/coreboot/+/79882/comment/d83fa726_b98cb490 : PS5, Line 8: Enable USB-C MUX operations via the EC > > So default N? Quick look at the chromeec, given the complexity of their tcpc driver, i would be su […] Cool - think it's right as in then. -- To view, visit https://review.coreboot.org/c/coreboot/+/79882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Gerrit-Change-Number: 79882 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 15:17:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: use common AMD MADT code
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79885?usp=email ) Change subject: soc/amd/stoneyridge/acpi: use common AMD MADT code ...................................................................... soc/amd/stoneyridge/acpi: use common AMD MADT code Now that Stoneyridge also reports the GNB IOAPIC on the domain and with the IOMMU_IOAPIC_IDX resource index the common AMD MADT code expects, we ca switch over to using this common code on Stoneyridge too. TEST=The resulting MADT doesn't change on Careena Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79885 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi.c 2 files changed, 1 insertion(+), 7 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index dadda8d..b823d02 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -18,6 +18,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index dc7ef5f..9dd8d72 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -22,13 +22,6 @@ #include <soc/southbridge.h> #include <soc/northbridge.h> -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/79885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Gerrit-Change-Number: 79885 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF compo...
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Anand Vaikar, Fred Reitberger, Nikolai Vyssotski, ritul guru. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79830?usp=email ) Change subject: soc/amd/glinda/include/soc: Update the fabric id for IOHUBS0 DF component ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79830/comment/875b8dc7_1e079c77 : PS2, Line 7: Update the fabric id for IOHUBS0 DF component i'd use 'soc/amd/glinda/include/data_fabric: update IOHUBS0 fabric ID' which fits in the 72 chars -- To view, visit https://review.coreboot.org/c/coreboot/+/79830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Gerrit-Change-Number: 79830 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 14:48:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79884?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain ...................................................................... soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain Move the GNB IOAPIC resource from being reported in the GNB PCI device to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the common AMD MADT code will be able to find the resource. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index bf2f992..2b6ba45 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -43,9 +43,6 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, idx++); - - /* NB IOAPIC2 resource */ - mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); } /** @@ -301,6 +298,10 @@ /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_from_to(dev, idx++, mem_useable, tom); + /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT + code can find this resource */ + mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000); + /* If there is memory above 4GiB */ if (high_tom >> 32) { /* 4GiB -> high top usable */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Gerrit-Change-Number: 79884 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: drop wrong comment in MADT code
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79883?usp=email ) Change subject: soc/amd/stoneyridge/acpi: drop wrong comment in MADT code ...................................................................... soc/amd/stoneyridge/acpi: drop wrong comment in MADT code The IOAPIC structure that this function created is for the IOAPIC in the GNB and not the one in the FCH which is called Kern in this SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79883 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/acpi.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index dc050cf..dc7ef5f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -24,7 +24,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/79883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76 Gerrit-Change-Number: 79883 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79862?usp=email ) Change subject: soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h ...................................................................... soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h Move the IOMMU_IOAPIC_IDX define from amdblocks/data_fabric.h to amdblocks/ioapic.h which is both a more logical place for it to be and this is also a preparation to use the common AMD MADT code for the Stoneyridge SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79862 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/acpi/madt.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/common/block/include/amdblocks/ioapic.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/genoa_poc/root_complex.c 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 814f514..140968c 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -3,7 +3,6 @@ #include <acpi/acpi_ivrs.h> #include <amdblocks/acpi.h> #include <amdblocks/cpu.h> -#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/iommu.h> #include <arch/ioapic.h> diff --git a/src/soc/amd/common/block/acpi/madt.c b/src/soc/amd/common/block/acpi/madt.c index 14fab74b..b502053c 100644 --- a/src/soc/amd/common/block/acpi/madt.c +++ b/src/soc/amd/common/block/acpi/madt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <amdblocks/data_fabric.h> +#include <amdblocks/ioapic.h> #include <device/device.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 3a08a20..9dbf5da 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -13,9 +13,6 @@ #define BROADCAST_FABRIC_ID 0xff -/* Index of IOAPIC resource associated with IOMMU */ -#define IOMMU_IOAPIC_IDX 0x20000120 - #define DF_MMIO_REG_OFFSET(instance) ((instance) * DF_MMIO_REG_SET_SIZE * sizeof(uint32_t)) /* The number of data fabric MMIO registers is SoC-specific */ diff --git a/src/soc/amd/common/block/include/amdblocks/ioapic.h b/src/soc/amd/common/block/include/amdblocks/ioapic.h index bd1c363..37f4b29 100644 --- a/src/soc/amd/common/block/include/amdblocks/ioapic.h +++ b/src/soc/amd/common/block/include/amdblocks/ioapic.h @@ -7,4 +7,7 @@ #define FCH_IOAPIC_ID 0 #define GNB_IOAPIC_ID 1 +/* Index of IOAPIC resource associated with IOMMU */ +#define IOMMU_IOAPIC_IDX 0x20000120 + #endif /* AMD_BLOCK_IOAPIC_H */ diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 8ed95ab..f21cad5 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/ioapic.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> #include <amdblocks/smn.h> diff --git a/src/soc/amd/genoa_poc/root_complex.c b/src/soc/amd/genoa_poc/root_complex.c index 7dd1f82..849bf77 100644 --- a/src/soc/amd/genoa_poc/root_complex.c +++ b/src/soc/amd/genoa_poc/root_complex.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/data_fabric.h> +#include <amdblocks/ioapic.h> #include <amdblocks/root_complex.h> #include <console/console.h> #include <device/device.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/79862?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 Gerrit-Change-Number: 79862 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: .gitignore: Ignore payloads/libpayload/generated/
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79873?usp=email ) Change subject: .gitignore: Ignore payloads/libpayload/generated/ ...................................................................... .gitignore: Ignore payloads/libpayload/generated/ Add 'generated/' to .gitignore. Change-Id: Ief7afe3cf6ffcaba6aa5be27f41c6a32de9e6bbb Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79873 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M .gitignore 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/.gitignore b/.gitignore index 126cae6..e813493 100644 --- a/.gitignore +++ b/.gitignore @@ -9,6 +9,7 @@ build/ coreboot-builds/ coreboot-builds*/ +generated/ site-local -- To view, visit https://review.coreboot.org/c/coreboot/+/79873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief7afe3cf6ffcaba6aa5be27f41c6a32de9e6bbb Gerrit-Change-Number: 79873 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
by Subrata Banik (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Kapil Porwal, Matt DeVillier, Sean Rhodes. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79882?usp=email ) Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/tcss/Kconfig: https://review.coreboot.org/c/coreboot/+/79882/comment/08adc61a_1e2ce35d : PS5, Line 8: Enable USB-C MUX operations via the EC > So default N? Quick look at the chromeec, given the complexity of their tcpc driver, i would be surprised if coreboot needs to do anything Actually, there are two ways to handle the USBC mode switch/init. One, EC initiate the USB-C mode switch by its own during boot, second is AP sends command to EC to initiate the USBC mode switch. for chromeos devices prior to rex, we were using first method aka EC owns the decision of mode switch bt starting with Rex, we have implement AP triggers the USBC mode switching. details https://review.coreboot.org/q/topic:%22tcss_ap_mode_entry%22 -- To view, visit https://review.coreboot.org/c/coreboot/+/79882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Gerrit-Change-Number: 79882 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 14:36:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
by Sean Rhodes (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Kapil Porwal, Matt DeVillier, Subrata Banik. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79882?usp=email ) Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/tcss/Kconfig: https://review.coreboot.org/c/coreboot/+/79882/comment/e2814ec1_b08fe49a : PS5, Line 8: Enable USB-C MUX operations via the EC > for ChromeEC devices, yes. […] So default N? Quick look at the chromeec, given the complexity of their tcpc driver, i would be surprised if coreboot needs to do anything -- To view, visit https://review.coreboot.org/c/coreboot/+/79882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Gerrit-Change-Number: 79882 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 14:29:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2024