coreboot-gerrit January 2024

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[M] Change in coreboot[main]: device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig options
by Martin L Roth (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Arthur Heymans, Sean Rhodes. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79669?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig options ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/usb4/Kconfig: https://review.coreboot.org/c/coreboot/+/79669/comment/317633b0_75746f77 : PS3, Line 38: d Shouldn't this just be an if around everything in this file except `config SOC_INTEL_COMMON_BLOCK_USB4` -- To view, visit https://review.coreboot.org/c/coreboot/+/79669?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia515d52baead9e151533278c33fda9436ee56168 Gerrit-Change-Number: 79669 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 14 Jan 2024 02:01:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device/Kconfig: Hide early graphic init option on trivial case
by Martin L Roth (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Arthur Heymans, Felix Singer, Nico Huber. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79668?usp=email ) Change subject: device/Kconfig: Hide early graphic init option on trivial case ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: I think we want NO_EARLY_GFX_INIT set in this case, but by adding the depends on to the choice statement, both MAINBOARD_USE_EARLY_LIBGFXINIT and NO_EARLY_GFX_INIT are set to 0. Is this really what was intended here? I mean, it may not matter in the long run, because NO_EARLY_GFX_INIT isn't actually used anywhere. Why is this even a choice instead of a simple config option? -- To view, visit https://review.coreboot.org/c/coreboot/+/79668?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0447d440009d6dcf8c1f911672156e159d810cf Gerrit-Change-Number: 79668 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 14 Jan 2024 01:55:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/asrock/b75m-itx: Use chipset dt reference names
by Janik (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Felix Singer, Kevin Keijzer. Janik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79971?usp=email ) Change subject: mb/asrock/b75m-itx: Use chipset dt reference names ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: I built before and after. `build/coreboot.rom` ended up being identical so the change was successful -- To view, visit https://review.coreboot.org/c/coreboot/+/79971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Gerrit-Change-Number: 79971 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Janik Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Comment-Date: Sun, 14 Jan 2024 00:55:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/fw_config: Remove redundant stdbool and stdint
by Elyes Haouas (Code Review) 14 Jan '24

14 Jan '24

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79911?usp=email ) Change subject: lib/fw_config: Remove redundant stdbool and stdint ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: needs #79910 -- To view, visit https://review.coreboot.org/c/coreboot/+/79911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8676769127d21a3b4693ed947a7231b94e99241 Gerrit-Change-Number: 79911 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 14 Jan 2024 00:04:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/asrock/b75m-itx: Use chipset dt reference names
by Felix Singer (Code Review) 13 Jan '24

13 Jan '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79971?usp=email ) Change subject: mb/asrock/b75m-itx: Use chipset dt reference names ...................................................................... mb/asrock/b75m-itx: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asrock/b75m-itx/devicetree.cb 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/79971/1 diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 6d4ca2d..59645f0 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -7,13 +7,13 @@ register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on - device pci 00.0 on + device ref host_bridge on subsystemid 0x1849 0x0150 end - device pci 01.0 on + device ref peg10 on subsystemid 0x1849 0x0151 end - device pci 02.0 on + device ref igd on subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x @@ -28,42 +28,42 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on subsystemid 0x1849 0x1e31 end - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on subsystemid 0x1849 0x1e3a end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on subsystemid 0x1849 0x1e2d end - device pci 1b.0 on # HDA Audio controller + device ref hda on subsystemid 0x1849 0x8892 end - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on subsystemid 0x1849 0x1e10 end - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on # PCIe Port #4, Realtek PCIe GbE Controller + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 on # Realtek PCIe GbE Controller subsystemid 0x1849 0x1e16 device pci 00.0 on end # PCI 10ec:8168 end - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on # PCIe Port #6 + device ref pcie_rp5 off end + device ref pcie_rp6 on subsystemid 0x1849 0x1e1a end - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref ehci1 on subsystemid 0x1849 0x1e26 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_bridge off end + device ref lpc on subsystemid 0x1849 0x1e49 chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -117,14 +117,14 @@ end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on subsystemid 0x1849 0x1e02 end - device pci 1f.3 on # SMBus + device ref smbus on subsystemid 0x1849 0x1e22 end - device pci 1f.5 off end - device pci 1f.6 off end # Thermal + device ref sata2 off end + device ref thermal off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Gerrit-Change-Number: 79971 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/asus/h61-series: Remove superfluous comments related to PCI devices
by Felix Singer (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Angel Pons. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79970?usp=email ) Change subject: mb/asus/h61-series: Remove superfluous comments related to PCI devices ...................................................................... mb/asus/h61-series: Remove superfluous comments related to PCI devices Since all devicetrees from asus/h61_series are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb 6 files changed, 55 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/79970/1 diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index cde0431..7f37acc 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -3,39 +3,39 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on - device ref host_bridge on end # Host bridge - device ref peg10 on end # PEG - device ref igd on end # iGPU + device ref host_bridge on end + device ref peg10 on end + device ref igd on end chip southbridge/intel/bd82x6x register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device ref mei1 on end # MEI #1 - device ref mei2 off end # MEI #2 - device ref me_ide_r off end # ME IDE-R - device ref me_kt off end # ME KT - device ref gbe off end # Intel GbE - device ref ehci2 on end # EHCI #2 - device ref hda on end # HD Audio + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on end + device ref hda on end - device ref pcie_rp1 off end # RP #1 - device ref pcie_rp2 off end # RP #2 - device ref pcie_rp3 off end # RP #3 - device ref pcie_rp4 off end # RP #4 - device ref pcie_rp5 off end # RP #5 - device ref pcie_rp6 off end # RP #6 - device ref pcie_rp7 off end # RP #7 - device ref pcie_rp8 off end # RP #8 + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref ehci1 on end # EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on end # LPC bridge - device ref sata1 on end # SATA (AHCI) - device ref smbus on end # SMBus - device ref sata2 off end # SATA (Legacy) - device ref thermal off end # Thermal + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on end + device ref sata1 on end # SATA (AHCI) + device ref smbus on end + device ref sata2 off end # SATA (Legacy) + device ref thermal off end end end end diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 066136cb..8558510 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,21 +5,21 @@ subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device ref hda on # High Definition Audio controller + device ref hda on subsystemid 0x1043 0x8445 end - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp2 off end # PCIe Port #2 - device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end device ref pcie_rp4 on end # PCIe x1 Slot 1 PCIE_1 device ref pcie_rp5 on end # PCIe x1 Slot 2 PCIE_2 device ref pcie_rp6 on # Realtek Gigabit NIC device pci 00.0 on end end - device ref pcie_rp7 off end # PCIe Port #7 - device ref pcie_rp8 off end # PCIe Port #8 + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge PCI-LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb index c4ff6b0..7612c55 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb @@ -6,7 +6,7 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM - device ref hda on # HD audio controller + device ref hda on subsystemid 0x1043 0x8445 end device ref pcie_rp1 on end # PCIe 1x slot (PCIEX1_1) @@ -18,13 +18,13 @@ device pci 00.0 on end end end - device ref pcie_rp4 off end # Unused PCIe port + device ref pcie_rp4 off end device ref pcie_rp5 on end # PCIe 1x slot (PCIEX1_3) - device ref pcie_rp6 off end # Unused PCIe port - device ref pcie_rp7 off end # Unused PCIe port - device ref pcie_rp8 off end # Unused PCIe port + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb index fc3313e..1aa08f26 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb @@ -6,16 +6,16 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device ref pcie_rp1 on end # RP #1 - device ref pcie_rp2 off end # RP #2 - device ref pcie_rp3 off end # RP #3 - device ref pcie_rp4 on end # RP #4: PCIEX1_1 - device ref pcie_rp5 on end # RP #5: PCIEX1_2 - device ref pcie_rp6 on end # RP #6: RTL8111 GbE NIC - device ref pcie_rp7 off end # RP #7 - device ref pcie_rp8 off end # RP #8 + device ref pcie_rp1 on end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 on end # PCIEX1_1 + device ref pcie_rp5 on end # PCIEX1_2 + device ref pcie_rp6 on end # RTL8111 GbE NIC + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb index 026bd81..59c2a14 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb @@ -7,7 +7,7 @@ device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) - device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" @@ -17,10 +17,10 @@ device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller device ref pcie_rp5 on end # PCIe x1 Port, x16 size (PCIEX16_2) device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller - device ref pcie_rp7 off end # Unused PCIe Port - device ref pcie_rp8 off end # Unused PCIe Port + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 9db03fc..ef22ce5 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -8,7 +8,7 @@ device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) - device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" @@ -16,10 +16,10 @@ end end device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller - device ref pcie_rp5 on end # RP #6: ASM1083 PCI Bridge + device ref pcie_rp5 on end # ASM1083 PCI Bridge device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller - device ref pcie_rp7 off end # Unused PCIe Port - device ref pcie_rp8 off end # Unused PCIe Port + device ref pcie_rp7 off end + device ref pcie_rp8 off end device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 -- To view, visit https://review.coreboot.org/c/coreboot/+/79970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Gerrit-Change-Number: 79970 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/asus/h61-series: Convert remaining PCI numbers into reference names
by Felix Singer (Code Review) 13 Jan '24

13 Jan '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79969?usp=email ) Change subject: mb/asus/h61-series: Convert remaining PCI numbers into reference names ...................................................................... mb/asus/h61-series: Convert remaining PCI numbers into reference names Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb 5 files changed, 47 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/79969/1 diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index cb30fc3..066136cb 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,21 +5,21 @@ subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1b.0 on # High Definition Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x1043 0x8445 end - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe x1 Slot 1 PCIE_1 - device pci 1c.4 on end # PCIe x1 Slot 2 PCIE_2 - device pci 1c.5 on # Realtek Gigabit NIC + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe x1 Slot 1 PCIE_1 + device ref pcie_rp5 on end # PCIe x1 Slot 2 PCIE_2 + device ref pcie_rp6 on # Realtek Gigabit NIC device pci 00.0 on end end - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb index aa9f8c8..c4ff6b0 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb @@ -6,25 +6,25 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM - device pci 1b.0 on # HD audio controller + device ref hda on # HD audio controller subsystemid 0x1043 0x8445 end - device pci 1c.0 on end # PCIe 1x slot (PCIEX1_1) - device pci 1c.1 on end # PCIe 1x slot (PCIEX1_2) - device pci 1c.2 on # Realtek Gigabit Ethernet + device ref pcie_rp1 on end # PCIe 1x slot (PCIEX1_1) + device ref pcie_rp2 on end # PCIe 1x slot (PCIEX1_2) + device ref pcie_rp3 on # Realtek Gigabit Ethernet subsystemid 0x1043 0x8432 chip drivers/net register "customized_leds" = "0x00f6" device pci 00.0 on end end end - device pci 1c.3 off end # Unused PCIe port - device pci 1c.4 on end # PCIe 1x slot (PCIEX1_3) - device pci 1c.5 off end # Unused PCIe port - device pci 1c.6 off end # Unused PCIe port - device pci 1c.7 off end # Unused PCIe port + device ref pcie_rp4 off end # Unused PCIe port + device ref pcie_rp5 on end # PCIe 1x slot (PCIEX1_3) + device ref pcie_rp6 off end # Unused PCIe port + device ref pcie_rp7 off end # Unused PCIe port + device ref pcie_rp8 off end # Unused PCIe port - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb index 5d9635c..fc3313e 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb @@ -6,16 +6,16 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 on end # RP #4: PCIEX1_1 - device pci 1c.4 on end # RP #5: PCIEX1_2 - device pci 1c.5 on end # RP #6: RTL8111 GbE NIC - device pci 1c.6 off end # RP #7 - device pci 1c.7 off end # RP #8 + device ref pcie_rp1 on end # RP #1 + device ref pcie_rp2 off end # RP #2 + device ref pcie_rp3 off end # RP #3 + device ref pcie_rp4 on end # RP #4: PCIEX1_1 + device ref pcie_rp5 on end # RP #5: PCIEX1_2 + device ref pcie_rp6 on end # RP #6: RTL8111 GbE NIC + device ref pcie_rp7 off end # RP #7 + device ref pcie_rp8 off end # RP #8 - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb index d726131..026bd81 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb @@ -5,22 +5,22 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM - device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) - device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) + device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" device pci 00.0 on end end end - device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller - device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) - device pci 1c.5 on end # ASMedia ASM1062 SATA Controller - device pci 1c.6 off end # Unused PCIe Port - device pci 1c.7 off end # Unused PCIe Port + device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller + device ref pcie_rp5 on end # PCIe x1 Port, x16 size (PCIEX16_2) + device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller + device ref pcie_rp7 off end # Unused PCIe Port + device ref pcie_rp8 off end # Unused PCIe Port - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 1b78b9b..9db03fc 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -6,22 +6,22 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM - device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) - device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) + device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" device pci 00.0 on end end end - device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller - device pci 1c.4 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.5 on end # ASMedia ASM1062 SATA Controller - device pci 1c.6 off end # Unused PCIe Port - device pci 1c.7 off end # Unused PCIe Port + device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller + device ref pcie_rp5 on end # RP #6: ASM1083 PCI Bridge + device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller + device ref pcie_rp7 off end # Unused PCIe Port + device ref pcie_rp8 off end # Unused PCIe Port - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port -- To view, visit https://review.coreboot.org/c/coreboot/+/79969?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Gerrit-Change-Number: 79969 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config
by Subrata Banik (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Shelley Chen, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Shelley Chen, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79936?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config ...................................................................... soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config This patch applies larger value for HEAP_SIZE config for platform that supports BMP_LOGO. TEST=Able to render a colored OEM splash screen w/o any boot hang. Change-Id: If34b1ef497d38ba561221c584aab5399cfc5de82 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/79936/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If34b1ef497d38ba561221c584aab5399cfc5de82 Gerrit-Change-Number: 79936 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt
by Felix Singer (Code Review) 13 Jan '24

13 Jan '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79968?usp=email ) Change subject: mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt ...................................................................... mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt Since all devicetrees from asus/maximus_iv_gene-z are using the reference names for PCI devices, remove the equivalent comments documenting their function. Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb 1 file changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/79968/1 diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 146ee6c..2642fbd 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -5,9 +5,9 @@ device domain 0 on subsystemid 0x1043 0x844d inherit - device ref host_bridge on end # Host bridge - device ref peg10 on end # PCIe bridge for discrete graphics - device ref igd on end # VGA controller + device ref host_bridge on end + device ref peg10 on end # discrete graphics + device ref igd on end chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM @@ -15,28 +15,28 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT - device ref gbe on # Intel Gigabit Ethernet + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe on subsystemid 0x1043 0x849c end - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on # HD audio controller + device ref ehci2 on end + device ref hda on subsystemid 0x1043 0x84dc end - device ref pcie_rp1 on end # PCIe port #1 - device ref pcie_rp2 off end # PCIe port #2 - device ref pcie_rp3 off end # PCIe port #3 - device ref pcie_rp4 off end # PCIe port #4 - device ref pcie_rp5 on end # PCIe port #5 - device ref pcie_rp6 on end # PCIe port #6 - device ref pcie_rp7 on end # PCIe port #7 - device ref pcie_rp8 off end # PCIe port #8 - device ref ehci1 on end # USB2 EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge + device ref pcie_rp1 on end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 off end + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel @@ -75,10 +75,10 @@ device pnp 2e.17 off end # GPIOA end end - device ref sata1 on end # SATA controller 1 - device ref smbus on end # SMBus - device ref sata2 off end # SATA controller 2 - device ref thermal off end # Thermal + device ref sata1 on end + device ref smbus on end + device ref sata2 off end + device ref thermal off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Gerrit-Change-Number: 79968 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/asus/p8x7x-series: Use chipset dt reference names
by Felix Singer (Code Review) 13 Jan '24

13 Jan '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79967?usp=email ) Change subject: mb/asus/p8x7x-series: Use chipset dt reference names ...................................................................... mb/asus/p8x7x-series: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 7 files changed, 83 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/79967/1 diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index cd4336f..192b4bd 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -21,9 +21,9 @@ # from runtime code) device domain 0 on - device ref host_bridge on end # Host bridge - device ref peg10 on end # PCIEX16_1 - device ref igd on end # iGPU + device ref host_bridge on end + device ref peg10 on end # PCIEX16_1 + device ref igd on end chip southbridge/intel/bd82x6x register "sata_interface_speed_support" = "0x3" @@ -34,32 +34,31 @@ register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device ref xhci on end # xHCI - device ref mei1 on end # MEI #1 - device ref mei2 off end # MEI #2 - device ref me_ide_r off end # ME IDE-R - device ref me_kt off end # ME KT - device ref gbe off end # Intel GbE - device ref ehci2 on end # EHCI #2 - device ref hda on end # HD Audio + device ref xhci on end + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on end + device ref hda on end - device ref pcie_rp1 off end # RP #1 - device ref pcie_rp2 off end # RP #2 - device ref pcie_rp3 off end # RP #3 - device ref pcie_rp4 off end # RP #4 - device ref pcie_rp5 off end # RP #5 - device ref pcie_rp6 off end # RP #6 - device ref pcie_rp7 off end # RP #7 - device ref pcie_rp8 off end # RP #8 + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref ehci1 on end # EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge - end - device ref sata1 on end # SATA (AHCI) - device ref smbus on end # SMBus - device ref sata2 off end # SATA (Legacy) - device ref thermal off end # Thermal + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on end + device ref sata1 on end # SATA (AHCI) + device ref smbus on end + device ref sata2 off end # SATA (Legacy) + device ref thermal off end end end end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 4de539b..4b7bb1c 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -2,21 +2,21 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 01.1 on end # PCIEX16_2 (electrical x8) - device pci 06.0 on end # PCIEX16_3 (electrical x4) + device ref peg11 on end # PCIEX16_2 (electrical x8) + device ref peg60 on end # PCIEX16_3 (electrical x4) subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1: PCIEX16_4 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: PCIEX1_1 - device pci 1c.5 on end # RP #6: 82574 GbE #1 - device pci 1c.6 on end # RP #7: 82574 GbE #2 - device pci 1c.7 off end # RP #8: - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # PCIEX1_1 + device ref pcie_rp6 on end # 82574 GbE #1 + device ref pcie_rp7 on end # 82574 GbE #2 + device ref pcie_rp8 off end + device ref pci_bridge on end + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index f20b49c..dbf1f35 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -5,16 +5,16 @@ subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: AR8161 GbE NIC - device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.6 on end # RP #7: PCIEX1_1 - device pci 1c.7 on end # RP #8: PCIEX1_2 + device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # AR8161 GbE NIC + device ref pcie_rp6 on end # ASM1083 PCI Bridge + device ref pcie_rp7 on end # PCIEX1_1 + device ref pcie_rp8 on end # PCIEX1_2 - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index c9fd784..5d688fd 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -11,18 +11,18 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 (PCIe x1 slot) - device pci 1c.5 on # PCIe Port #6 (RTL8111F GbE NIC) + device ref pcie_rp1 on end # PCIe x4 slot + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # PCIe x1 slot + device ref pcie_rp6 on # RTL8111F GbE NIC subsystemid 0x1849 0x1e1a device pci 00.0 on end # make onboard end - device pci 1c.6 on end # PCIe Port #7 (PCI slot via ASM1083) - device pci 1c.7 off end # PCIe Port #8 - device pci 1f.0 on # LPC bridge + device ref pcie_rp7 on end # PCI slot via ASM1083 + device ref pcie_rp8 off end + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index d7aea49..da34af3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -13,16 +13,16 @@ register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "true" - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 - device pci 1c.1 on end # PCIe Port 2 RTL8111F - device pci 1c.2 off end # PCIe Port 3 unused - device pci 1c.3 off end # PCIe Port 4 unused - device pci 1c.4 off end # PCIe Port 5 unused - device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 - device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA - device pci 1c.7 off end # PCIe Port 8 unused + device ref pcie_rp1 on end # PCIEX_16_3 + device ref pcie_rp2 on end # RTL8111F + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 on end # ASM1042 USB3 + device ref pcie_rp7 on end # ASM1061 eSATA + device ref pcie_rp8 off end - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb index 77484c7..043be06 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb @@ -3,19 +3,19 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x84ca inherit - device pci 01.1 on end # PCIEX_16_2 + device ref peg11 on end # PCIEX_16_2 chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x1 or x4) - device pci 1c.1 on end # PCIe Port 2 PCIEX_1_1 - device pci 1c.3 on end # PCIe Port 4 ASM1061 SATA or PCIEX_1_2 - device pci 1c.4 on end # PCIe Port 5 ASM1083 PCI Bridge - device pci 1c.6 on end # PCIe Port 7 Wi-Fi Go! - device pci 1c.7 on end # PCIe Port 8 ASM1042 USB3 + device ref gbe on end + device ref pcie_rp1 on end # PCIEX_16_3 (electrical x1 or x4) + device ref pcie_rp2 on end # PCIEX_1_1 + device ref pcie_rp4 on end # ASM1061 SATA or PCIEX_1_2 + device ref pcie_rp5 on end # ASM1083 PCI Bridge + device ref pcie_rp7 on end # Wi-Fi Go! + device ref pcie_rp8 on end # ASM1042 USB3 - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 6be23fa..0ae41b3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -6,16 +6,16 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: RTL8111 GbE NIC - device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.6 on end # RP #7: PCIEX1_1 - device pci 1c.7 on end # RP #8: PCIEX1_2 + device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # RTL8111 GbE NIC + device ref pcie_rp6 on end # ASM1083 PCI Bridge + device ref pcie_rp7 on end # PCIEX1_1 + device ref pcie_rp8 on end # PCIEX1_2 - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A -- To view, visit https://review.coreboot.org/c/coreboot/+/79967?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Gerrit-Change-Number: 79967 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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coreboot-gerrit January 2024