coreboot-gerrit January 2024

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[XL] Change in coreboot[main]: mb/arm/rdn2: Add support for Arm Neoverse N2
by Naresh Solanki (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, David Milosevic, Maximilian Brune, Patrick Rudolph, Paul Menzel. Hello Angel Pons, Arthur Heymans, David Milosevic, Lean Sheng Tan, Maximilian Brune, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79103?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/arm/rdn2: Add support for Arm Neoverse N2 ...................................................................... mb/arm/rdn2: Add support for Arm Neoverse N2 Add support for Arm Neoverse N2 Reference design. Based on Arm Neoverse N2 reference design Revision: Release D TEST=Build Arm Neoverse N2 & make sure there is no error. Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- A src/mainboard/arm/Kconfig A src/mainboard/arm/Kconfig.name A src/mainboard/arm/rdn2/Kconfig A src/mainboard/arm/rdn2/Kconfig.name A src/mainboard/arm/rdn2/Makefile.inc A src/mainboard/arm/rdn2/acpi.c A src/mainboard/arm/rdn2/board_info.txt A src/mainboard/arm/rdn2/bootblock.c A src/mainboard/arm/rdn2/bootblock_custom.S A src/mainboard/arm/rdn2/cbmem.c A src/mainboard/arm/rdn2/chip.h A src/mainboard/arm/rdn2/devicetree.cb A src/mainboard/arm/rdn2/dsdt.asl A src/mainboard/arm/rdn2/flash.fmd A src/mainboard/arm/rdn2/include/mainboard/addressmap.h A src/mainboard/arm/rdn2/mainboard.c A src/mainboard/arm/rdn2/media.c A src/mainboard/arm/rdn2/memlayout.ld A src/mainboard/arm/rdn2/mmio.c A src/mainboard/arm/rdn2/pptt.c 20 files changed, 1,184 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/79103/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Gerrit-Change-Number: 79103 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: acpi: Add IORT helper function
by Naresh Solanki (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Felix Held, Lance Zhao, Patrick Rudolph, Tim Wawrzynczak. Hello Angel Pons, Arthur Heymans, Cliff Huang, Felix Held, Lance Zhao, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79404?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: acpi: Add IORT helper function ...................................................................... acpi: Add IORT helper function Add helper function for ACPI IORT table. Change-Id: I7feaf306b5eea21bfc9a2e2a1a2c3ddc3c683c0b Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/acpi/Makefile.inc A src/acpi/acpi_iort.c M src/include/acpi/acpi_iort.h 3 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/79404/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7feaf306b5eea21bfc9a2e2a1a2c3ddc3c683c0b Gerrit-Change-Number: 79404 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: [RFC] region: Allow region_end() to return 64-bit numbers
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79906?usp=email ) Change subject: [RFC] region: Allow region_end() to return 64-bit numbers ...................................................................... Abandoned I like the idea to turn it into a region_last() (returning an inclusive offset) better. -- To view, visit https://review.coreboot.org/c/coreboot/+/79906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id261d72c58659f180ca8e5cb6c4bcfc3855ad903 Gerrit-Change-Number: 79906 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: device_util: GIC V3 Path update
by Naresh Solanki (Code Review) 14 Jan '24

14 Jan '24

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79972?usp=email ) Change subject: device_util: GIC V3 Path update ...................................................................... device_util: GIC V3 Path update Change-Id: Ib4004c1f1b854a54dfdf9eaa7f25583dec947302 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/device/device_util.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/79972/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index b37d1d9..d77bdfd 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -229,6 +229,9 @@ case DEVICE_PATH_MDIO: snprintf(buffer, sizeof(buffer), "MDIO: %02x", dev->path.mdio.addr); break; + case DEVICE_PATH_GICC_V3: + snprintf(buffer, sizeof(buffer), "GICV3: %02x", dev->path.gicc_v3.mpidr); + break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); -- To view, visit https://review.coreboot.org/c/coreboot/+/79972?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4004c1f1b854a54dfdf9eaa7f25583dec947302 Gerrit-Change-Number: 79972 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: [RFC] region: Introduce region_create() functions
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Jérémy Compostella, Martin L Roth, Maximilian Brune. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79905?usp=email ) Change subject: [RFC] region: Introduce region_create() functions ...................................................................... Patch Set 1: (4 comments) File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/c/coreboot/+/79905/comment/0056f63f_7faa6296 : PS1, Line 103: static inline int region_create_untrusted( > Does it make sense to mix the constructor and the checking of invalid input values? […] Certainly possible but we would have to repeat the check for different callers. And that this mustn't overflow is an implementation detail, kind of the contract (pre-condition) of region_create() with the assert() in place. Though, we have no way to enforce such contracts in C. https://review.coreboot.org/c/coreboot/+/79905/comment/4deac652_ee637d70 : PS1, Line 104: struct region *r, unsigned long long offset, unsigned long long size) > Is there a specific reason why you use "unsigned long long" type? It's the biggest there is. The idea is to ensure that values are not accidentally truncated when calling the function. The _unstrusted function should work 100%ly no matter what the caller looks like. https://review.coreboot.org/c/coreboot/+/79905/comment/dbb41d18_081a2f40 : PS1, Line 106: offset > SIZE_MAX || size > SIZE_MAX > I am puzzled. […] size_t/SIZE_MAX are implementation defined. I'm rather sure that compiled for x86_32 size_t is 32 bits wide. Still, somebody would call the function with a value >= 4G. (C compilers don't warn about implicit truncation, and static analyzers often only do so when they have reason to believe that the value is too big.) File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/79905/comment/25f26489_20406243 : PS1, Line 334: if (region_create_untrusted( > If I understand correctly the only real difference between `region_create` and `region_create_untrus […] These regions can come from the command line. It's a minor difference with the default behavior of assert(). Though, if I'd have a typo in my command line, I'd prefer a proper error message over an annoying "assertion failed". And generally, seeing command-line input as unstrusted seems right IMO. -- To view, visit https://review.coreboot.org/c/coreboot/+/79905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Gerrit-Change-Number: 79905 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sun, 14 Jan 2024 10:54:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.inc: Enable Wcast-function-type command option
by Elyes Haouas (Code Review) 14 Jan '24

14 Jan '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79944?usp=email ) Change subject: Makefile.inc: Enable Wcast-function-type command option ...................................................................... Makefile.inc: Enable Wcast-function-type command option Clang enables by default Wcast-function-type. Enable it for gcc. Change-Id: I6aebe41e325dea74d52e396e27eec601bdcfd3a4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/79944/1 diff --git a/Makefile.inc b/Makefile.inc index 23f56a4..37ae763 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -494,7 +494,7 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition -CFLAGS_common += -Wdangling-else -Wmissing-include-dirs +CFLAGS_common += -Wdangling-else -Wmissing-include-dirs -Wcast-function-type CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/79944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6aebe41e325dea74d52e396e27eec601bdcfd3a4 Gerrit-Change-Number: 79944 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel: Use boolean for pcie_hotplug_map attribute
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79932?usp=email ) Change subject: sb/intel: Use boolean for pcie_hotplug_map attribute ...................................................................... sb/intel: Use boolean for pcie_hotplug_map attribute Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/pciehp.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h 5 files changed, 10 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 30c2675..66d5cb1 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -65,7 +65,7 @@ int docking_supported; - uint8_t pcie_hotplug_map[8]; + bool pcie_hotplug_map[8]; /* Ports which can be routed to either EHCI or xHCI. */ uint32_t xhci_switchable_ports; diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index b549619..d5766d8 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -4,10 +4,11 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/pci.h> +#include <stdbool.h> #include "pciehp.h" -void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number) +void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number) { int port; int have_hotplug = 0; diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h index b4e65c4..beb210c 100644 --- a/src/southbridge/intel/common/pciehp.h +++ b/src/southbridge/intel/common/pciehp.h @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stdbool.h> + #ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H #define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H -void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number); +void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number); void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus); #endif diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index ec7b977..d52a0c2 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#include <stdbool.h> #include <stdint.h> enum { @@ -73,7 +74,7 @@ uint8_t scale : 2; } pcie_power_limits[6]; - uint8_t pcie_hotplug_map[8]; + bool pcie_hotplug_map[8]; /* Additional LPC IO decode ranges */ uint32_t gen1_dec; diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ae31d4f..f12a67e 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include <stdbool.h> #include <stdint.h> enum { @@ -59,7 +60,7 @@ uint8_t scale : 2; } pcie_power_limits[6]; - uint8_t pcie_hotplug_map[8]; + bool pcie_hotplug_map[8]; /* Additional LPC IO decode ranges */ uint32_t gen1_dec; -- To view, visit https://review.coreboot.org/c/coreboot/+/79932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba Gerrit-Change-Number: 79932 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/asrock/b75m-itx: Use chipset dt reference names
by Kevin Keijzer (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Felix Singer. Kevin Keijzer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79971?usp=email ) Change subject: mb/asrock/b75m-itx: Use chipset dt reference names ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Gerrit-Change-Number: 79971 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Janik Haag Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sun, 14 Jan 2024 09:34:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel: Use boolean for pcie_hotplug_map attribute
by Patrick Rudolph (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Arthur Heymans, Felix Singer. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79932?usp=email ) Change subject: sb/intel: Use boolean for pcie_hotplug_map attribute ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba Gerrit-Change-Number: 79932 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 14 Jan 2024 08:23:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Patrick Rudolph (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lance Zhao, Matt DeVillier, Nico Huber, Tim Chu, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 14 Jan 2024 08:19:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2024