coreboot-gerrit January 2024

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[S] Change in coreboot[main]: tree: More use accessor functions for struct region fields
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79955?usp=email to look at the new patch set (#2). Change subject: tree: More use accessor functions for struct region fields ...................................................................... tree: More use accessor functions for struct region fields Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c 5 files changed, 16 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79955/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Gerrit-Change-Number: 79955 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: [RFC] region: Introduce region_create() functions
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Jérémy Compostella, Martin L Roth, Maximilian Brune. Hello Jérémy Compostella, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79905?usp=email to look at the new patch set (#4). Change subject: [RFC] region: Introduce region_create() functions ...................................................................... [RFC] region: Introduce region_create() functions This introduces two new functions to create region objects. They allow us to check for integer overflows (region_create_untrusted()) or assert their absence (region_create()). Again, FIT payload support is left out, as it doesn't use the region API (only the struct). Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/commonlib/include/commonlib/region.h M src/cpu/x86/smm/smm_module_loader.c M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/cpu/x86/smm.h M src/lib/fmap.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7280/soc.c M util/cbfstool/cbfstool.c M util/cbfstool/cse_serger.c 10 files changed, 82 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/79905/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Gerrit-Change-Number: 79905 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/testing: Add a few build tests using all cores
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Martin L Roth. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77329?usp=email ) Change subject: util/testing: Add a few build tests using all cores ...................................................................... Patch Set 3: (1 comment) File util/testing/Makefile.inc: https://review.coreboot.org/c/coreboot/+/77329/comment/0c98095a_95a9283c : PS3, Line 124: --exitcode Is it necessary to let make abort here? I just noticed this because Jenkins made me believe that only a single board would be failing (Skyrim), so I assumed everything else passed and made some wrong (not too worry about) assumptions. -- To view, visit https://review.coreboot.org/c/coreboot/+/77329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51e39bc1ce6b9b7c257d0170ce3d2b5ab99d35df Gerrit-Change-Number: 77329 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sun, 14 Jan 2024 17:03:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: tree: More use accessor functions for struct region fields
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79955?usp=email ) Change subject: tree: More use accessor functions for struct region fields ...................................................................... tree: More use accessor functions for struct region fields Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/soc.c 5 files changed, 16 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79955/1 diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index b3d7c69..ec3eef6 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -221,8 +221,8 @@ size_t addr, len, gran_value, total_ranges, range; bool granularity_64k = true; /* assume 64k granularity */ - addr = region->offset; - len = region->size; + addr = region_offset(region); + len = region_sz(region); reg32 = pci_read_config32(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START); rom_base = WORD_TO_DWORD_UPPER(reg32); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 7d9ef35..b49acae 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -85,13 +85,17 @@ if (vboot_is_firmware_slot_a(ctx)) { fname = "apu/amdfw_a"; - if (!fmap_locate_area("FW_MAIN_A", &fw_slot)) - map_base = rdev_mmap(boot_device_ro(), fw_slot.offset, fw_slot.size); + if (!fmap_locate_area("FW_MAIN_A", &fw_slot)) { + map_base = rdev_mmap(boot_device_ro(), + region_offset(&fw_slot), region_sz(&fw_slot)); + } } else { fname = "apu/amdfw_b"; - if (!fmap_locate_area("FW_MAIN_B", &fw_slot)) - map_base = rdev_mmap(boot_device_ro(), fw_slot.offset, fw_slot.size); + if (!fmap_locate_area("FW_MAIN_B", &fw_slot)) { + map_base = rdev_mmap(boot_device_ro(), + region_offset(&fw_slot), region_sz(&fw_slot)); + } } if (!map_base) { @@ -118,7 +122,7 @@ psp_dir_addr = ef_table->new_psp_directory; bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + - (uint32_t)map_base - fw_slot.offset); + (uint32_t)map_base - region_offset(&fw_slot)); if (*psp_dir_in_spi != PSP_COOKIE) { printk(BIOS_ERR, "PSP Directory address is not correct.\n"); cbfs_unmap(amdfw_location); @@ -129,7 +133,7 @@ if (bios_dir_addr) { bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + - (uint32_t)map_base - fw_slot.offset); + (uint32_t)map_base - region_offset(&fw_slot)); if (*bios_dir_in_spi != BHD_COOKIE) { printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); cbfs_unmap(amdfw_location); diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index cfe3e2a..56fd3bf 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -106,8 +106,8 @@ ddr_region->size = ddr_size * MiB; /* Use DDR info to configure MMU */ - qc_mmu_dram_config_post_dram_init((void *)ddr_region->offset, - (size_t)ddr_region->size); + qc_mmu_dram_config_post_dram_init( + (void *)(uintptr_t)region_offset(ddr_region), region_sz(ddr_region)); } static void write_qclib_log_to_cbmemc(struct qclib_cb_if_table_entry *te) diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index d8df98a..cef7e8f 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -12,7 +12,7 @@ void *start = NULL; void *end = NULL; - ram_range(dev, 0, (uintptr_t)ddr_region->offset, ddr_region->size); + ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region)); reserved_ram_range(dev, 1, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop)); reserved_ram_range(dev, 2, (uintptr_t)_dram_soc, REGION_SIZE(dram_soc)); if (soc_modem_carve_out(&start, &end)) diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index e6dbf21..a972d6e 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -19,7 +19,7 @@ void *start = NULL; void *end = NULL; - ram_range(dev, 0, (uintptr_t)ddr_region->offset, ddr_region->size); + ram_range(dev, 0, (uintptr_t)region_offest(ddr_region), region_sz(ddr_region)); reserved_ram_range(dev, 1, (uintptr_t)_dram_soc, REGION_SIZE(dram_soc)); reserved_ram_range(dev, 2, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan)); reserved_ram_range(dev, 3, (uintptr_t)_dram_wpss, REGION_SIZE(dram_wpss)); -- To view, visit https://review.coreboot.org/c/coreboot/+/79955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Gerrit-Change-Number: 79955 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: [RFC] region: Introduce region_create() functions
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Jérémy Compostella, Martin L Roth, Maximilian Brune. Hello Jérémy Compostella, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79905?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Martin L Roth, Verified+1 by build bot (Jenkins) Change subject: [RFC] region: Introduce region_create() functions ...................................................................... [RFC] region: Introduce region_create() functions This introduces two new functions to create region objects. They allow us to check for integer overflows (region_create_untrusted()) or assert their absence (region_create()). Again, FIT payload support is left out, as it doesn't use the region API (only the struct). Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/commonlib/include/commonlib/region.h M src/cpu/x86/smm/smm_module_loader.c M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/cpu/x86/smm.h M src/lib/fmap.c M src/soc/qualcomm/common/qclib.c M util/cbfstool/cbfstool.c M util/cbfstool/cse_serger.c 9 files changed, 81 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/79905/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Gerrit-Change-Number: 79905 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: mb/sifive: Add Hifive Unmatched mainboard
by Maximilian Brune (Code Review) 14 Jan '24

14 Jan '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79954?usp=email ) Change subject: mb/sifive: Add Hifive Unmatched mainboard ...................................................................... mb/sifive: Add Hifive Unmatched mainboard Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53 --- A src/mainboard/sifive/hifive-unmatched/Kconfig A src/mainboard/sifive/hifive-unmatched/Kconfig.name A src/mainboard/sifive/hifive-unmatched/board_info.txt A src/mainboard/sifive/hifive-unmatched/cbfs_spi.c A src/mainboard/sifive/hifive-unmatched/default.fmd A src/mainboard/sifive/hifive-unmatched/devicetree.cb A src/mainboard/sifive/hifive-unmatched/fixup_fdt.c A src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts A src/mainboard/sifive/hifive-unmatched/mainboard.c A src/mainboard/sifive/hifive-unmatched/romstage.c 12 files changed, 1,234 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79954/1 diff --git a/src/mainboard/sifive/hifive-unmatched/Kconfig b/src/mainboard/sifive/hifive-unmatched/Kconfig new file mode 100644 index 0000000..5e2a064f --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SIFIVE_HIFIVE_UNMATCHED + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_SIFIVE_FU740 + select BOARD_ROMSIZE_KB_32768 + select MISSING_BOARD_RESET + select FLATTENED_DEVICE_TREE + select SPI_FLASH + select SPI_FLASH_ISSI + select SPI_SDCARD + +config HEAP_SIZE + default 0x10000 #TODO + +config MAINBOARD_DIR + default "sifive/hifive-unmatched" + +config MAINBOARD_PART_NUMBER + default "HiFive Unmatched" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" + +endif diff --git a/src/mainboard/sifive/hifive-unmatched/Kconfig.name b/src/mainboard/sifive/hifive-unmatched/Kconfig.name new file mode 100644 index 0000000..bbba82c --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIFIVE_HIFIVE_UNMATCHED + bool "HiFive Unmatched" diff --git a/src/mainboard/sifive/hifive-unmatched/board_info.txt b/src/mainboard/sifive/hifive-unmatched/board_info.txt new file mode 100644 index 0000000..e48ba27 --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/board_info.txt @@ -0,0 +1,6 @@ +Category: eval +ROM package: SOIC-16 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Board URL: https://www.crowdsupply.com/sifive/hifive-unmatched diff --git a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c new file mode 100644 index 0000000..122fa80 --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is basically drivers/spi/cbfs_spi.cb but the boot device is not known at build time + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/mmio.h> +#include <lib.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/spi.h> +#include <spi_flash.h> +#include <spi_sdcard.h> +#include <stdint.h> +#include <symbols.h> +#include <timer.h> + +// There are two different means of accessing the SPI flash. +// They are controled by the fctrl register. +// 1. memory mapped access +// 2. FIFO based access + +/* follow is the FSBL boot device defined by ZSBL of sifive + * FSBL replaced by bootblock of coreboot + * MSEL_SPInx1 -> test if boot from memory-mapped on SPIn + * MSEL_SPInx4 -> test if boot from memory-mapped on QPIn + * MSEL_SPInSD -> test if boot from sdcard mount on SPIn */ +#define MSEL_SPI0x1(m) (((m) == 5) || ((m) == 14)) +#define MSEL_SPI0x4(m) (((m) == 6) || ((m) == 10) || ((m) == 15)) +#define MSEL_SPI1x1(m) ((m) == 12) +#define MSEL_SPI1x4(m) (((m) == 7) || ((m) == 13)) +#define MSEL_SPI1SD(m) ((m) == 8) +#define MSEL_SPI2x1(m) ((m) == 9) +#define MSEL_SPI2SD(m) ((m) == 11) + +#define MSEL_ACCESS_METHOD_MMAP(m) ((m == 5) || (m == 6) || (m == 7) || (m == 10) || (m == 13)) + +// probably something for devicetree +struct fu740_spi_config fu740_spi_configs[] = { + { 0 }, + { + .freq = 10*1000*1000, + }, + { 0 }, +}; + +static struct spi_sdcard spi2_sdcard; //TODO initialize SPI2 +//static struct spi_flash spi0_flash; +//static struct spi_flash spi1_flash; +static struct spi_flash spi_flash; +static bool spi_flash_init_done; + +static ssize_t sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + spi_sdcard_read(&spi2_sdcard, dest, offset, count); + return count; +} + +static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) +{ + if (spi_flash_read(&spi_flash, offset, size, b)) + return -1; + return size; +} + +static ssize_t spi_writeat(const struct region_device *rd, const void *b, + size_t offset, size_t size) +{ + if (spi_flash_write(&spi_flash, offset, size, b)) + return -1; + return size; +} + +static ssize_t spi_eraseat(const struct region_device *rd, size_t offset, size_t size) +{ + if (spi_flash_erase(&spi_flash, offset, size)) + return -1; + return size; +} + +static const struct region_device_ops sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = sd_readat, +}; + +static const struct region_device_ops spi_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = spi_readat, + .writeat = spi_writeat, + .eraseat = spi_eraseat, +}; + +//TODO using postram cache means that all spi transistions are transfered to actual memory. Native memory mapping obviously doesnt have that problem. That can however only happen if memory has been initialized before accessing the boot device. So no CBFS access before boot. +//static struct mem_pool mem_cbfs_cache = +// MEM_POOL_INIT(_postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); +//static struct mmap_helper_region_device spi_mdev = +// MMAP_HELPER_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE, &mem_cbfs_cache); + +static struct mmap_helper_region_device spi_mdev = + MMAP_HELPER_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache); + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_DEV_INIT(&sd_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache); + +void boot_device_init(void) +{ + printk(BIOS_DEBUG, "%s 0\n", __func__); + if (spi_flash_init_done == true) + return; + + uint32_t m = read32((uint32_t *)FU740_MSEL); + // Pass the information of the flash read operation to the spi controller + //.pad_cnt = 6, + if (MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) { + //config.ffmt_config.data_proto = FU740_SPI_PROTO_Q; + //config.ffmt_config.cmd_code = 0x6B; // Quad output read + //.cmd_code = 0xec, + } + if (MSEL_SPI1x1(m)) { + printk(BIOS_DEBUG, "%s 1\n", __func__); + fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_S; + fu740_spi_configs[1].ffmt_config.cmd_code = 0x03; // Normal read + //TODO SPI1x1 is always using programmed IO (FIFO)? (memory map did not work...) + if (spi_flash_probe(1, 0, &spi_flash)) { + printk(BIOS_EMERG, "failed to init SPI flash\n"); + return; + } + // initialize soc spi controller + //if (fu740_spi_setup(&spi1_flash.spi) == -1) { + // printk(BIOS_EMERG, "failed to configure mmap for SPI flash\n"); + //} + //hexdump((void*)0x10041000, 0x100); + //hexdump((void*)0x30000000, 0x100); + printk(BIOS_DEBUG, "%s 2\n", __func__); + } else if (MSEL_SPI2SD(m)) { + spi_sdcard_init(&spi2_sdcard, 2, 0); + } else { + die("Wrong configuration of MSEL\n"); + } + + spi_flash_init_done = true; +} + +/* Return the CBFS boot device. */ +const struct region_device *boot_device_ro(void) +{ + if (spi_flash_init_done != true) + return NULL; + + uint32_t m = read32((uint32_t *)FU740_MSEL); + + if (MSEL_SPI2SD(m) || MSEL_SPI1SD(m)) + return &sd_mdev.rdev; + return &spi_mdev.rdev; +} + +//const struct spi_flash *boot_device_spi_flash(void) +//{ +// boot_device_init(); +// +// if (spi_flash_init_done != true) +// return NULL; +// +// return &spi_flash; +//} diff --git a/src/mainboard/sifive/hifive-unmatched/default.fmd b/src/mainboard/sifive/hifive-unmatched/default.fmd new file mode 100644 index 0000000..322776d --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/default.fmd @@ -0,0 +1,7 @@ +FLASH@0 32M { + BIOS@0 32M { + BOOTBLOCK@0 128K + FMAP 512 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/sifive/hifive-unmatched/devicetree.cb b/src/mainboard/sifive/hifive-unmatched/devicetree.cb new file mode 100644 index 0000000..3d52b54 --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/devicetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/sifive/fu740 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/sifive/hifive-unmatched/fixup_fdt.c b/src/mainboard/sifive/hifive-unmatched/fixup_fdt.c new file mode 100644 index 0000000..ed24ee3 --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/fixup_fdt.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <soc/otp.h> +#include <soc/sdram.h> +#include <cbfs.h> +#include <device_tree.h> +#include <bootstate.h> +#include <mcall.h> + +static void do_fixup_mac(struct device_tree_node *node) +{ + uint32_t serial = otp_read_serial(); + static unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 }; + if (serial != ~0) { + mac[5] |= (serial >> 0) & 0xff; + mac[4] |= (serial >> 8) & 0xff; + mac[3] |= (serial >> 16) & 0xff; + } + dt_add_bin_prop(node, "local-mac-address", mac, 6); +} + +static void fixup_mac(struct device_tree_node *parent) +{ + struct device_tree_property *prop; + const char *name = "local-mac-address"; + + list_for_each(prop, parent->properties, list_node) { + if (!strcmp(name, prop->prop.name)) + do_fixup_mac(parent); + } + + struct device_tree_node *child; + list_for_each(child, parent->children, list_node) { + fixup_mac(child); + } +} + +static void do_fixup_memory(struct device_tree_node *node) +{ + u64 addrs[1], sizes[1]; + addrs[0] = 0x80000000; + sizes[0] = sdram_size(); + dt_add_reg_prop(node, addrs, sizes, 1, 2, 2); +} + +static void fixup_memory(struct device_tree_node *parent) +{ + struct device_tree_property *prop; + const char *name = "device_type"; + const char *value = "memory"; + + list_for_each(prop, parent->properties, list_node) { + if (!strcmp(name, prop->prop.name)) { + if (!strcmp(value, (char *)prop->prop.data)) + do_fixup_memory(parent); + } + } + + struct device_tree_node *child; + list_for_each(child, parent->children, list_node) { + fixup_memory(child); + } +} + +static void fixup_fdt(void *unused) +{ + printk(BIOS_DEBUG, "fix up FDT\n"); + + void *fdt_rom; + struct device_tree *tree; + + /* load flat dt from cbfs */ + fdt_rom = cbfs_map("fallback/DTB", NULL); + + if (fdt_rom == NULL) { + printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); + return; + } + + /* Expand DT into a tree */ + tree = fdt_unflatten(fdt_rom); + + /* fixup tree */ + fixup_mac(tree->root); + fixup_memory(tree->root); + + /* convert the tree to a flat dt */ + void *dt = malloc(dt_flat_size(tree)); + + if (dt == NULL) { + printk(BIOS_ERR, "Unable to allocate memory for flat device tree\n"); + return; + } + + dt_flatten(tree, dt); + + /* update HLS */ + for (int i = 0; i < CONFIG_MAX_CPUS; i++) + OTHER_HLS(i)->fdt = dt; +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, fixup_fdt, NULL); diff --git a/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi b/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi new file mode 100644 index 0000000..823240c --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu740-c000", "sifive,fu740"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = &eth0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,bullet0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&ccache>; + reg = <0x0>; + riscv,isa = "rv64imac"; + // the S7 core does not support Supervisor mode and has no FPU + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + // clint is mainly used by openSBI and not the OS, since interrupts-extended currently only + // contains machine mode interrupts which the OS will ignore if not running in machine mode + clint: clint@2000000 { + compatible = "riscv,clint0"; + //TODO Add RISCV_M_SOFT_IRQ and RISCV_M_TIME_IRQ macros for better readability + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + }; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <69>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu740-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <39>; + clocks = <&prci 7>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <40>; + clocks = <&prci 7>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci 7>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@10031000 { + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10031000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <53>; + clocks = <&prci 7>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <41>; + clocks = <&prci 7>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <42>; + clocks = <&prci 7>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@10050000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <43>; + clocks = <&prci 7>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <55>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci 2>, + <&prci 2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + phandle = <0x13>; //TODO remove + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <44>, <45>, <46>, <47>; + clocks = <&prci 7>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <48>, <49>, <50>, <51>; + clocks = <&prci 7>; + #pwm-cells = <3>; + status = "disabled"; + }; + ccache: cache-controller@2010000 { + compatible = "sifive,fu740-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <19>, <21>, <22>, <20>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic0>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>, <31>, <32>, <33>, <34>, <35>, <36>, + <37>, <38>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&prci 7>; + status = "disabled"; + }; + pcie@e00000000 { + compatible = "sifive,fu740-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0xe 0x00000000 0x0 0x80000000>, + <0xd 0xf0000000 0x0 0x10000000>, + <0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + //TODO + //ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ + // <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ + // <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ + // <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000 0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x10000000 0xc3000000 0x20 0x00 0x20 0x00 0x20 0x00>; + num-lanes = <0x8>; + interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci 8>; + pwren-gpios = <&gpio 5 0>; + reset-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; + }; +}; diff --git a/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts b/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts new file mode 100644 index 0000000..715ec1b --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/include/ "fu740-c000.dtsi" + +/ { + model = "SiFive HiFive Unmatched A00"; + compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740"; + + cpus { + //TODO replace with CLOCK_FREQUENCY macro that is used in both code and here to have a single source of truth + timebase-frequency = <1000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x4 0x00000000>; + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + vcc-supply = <&vdd_bpro>; + interrupt-parent = <&gpio>; + interrupts = <6 8>; + }; + + eeprom@54 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x54>; + label = "board-id"; + vcc-supply = <0x10>; + pagesize = <16>; + read-only; + size = <256>; + }; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio>; + interrupts = <1 8>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + }; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + + regulators { + vdd_bcore: bcores-merged { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-min-microamp = <4800000>; + regulator-max-microamp = <4800000>; + regulator-always-on; + }; + + vdd_bpro: bpro { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <2400000>; + regulator-max-microamp = <2400000>; + regulator-always-on; + }; + + vdd_bperi: bperi { + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1060000>; + regulator-min-microamp = <1500000>; + regulator-max-microamp = <1500000>; + regulator-always-on; + }; + + vdd_bmem_bio: bmem-bio-merged { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <3000000>; + regulator-always-on; + }; + + vdd_ldo1: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ldo2: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ldo3: ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ldo4: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_ldo5: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ldo6: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ldo7: ldo7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ldo8: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ld09: ldo9 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + vdd_ldo10: ldo10 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_ldo11: ldo11 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + }; + }; + +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&spi0 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + gpios = <0x11 0x0f 0x01>; + }; +}; + +&eth0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", + "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", + "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", + "EN_VDD_SD", "SD_CD"; +}; diff --git a/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts b/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts new file mode 100644 index 0000000..82b5830 --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/include/ "fu740-c000.dtsi" + +/ { + model = "SiFive HiFive Unmatched A00"; + compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740"; + + cpus { + //TODO replace with CLOCK_FREQUENCY macro that is used in both code and here to have a single source of truth + timebase-frequency = <1000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x4 0x00000000>; + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + vcc-supply = <&vdd_bpro>; + interrupt-parent = <&gpio>; + interrupts = <6 3>; + }; + + eeprom@54 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x54>; + label = "board-id"; + pagesize = <16>; + read-only; + size = <256>; + }; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio>; + interrupts = <1 3>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + }; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + + regulators { + vdd_bcore: bcores-merged { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-min-microamp = <4800000>; + regulator-max-microamp = <4800000>; + regulator-always-on; + }; + + vdd_bpro: bpro { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <2400000>; + regulator-max-microamp = <2400000>; + regulator-always-on; + }; + + vdd_bperi: bperi { + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1060000>; + regulator-min-microamp = <1500000>; + regulator-max-microamp = <1500000>; + regulator-always-on; + }; + + vdd_bmem_bio: bmem-bio-merged { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <3000000>; + regulator-always-on; + }; + + vdd_ldo1: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ldo2: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ldo3: ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ldo4: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_ldo5: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ldo6: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ldo7: ldo7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ldo8: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ld09: ldo9 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + vdd_ldo10: ldo10 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_ldo11: ldo11 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + }; + }; + +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&spi0 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +&eth0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", + "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", + "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", + "EN_VDD_SD", "SD_CD"; +}; diff --git a/src/mainboard/sifive/hifive-unmatched/mainboard.c b/src/mainboard/sifive/hifive-unmatched/mainboard.c new file mode 100644 index 0000000..2b4c659 --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/mainboard.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sifive/hifive-unmatched/romstage.c b/src/mainboard/sifive/hifive-unmatched/romstage.c new file mode 100644 index 0000000..edab59f --- /dev/null +++ b/src/mainboard/sifive/hifive-unmatched/romstage.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/tables.h> // write_tables() +#include <cbmem.h> +#include <console/console.h> +#include <console/streams.h> +#include <console/uart.h> +#include <hardwaremain.h> +#include <program_loading.h> +#include <soc/clock.h> +#include <soc/sdram.h> +#include <symbols.h> // _dram symbol +#include <mcall.h> // HLS() +#include <lib.h> // hexdump +#include <device_tree.h> // fdt_unflatten +#include <cbfs.h> // cbfs_map +#include <arch/encoding.h> // write_csr +#include <soc/gpio.h> // gpio_init +#include <delay.h> +#include <romstage_common.h> +#include <soc/addressmap.h> + +void __noreturn romstage_main(void) +{ + //TODO see if it makes any difference and check doc +#define CSR_U74_FEATURE_DISABLE 0x7c1 + write_csr(0x7c1, 0); + + console_init(); + + clock_init(); + //delay(2); //TODO see if that works or if we need to put it below uart_init? Maybe uart_init is just taking too long? + + if (CONFIG(CONSOLE_SERIAL)) + uart_init(get_uart_for_console()); + + printk(BIOS_SPEW, "%s: after uart_init\n", __func__); + //delay(2); //TODO see if that works or if we need to put it below uart_init? Maybe uart_init is just taking too long? + + if (get_log_level() == BIOS_SPEW) { + // print FDT supplied by ROM code + // /TODO in order to unflatten the fdt from zsbl I need malloc. But malloc currently is tied to the heap which in turn is tied to actual dram. For testing use cbfs_cache as backend for malloc to circuimvent this (works suprisingly flawless). //TODO maybe just add romstage to ENV_HAS_HEAP + //printk(BIOS_SPEW, "fdt: %p\n", HLS()->fdt); + //struct device_tree *tree = fdt_unflatten(HLS()->fdt); + //dt_print_node(tree->root); + } + +#define DDR_SIZE (16UL * 1024UL * 1024UL * 1024UL) + //TODO test if the common version works + //sdram_init((u32 *)FU740_DDRCTRL, (u64 *)FU740_PHYSICAL_FILTER, FU740_DRAM, DDR_SIZE); + sdram_init(); + + cbmem_initialize_empty(); + + // need to setup devices because bootmem will get the memory ranges by enemurating the devices + + // Schedule the static boot state entries. + //boot_state_schedule_static_entries(); + + //bs_walk_state_machine(); + + //die("Boot state machine failure.\n"); + + //// write_tables will set up bootmem which is needed for payload_load() to figure out where it is allowed to place the payload + //write_tables(); + + //bootmem_dump_ranges(); + //printk(BIOS_DEBUG, "%s: 1", __func__); + //payload_load(); + //bootmem_dump_ranges(); + //printk(BIOS_DEBUG, "%s: 2", __func__); + //payload_run(); + run_ramstage(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53 Gerrit-Change-Number: 79954 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[main]: soc/sifive/fu740: Add fu740 soc
by Maximilian Brune (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79953?usp=email ) Change subject: soc/sifive/fu740: Add fu740 soc ...................................................................... soc/sifive/fu740: Add fu740 soc Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ibae3b8f1a534c4a5a8b26e723be7d59a92f788bf --- M src/Kconfig A src/soc/sifive/fu740/Makefile.inc A src/soc/sifive/fu740/TODO A src/soc/sifive/fu740/cbmem.c A src/soc/sifive/fu740/chip.c A src/soc/sifive/fu740/clint.c A src/soc/sifive/fu740/clock.c A src/soc/sifive/fu740/ddrregs.c A src/soc/sifive/fu740/gpio.c A src/soc/sifive/fu740/include/soc/addressmap.h A src/soc/sifive/fu740/include/soc/clock.h A src/soc/sifive/fu740/include/soc/gpio.h A src/soc/sifive/fu740/include/soc/otp.h A src/soc/sifive/fu740/include/soc/sdram.h A src/soc/sifive/fu740/include/soc/spi.h A src/soc/sifive/fu740/include/soc/ux00ddr.h A src/soc/sifive/fu740/memlayout.ld A src/soc/sifive/fu740/otp.c A src/soc/sifive/fu740/regconfig-ctl.h A src/soc/sifive/fu740/regconfig-phy.h A src/soc/sifive/fu740/sdram.c A src/soc/sifive/fu740/spi.c A src/soc/sifive/fu740/spi_internal.h A src/soc/sifive/fu740/uart.c 24 files changed, 4,655 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/79953/1 diff --git a/src/Kconfig b/src/Kconfig index 5cb9a1a..511d709 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -245,7 +245,7 @@ config SEPARATE_ROMSTAGE bool "Build a separate romstage" - default y + default n # TODO fix help Build a separate romstage that is loaded by bootblock. With this option disabled the romstage sources are linked inside the bootblock diff --git a/src/soc/sifive/fu740/Makefile.inc b/src/soc/sifive/fu740/Makefile.inc new file mode 100644 index 0000000..7022fb0 --- /dev/null +++ b/src/soc/sifive/fu740/Makefile.inc @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifdef CONFIG_SOC_SIFIVE_FU740 + +CPPFLAGS_common += -Isrc/soc/sifive/fu740/include + +bootblock-y += uart.c +bootblock-y += clint.c +bootblock-y += spi.c +bootblock-y += sdram.c +bootblock-y += cbmem.c +bootblock-y += otp.c +bootblock-y += clock.c +bootblock-y += ddrregs.c +bootblock-y += chip.c +bootblock-y += gpio.c + +ramstage-y += uart.c +ramstage-y += clint.c +ramstage-y += spi.c +ramstage-y += sdram.c +ramstage-y += cbmem.c +ramstage-y += otp.c +ramstage-y += clock.c +ramstage-y += chip.c + +$(objcbfs)/romstage.bin: $(objcbfs)/romstage.raw.bin + @printf " GPT $(notdir $(@))\n" + @util/riscv/sifive-gpt.py $< $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf " GPT $(notdir $(@))\n" + @util/riscv/sifive-gpt.py $< $@ + +endif diff --git a/src/soc/sifive/fu740/TODO b/src/soc/sifive/fu740/TODO new file mode 100644 index 0000000..c7e03a5 --- /dev/null +++ b/src/soc/sifive/fu740/TODO @@ -0,0 +1,52 @@ +1. put more into common code (e.g. sdram.c) +2. refactor SPI code. It works but there are quite some TODO left and it also currently only supports 1 MSEL configuration +3. sometimes PCIe is not working with the following error message in Linux: +[ 0.619711] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 +[ 0.621521] fu740-pcie e00000000.pcie: host bridge /soc/pcie@e00000000 ranges: +[ 0.621603] fu740-pcie e00000000.pcie: IO 0x0060080000..0x006008ffff -> 0x0060080000 +[ 0.621659] fu740-pcie e00000000.pcie: MEM 0x0060090000..0x007fffffff -> 0x0060090000 +[ 0.621685] fu740-pcie e00000000.pcie: MEM 0x2000000000..0x3fffffffff -> 0x2000000000 +[ 0.727890] fu740-pcie e00000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 4K, limit 4096G +[ 0.828041] fu740-pcie e00000000.pcie: PCIe Gen.1 x8 link up +[ 1.828944] fu740-pcie e00000000.pcie: Phy link never came up +[ 1.828961] fu740-pcie e00000000.pcie: error: link did not start at new speed +[ 1.829142] ------------[ cut here ]------------ +[ 1.829152] WARNING: CPU: 2 PID: 1 at drivers/pci/controller/dwc/pcie-fu740.c:232 fu740_pcie_start_link+0x1b4/0x1ce +[ 1.829191] Modules linked in: +[ 1.829205] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 6.5.0-9-generic #9.1-Ubuntu +[ 1.829215] Hardware name: SiFive HiFive Unmatched A00 (DT) +[ 1.829221] epc : fu740_pcie_start_link+0x1b4/0x1ce +[ 1.829234] ra : fu740_pcie_start_link+0x1ca/0x1ce +[ 1.829247] epc : ffffffff806fa1ac ra : ffffffff806fa1c2 sp : ffffffc800023b30 +[ 1.829256] gp : ffffffff822602d8 tp : ffffffd88027b600 t0 : ffffffff82029670 +[ 1.829263] t1 : 0000000000000000 t2 : 0000000000000000 s0 : ffffffc800023b70 +[ 1.829270] s1 : ffffffd88095d840 a0 : 0000000000000000 a1 : 0000000000000000 +[ 1.829276] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 +[ 1.829282] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 +[ 1.829288] s2 : ffffffffffffff92 s3 : 0000000000716c81 s4 : ffffffd8802b2c10 +[ 1.829295] s5 : 0000000000000003 s6 : ffffffffffffff92 s7 : ffffffff8108b448 +[ 1.829301] s8 : 0000000000000008 s9 : ffffffff80e00106 s10: 0000000000000000 +[ 1.829307] s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 +[ 1.829313] t5 : 0000000000000000 t6 : 0000000000000000 +[ 1.829317] status: 0000000200000120 badaddr: ffffffffffffff92 cause: 0000000000000003 +[ 1.829326] [<ffffffff806fa1ac>] fu740_pcie_start_link+0x1b4/0x1ce +[ 1.829341] [<ffffffff806f8692>] dw_pcie_host_init+0x21e/0x2cc +[ 1.829355] [<ffffffff806fa2ca>] fu740_pcie_probe+0x104/0x15a +[ 1.829366] [<ffffffff8083e510>] platform_probe+0x5e/0xc6 +[ 1.829388] [<ffffffff8083a7b4>] call_driver_probe+0x22/0x142 +[ 1.829400] [<ffffffff8083b36e>] really_probe+0x9a/0x2a2 +[ 1.829413] [<ffffffff8083b5f4>] __driver_probe_device+0x7e/0x146 +[ 1.829425] [<ffffffff8083b6f4>] driver_probe_device+0x38/0xd0 +[ 1.829436] [<ffffffff8083b966>] __driver_attach+0xee/0x1e8 +[ 1.829448] [<ffffffff80838e78>] bus_for_each_dev+0x6c/0xc4 +[ 1.829460] [<ffffffff8083acbe>] driver_attach+0x26/0x34 +[ 1.829471] [<ffffffff8083a1fe>] bus_add_driver+0x112/0x21e +[ 1.829483] [<ffffffff8083cb12>] driver_register+0x52/0x106 +[ 1.829497] [<ffffffff8083e0b6>] __platform_driver_register+0x28/0x34 +[ 1.829511] [<ffffffff80e3322e>] fu740_pcie_driver_init+0x22/0x2c +[ 1.829528] [<ffffffff80002962>] do_one_initcall+0x5c/0x1e2 +[ 1.829542] [<ffffffff80e01836>] kernel_init_freeable+0x286/0x300 +[ 1.829560] [<ffffffff80ce5b40>] kernel_init+0x2a/0x16e +[ 1.829584] [<ffffffff80003f82>] ret_from_fork+0xe/0x20 +[ 1.829597] ---[ end trace 0000000000000000 ]--- +[ 1.829635] fu740-pcie: probe of e00000000.pcie failed with error -110 diff --git a/src/soc/sifive/fu740/cbmem.c b/src/soc/sifive/fu740/cbmem.c new file mode 100644 index 0000000..e3ccf3a --- /dev/null +++ b/src/soc/sifive/fu740/cbmem.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <soc/addressmap.h> +#include <soc/sdram.h> +#include <symbols.h> + +uintptr_t cbmem_top_chipset(void) +{ +#define FU740_MAXDRAM 0x800000000ULL // 32 GiB + return MIN((uintptr_t)FU740_DRAM + sdram_size(), FU740_MAXDRAM); +} diff --git a/src/soc/sifive/fu740/chip.c b/src/soc/sifive/fu740/chip.c new file mode 100644 index 0000000..6909717 --- /dev/null +++ b/src/soc/sifive/fu740/chip.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <device/device.h> +#include <soc/addressmap.h> +#include <symbols.h> + +static void fu740_init(struct device *dev) { + int index = 0; + ram_from_to(dev, index++, FU740_DRAM, (uintptr_t)cbmem_top()); +} + +struct chip_operations soc_sifive_fu740_ops = { + CHIP_NAME("SIFIVE FU740") + .enable_dev = fu740_init, +}; + diff --git a/src/soc/sifive/fu740/clint.c b/src/soc/sifive/fu740/clint.c new file mode 100644 index 0000000..6f25148 --- /dev/null +++ b/src/soc/sifive/fu740/clint.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mcall.h> +#include <stdint.h> +#include <device/mmio.h> +#include <soc/addressmap.h> + +void mtime_init(void) +{ + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(FU740_CLINT + 0xbff8); + HLS()->timecmp = (uint64_t *)(FU740_CLINT + 0x4000 + 8 * hart_id); +} + +void set_msip(int hartid, int val) +{ + write32((void *)(FU740_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/sifive/fu740/clock.c b/src/soc/sifive/fu740/clock.c new file mode 100644 index 0000000..48046e2 --- /dev/null +++ b/src/soc/sifive/fu740/clock.c @@ -0,0 +1,452 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// This file is used for setting up clocks and get devices out of reset +// For more Information see FU740-C000 Manual Chapter 7 Clocking and Reset + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <gpio.h> +#include <stdint.h> + +// Clock frequencies for the cores, ddr and the peripherals are all derived from the hfclk (high frequency clock) and it is always 26 MHz +#define FU740_HFCLK_FREQ 26*MHz + +struct prci_ctlr { + u32 hfxosccfg; // offset 0x00 + u32 core_pllcfg; // offset 0x04 + u32 core_plloutdiv; // offset 0x08 + u32 ddr_pllcfg; // offset 0x0c + u32 ddr_plloutdiv; // offset 0x10 + u32 pcieaux_plloutdiv; // offset 0x14 (undocumented) + u32 reserved18; // offset 0x18 + u32 gemgxl_pllcfg; // offset 0x1c + u32 gemgxl_plloutdiv; // offset 0x20 + u32 core_clk_sel_reg; // offset 0x24 + u32 devices_reset_n; // offset 0x28 + u32 clk_mux_status; // offset 0x2C + u32 cltx_pllcfg; // offset 0x30 chiplink (undocumented) + u32 cltx_plloutdiv; // offset 0x34 chiplink (undocumented) + u32 dvfs_core_pllcfg; // offset 0x38 + u32 dvfs_core_plloutdiv; // offset 0x3C + u32 corepllsel; // offset 0x40 (undocumented, but probably same as last gen) + u8 reserved44[12]; // offset 0x44 + u32 hfpclk_pllcfg; // offset 0x50 + u32 hfpclk_plloutdiv; // offset 0x54 + u32 hfpclkpllsel; // offset 0x58 (undocumented, but probably same as last gen) + u32 hfpclk_div_reg; // offset 0x5C + u8 reserved60[128]; // offset 0x60 + u32 prci_plls; // offset 0xE0 + u8 reservedE4[12]; // offset 0xE4 + u32 procmoncfg_core_clock; // offset 0xF0 (undocumented) +} __packed; + +static struct prci_ctlr *prci = (void *)FU740_PRCI; + +// ================================= +// clock selections +// ================================= + +#define PRCI_COREPLLSEL_MASK 1 +#define PRCI_COREPLLSEL_COREPLL 0 +#define PRCI_COREPLLSEL_DVFSCOREPLL 1 + +#define PRCI_CORECLKSEL_MASK 1 +#define PRCI_CORECLKSEL_CORECLKPLL 0 +#define PRCI_CORECLKSEL_HFCLK 1 + +#define PRCI_HFPCLKSEL_MASK 1 +#define PRCI_HFPCLKSEL_PLL 0 +#define PRCI_HFPCLKSEL_HFCLK 1 + +// =================================== +// pllcfg register format is used by all PLLs +// =================================== + +#define PRCI_PLLCFG_DIVR_SHIFT 0 +#define PRCI_PLLCFG_DIVF_SHIFT 6 +#define PRCI_PLLCFG_DIVQ_SHIFT 15 +#define PRCI_PLLCFG_RANGE_SHIFT 18 +#define PRCI_PLLCFG_BYPASS_SHIFT 24 +#define PRCI_PLLCFG_FSEBYPASS_SHIFT 25 +#define PRCI_PLLCFG_LOCK_SHIFT 31 + +#define PRCI_PLLCFG_DIVR_MASK (0x03f << PRCI_PLLCFG_DIVR_SHIFT) +#define PRCI_PLLCFG_DIVF_MASK (0x1ff << PRCI_PLLCFG_DIVF_SHIFT) +#define PRCI_PLLCFG_DIVQ_MASK (0x007 << PRCI_PLLCFG_DIVQ_SHIFT) +#define PRCI_PLLCFG_RANGE_MASK (0x007 << PRCI_PLLCFG_RANGE_SHIFT) +#define PRCI_PLLCFG_BYPASS_MASK (0x001 << PRCI_PLLCFG_BYPASS_SHIFT) +#define PRCI_PLLCFG_FSEBYPASS_MASK (0x001 << PRCI_PLLCFG_FSEBYPASS_SHIFT) +#define PRCI_PLLCFG_LOCK_MASK (0x001 << PRCI_PLLCFG_LOCK_SHIFT) + +// =================================== +// plloutdiv register formats +// =================================== + +// registered are used to enable/disable PLLs +#define PRCI_DVFSCORE_PLLOUTDIV_MASK (1 << 24) // Note: u-boot and fu740 manual differ here ... +#define PRCI_HFPCLK_PLLOUTDIV_MASK (1 << 31) // Note: according to u-boot it is (1 << 24) but if I use that it gets stuck +#define PRCI_DDR_PLLOUTDIV_MASK (1 << 31) +#define PRCI_GEMGXL_PLLOUTDIV_MASK (1 << 31) +#define PRCI_CLTX_PLLOUTDIV_MASK (1 << 24) // undocumented (chiplink tx) +#define PRCI_PCIEAUX_PLLOUTDIV_MASK (1 << 0) // undocumented +#define PRCI_CORE_PLLOUTDIV_MASK (1 << 31) // undocumented + +// =================================== +// devicereset register formats +// =================================== + +// used to get devices in or out of reset +#define PRCI_DEVICES_RESET_DDR_CTRL_RST (1 << 0) // DDR Controller +#define PRCI_DEVICES_RESET_DDR_AXI_RST (1 << 1) // DDR Controller AXI Interface +#define PRCI_DEVICES_RESET_DDR_AHB_RST (1 << 2) // DDR Controller AHB Interface +#define PRCI_DEVICES_RESET_DDR_PHY_RST (1 << 3) // DDR PHY +#define PRCI_DEVICES_RESET_PCIEAUX_RST (1 << 4) +#define PRCI_DEVICES_RESET_GEMGXL_RST (1 << 5) // Gigabit Ethernet Subsystem +#define PRCI_DEVICES_RESET_CLTX_RST (1 << 6) // chiplink reset (undocumented) + +// =================================== +// prci_plls register format +// =================================== + +// used to check if certain PLLs are present in the SOC +#define PRCI_PLLS_CLTXPLL (1 << 0) +#define PRCI_PLLS_GEMGXLPLL (1 << 1) +#define PRCI_PLLS_DDRPLL (1 << 2) +#define PRCI_PLLS_HFPCLKPLL (1 << 3) +#define PRCI_PLLS_DVFSCOREPLL (1 << 4) +#define PRCI_PLLS_COREPLL (1 << 5) + +// =================================== +// clk_mux_status register format +// =================================== + +// read only register which is used to set some clock multiplex settings +// the value of this register depends on the state of pins connected to the FU740 SOC +// on the hifive-unmatched board the state of the pins is set by a hardware switch +#define PRCI_CLK_MUX_STATUS_CORECLKPLLSEL (1 << 0) + // 0 - HFCLK or CORECLK + // 1 - only HFCLK +#define PRCI_CLK_MUX_STATUS_TLCLKSEL (1 << 1) + // 0 - CORECLK/2 + // 1 - CORECLK +#define PRCI_CLK_MUX_STATUS_RTCXSEL (1 << 2) + // 0 - use HFXCLK for RTC + // 1 - use RTCXALTCLKIN for RTC +#define PRCI_CLK_MUX_STATUS_DDRCTRLCLKSEL (1 << 3) +#define PRCI_CLK_MUX_STATUS_DDRPHYCLKSEL (1 << 4) +#define PRCI_CLK_MUX_STATUS_RESERVED (1 << 5) +#define PRCI_CLK_MUX_STATUS_GEMGXLCLKSEL (1 << 6) +#define PRCI_CLK_MUX_STATUS_MAINMEMCLKSEL (1 << 7) + +// =================================== +// hfxosccfg register format +// =================================== + +#define PRCI_HFXOSCCFG_HFXOSEN (1 << 30) // Crystal Oszillator enable + // Note: I guess (it is not documented) + // 0 - XTAL PADS + // 1 - OSC PADS +#define PRCI_HFXOSCCFG_HFXOSCRDY (1 << 31) // Crystal Oszillator ready + +struct pll_settings { + unsigned int divr:6; // divider before PLL loop (reference), equal to divr + 1 + unsigned int divf:9; // VCO feedback divider value, equal to 2 * (divf + 1) + unsigned int divq:3; // divider after PLL loop, equal to 2^divq + // PLL filter range (TODO documentation is not really clear on how to set it) + unsigned int range:3; + unsigned int bypass:1; // probably used to bypass the PLL + // internal or external input path (internal = 1, external = 0) + //WARN this is only a guess since it is undocumented + unsigned int fsebypass:1; +}; + +static void configure_pll(u32 *reg, const struct pll_settings *s) +{ + // Write the settings to the register + u32 c = read32(reg); + clrsetbits32(&c, PRCI_PLLCFG_DIVR_MASK + | PRCI_PLLCFG_DIVF_MASK + | PRCI_PLLCFG_DIVQ_MASK + | PRCI_PLLCFG_RANGE_MASK + | PRCI_PLLCFG_BYPASS_MASK + | PRCI_PLLCFG_FSEBYPASS_MASK, + (s->divr << PRCI_PLLCFG_DIVR_SHIFT) + | (s->divf << PRCI_PLLCFG_DIVF_SHIFT) + | (s->divq << PRCI_PLLCFG_DIVQ_SHIFT) + | (s->range << PRCI_PLLCFG_RANGE_SHIFT) + | (s->bypass << PRCI_PLLCFG_BYPASS_SHIFT) + | (s->fsebypass << PRCI_PLLCFG_FSEBYPASS_SHIFT)); + write32(reg, c); + + // Wait for PLL lock + while (!(read32(reg) & PRCI_PLLCFG_LOCK_MASK)); +} + +/* + * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible) + * Section 7.4.2 provides the necessary values + * + * COREPLL is set up for ~1 GHz output frequency. + * divr = 0 (x1), divf = 76 (x154) => (4004 MHz VCO), divq = 2 (/4 Output divider) + */ +static const struct pll_settings corepll_settings = { + .divr = 0, + .divf = 76, + .divq = 2, + .range = 4, + .bypass = 0, + .fsebypass = 1, // external feedback mode is not supported +}; + +/* + * Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset + * + * DDRPLL is set up for 933 MHz output frequency. + * divr = 0 (x1), divf = 71 (x144) => (3744 MHz VCO), divq = 2 (/4 output divider) + */ +static const struct pll_settings ddrpll_settings = { + .divr = 0, + .divf = 71, + .divq = 2, + .range = 4, + .bypass = 0, + .fsebypass = 1, // external feedback mode is not supported +}; + +/* + * GEMGXLPLL is set up for 125 MHz output frequency. + * divr = 0 (x1), divf = 76 (x154) => (4004 MHz VCO), divq = 5 (/32 output divider) + */ +static const struct pll_settings gemgxlpll_settings = { + .divr = 0, + .divf = 76, + .divq = 5, + .range = 4, + .bypass = 0, + .fsebypass = 1, // external feedback mode is not supported +}; + +/* + * HFPCLKPLL is set up for 520 MHz output frequency. + * TODO a lower value should also suffice as well as safe some power + * divr = 1 (/2), divf = 39 (x80) => (2080 MHz VCO), divq = 2 (/4 output divider) + */ +static const struct pll_settings hfpclkpll_settings = { + .divr = 1, + //.divf = 122, + .divf = 39, + .divq = 2, + .range = 4, + .bypass = 0, + .fsebypass = 1, // external feedback mode is not supported +}; + +/* + * CLTXCLKPLL is set up for 520 MHz output frequency. + * divr = 1 (/2), divf = 122 (x154) => (4004 MHz VCO), divq = 2 (/4 output divider) + */ +static const struct pll_settings cltxpll_settings = { + .divr = 1, + .divf = 39, + .divq = 2, + .range = 4, + .bypass = 0, + .fsebypass = 1, // external feedback mode is not supported +}; + +//TODO maybe it makes sense to disable the clocks before configuring them (test out) + +static void init_coreclk(void) +{ + // we can't modify the coreclk PLL while we are running on it, so let coreclk devise + // its clock from hfclk before modifying PLL + clrsetbits32(&prci->core_clk_sel_reg, PRCI_CORECLKSEL_MASK, PRCI_CORECLKSEL_HFCLK); + + // only configure pll if it is present + if (!(read32(&prci->prci_plls) & PRCI_PLLS_COREPLL)) { + return; + } + + configure_pll(&prci->core_pllcfg, &corepll_settings); + + // switch coreclk multiplexer to use corepll as clock source again + clrsetbits32(&prci->core_clk_sel_reg, PRCI_CORECLKSEL_MASK, PRCI_CORECLKSEL_CORECLKPLL); +} + +static void init_ddrclk(void) +{ + // only configure pll if it is present + if (!(read32(&prci->prci_plls) & PRCI_PLLS_DDRPLL)) { + return; + } + + // disable ddr clock output before reconfiguring the PLL + u32 cfg1 = read32(&prci->ddr_plloutdiv); + clrbits32(&cfg1, PRCI_DDR_PLLOUTDIV_MASK); + write32(&prci->ddr_plloutdiv, cfg1); + + configure_pll(&prci->ddr_pllcfg, &ddrpll_settings); + + // PLL is ready/locked so enable it (its gated) + setbits32(&cfg1, PRCI_DDR_PLLOUTDIV_MASK); + write32(&prci->ddr_plloutdiv, cfg1); +} + +static void init_gemgxlclk(void) +{ + // only configure pll if it is present + if (!(read32(&prci->prci_plls) & PRCI_PLLS_GEMGXLPLL)) { + return; + } + + // disable gemgxl clock output before reconfiguring the PLL + u32 cfg1 = read32(&prci->gemgxl_plloutdiv); + clrbits32(&cfg1, PRCI_GEMGXL_PLLOUTDIV_MASK); + write32(&prci->gemgxl_plloutdiv, cfg1); + + configure_pll(&prci->gemgxl_pllcfg, &gemgxlpll_settings); + + // PLL is ready/locked so enable it (its gated) + setbits32(&cfg1, PRCI_GEMGXL_PLLOUTDIV_MASK); + write32(&prci->gemgxl_plloutdiv, cfg1); +} + +/* + * Configure High Frequency peripheral clock which is used by + * UART, SPI, GPIO, I2C and PWM subsystem + */ +static void init_hfpclk(void) +{ + // we can't modify the hfpclk PLL while we are running on it, so let pclk devise + // its clock from hfclk before modifying PLL + u32 hfpclksel = read32(&prci->hfpclkpllsel); + hfpclksel |= PRCI_HFPCLKSEL_HFCLK; + write32(&prci->hfpclkpllsel, hfpclksel); + + configure_pll(&prci->hfpclk_pllcfg, &hfpclkpll_settings); + + // PLL is ready/locked so enable it (its gated) + u32 hfpclk_plloutdiv = read32(&prci->hfpclk_plloutdiv); + hfpclk_plloutdiv |= PRCI_HFPCLK_PLLOUTDIV_MASK; + write32(&prci->hfpclk_plloutdiv, hfpclk_plloutdiv); + + printk(BIOS_DEBUG, "%s: 1\n", __func__); + mdelay(1); + + // switch to using PLL for hfpclk + clrbits32(&prci->hfpclkpllsel, PRCI_HFPCLKSEL_MASK); + + udelay(70); +} + +static void reset_deassert(u8 reset_index) { + u32 device_reset = read32(&prci->devices_reset_n); + device_reset |= reset_index; + write32(&prci->devices_reset_n, device_reset); +} + +static void init_cltx(void) +{ + // disable hfpclkpll before configuring it + u32 cfg1 = read32(&prci->cltx_plloutdiv); + clrbits32(&cfg1, PRCI_CLTX_PLLOUTDIV_MASK); + write32(&prci->cltx_plloutdiv, cfg1); + + configure_pll(&prci->cltx_pllcfg, &cltxpll_settings); + + // PLL is ready/locked so enable it (its gated) + setbits32(&cfg1, PRCI_CLTX_PLLOUTDIV_MASK); + write32(&prci->cltx_plloutdiv, cfg1); + + // get chiplink out of reset + reset_deassert(PRCI_DEVICES_RESET_CLTX_RST); + + udelay(70); +} + +void clock_init(void) +{ + printk(BIOS_SPEW, "PLLs present on platform: %x\n", read32(&prci->prci_plls)); + + // first configure the coreclk (used by HARTs) to get maximum speed early on + init_coreclk(); + + // put all devices in reset (e.g. DDR, ethernet, pcie) before configuring their clocks + write32(&prci->devices_reset_n, 0); + + // initialize clock used by DDR subsystem + init_ddrclk(); + + // get DDR controller out of reset + reset_deassert(PRCI_DEVICES_RESET_DDR_CTRL_RST); + + // wait at least one full DDR controller clock cycle + asm volatile ("fence"); + + // get DDR controller (register interface) out of reset + // get DDR subsystem PHY out of reset + reset_deassert(PRCI_DEVICES_RESET_DDR_AXI_RST | + PRCI_DEVICES_RESET_DDR_AHB_RST | + PRCI_DEVICES_RESET_DDR_PHY_RST); + + // we need to wait 256 full ddrctrl clock cycles until we can interact with the DDR subsystem + for (int i = 0; i < 256; i++) + asm volatile ("nop"); + + if (read32(&prci->prci_plls) & PRCI_PLLS_HFPCLKPLL) { + // set hfclk as reference for peripheral clock since we don't have the PLL + //clrsetbits32(&prci->hfpclkpllsel, PRCI_HFPCLKSEL_MASK, PRCI_HFPCLKSEL_HFCLK); + init_hfpclk(); + } else if (read32(&prci->prci_plls) & PRCI_PLLS_CLTXPLL) { + // Note: this path has never been tested since the platforms tested with + // always have HFPCLKPLL + init_cltx(); + // get chiplink out of reset + reset_deassert(PRCI_DEVICES_RESET_CLTX_RST); + } + + // GEMGXL init VSC8541 PHY reset sequence; + gpio_set_direction(GEMGXL_RST, GPIO_OUTPUT); + gpio_set(GEMGXL_RST, 1); + + udelay(1); + + /* Reset PHY again to enter unmanaged mode */ + gpio_set(GEMGXL_RST, 0); + udelay(1); + gpio_set(GEMGXL_RST, 1); + mdelay(15); + + init_gemgxlclk(); + + // get ethernet out of reset + reset_deassert(PRCI_DEVICES_RESET_GEMGXL_RST); +} + +// get the peripheral clock frequency used by UART (probably also SPI, GPIO, I2C and PWM) +int clock_get_pclk(void) +{ + u64 pclk = FU740_HFCLK_FREQ; + + // check if hfpclkpll is present and + // check if hfpclkpll is selected in the multiplexer TODO + // check if hpfclkpll is enabled + if ((read32(&prci->prci_plls) & PRCI_PLLS_HFPCLKPLL) && + (read32(&prci->hfpclk_plloutdiv) & PRCI_HFPCLK_PLLOUTDIV_MASK)) { + int hfpclk_pllcfg = read32(&prci->hfpclk_pllcfg); + int divr = (hfpclk_pllcfg & PRCI_PLLCFG_DIVR_MASK) >> PRCI_PLLCFG_DIVR_SHIFT; + int divf = (hfpclk_pllcfg & PRCI_PLLCFG_DIVF_MASK) >> PRCI_PLLCFG_DIVF_SHIFT; + int divq = (hfpclk_pllcfg & PRCI_PLLCFG_DIVQ_MASK) >> PRCI_PLLCFG_DIVQ_SHIFT; + pclk /= (divr + 1); // reference divider + pclk *= (2 * (divf + 1)); // feedback divider + pclk /= (1 << divq); // output divider + } + printk(BIOS_DEBUG, "pclk: %llu\n", pclk / (read32(&prci->hfpclk_div_reg) + 2)); + + // divider value before pclk seems to be (hfpclkdiv + 2). Not mentioned in fu740 manual though. + return pclk / (read32(&prci->hfpclk_div_reg) + 2); +} diff --git a/src/soc/sifive/fu740/ddrregs.c b/src/soc/sifive/fu740/ddrregs.c new file mode 100644 index 0000000..5e86c0d --- /dev/null +++ b/src/soc/sifive/fu740/ddrregs.c @@ -0,0 +1,1491 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdint.h> +#include "regconfig-phy.h" +#include "regconfig-ctl.h" + +const uint32_t denali_ddr_phy_data[1215] = { + DENALI_PHY_00_DATA, + DENALI_PHY_01_DATA, + DENALI_PHY_02_DATA, + DENALI_PHY_03_DATA, + DENALI_PHY_04_DATA, + DENALI_PHY_05_DATA, + DENALI_PHY_06_DATA, + DENALI_PHY_07_DATA, + DENALI_PHY_08_DATA, + DENALI_PHY_09_DATA, + DENALI_PHY_10_DATA, + DENALI_PHY_11_DATA, + DENALI_PHY_12_DATA, + DENALI_PHY_13_DATA, + DENALI_PHY_14_DATA, + DENALI_PHY_15_DATA, + DENALI_PHY_16_DATA, + DENALI_PHY_17_DATA, + DENALI_PHY_18_DATA, + DENALI_PHY_19_DATA, + DENALI_PHY_20_DATA, + DENALI_PHY_21_DATA, + DENALI_PHY_22_DATA, + DENALI_PHY_23_DATA, + DENALI_PHY_24_DATA, + DENALI_PHY_25_DATA, + DENALI_PHY_26_DATA, + DENALI_PHY_27_DATA, + DENALI_PHY_28_DATA, + DENALI_PHY_29_DATA, + DENALI_PHY_30_DATA, + DENALI_PHY_31_DATA, + DENALI_PHY_32_DATA, + DENALI_PHY_33_DATA, + DENALI_PHY_34_DATA, + DENALI_PHY_35_DATA, + DENALI_PHY_36_DATA, + DENALI_PHY_37_DATA, + DENALI_PHY_38_DATA, + DENALI_PHY_39_DATA, + DENALI_PHY_40_DATA, + DENALI_PHY_41_DATA, + DENALI_PHY_42_DATA, + DENALI_PHY_43_DATA, + DENALI_PHY_44_DATA, + DENALI_PHY_45_DATA, + DENALI_PHY_46_DATA, + DENALI_PHY_47_DATA, + DENALI_PHY_48_DATA, + DENALI_PHY_49_DATA, + DENALI_PHY_50_DATA, + DENALI_PHY_51_DATA, + DENALI_PHY_52_DATA, + DENALI_PHY_53_DATA, + DENALI_PHY_54_DATA, + DENALI_PHY_55_DATA, + DENALI_PHY_56_DATA, + DENALI_PHY_57_DATA, + DENALI_PHY_58_DATA, + DENALI_PHY_59_DATA, + DENALI_PHY_60_DATA, + DENALI_PHY_61_DATA, + DENALI_PHY_62_DATA, + DENALI_PHY_63_DATA, + DENALI_PHY_64_DATA, + DENALI_PHY_65_DATA, + DENALI_PHY_66_DATA, + DENALI_PHY_67_DATA, + DENALI_PHY_68_DATA, + DENALI_PHY_69_DATA, + DENALI_PHY_70_DATA, + DENALI_PHY_71_DATA, + DENALI_PHY_72_DATA, + DENALI_PHY_73_DATA, + DENALI_PHY_74_DATA, + DENALI_PHY_75_DATA, + DENALI_PHY_76_DATA, + DENALI_PHY_77_DATA, + DENALI_PHY_78_DATA, + DENALI_PHY_79_DATA, + DENALI_PHY_80_DATA, + DENALI_PHY_81_DATA, + DENALI_PHY_82_DATA, + DENALI_PHY_83_DATA, + DENALI_PHY_84_DATA, + DENALI_PHY_85_DATA, + DENALI_PHY_86_DATA, + DENALI_PHY_87_DATA, + DENALI_PHY_88_DATA, + DENALI_PHY_89_DATA, + DENALI_PHY_90_DATA, + DENALI_PHY_91_DATA, + DENALI_PHY_92_DATA, + DENALI_PHY_93_DATA, + DENALI_PHY_94_DATA, + DENALI_PHY_95_DATA, + DENALI_PHY_96_DATA, + DENALI_PHY_97_DATA, + DENALI_PHY_98_DATA, + DENALI_PHY_99_DATA, + DENALI_PHY_100_DATA, + DENALI_PHY_101_DATA, + DENALI_PHY_102_DATA, + DENALI_PHY_103_DATA, + DENALI_PHY_104_DATA, + DENALI_PHY_105_DATA, + DENALI_PHY_106_DATA, + DENALI_PHY_107_DATA, + DENALI_PHY_108_DATA, + DENALI_PHY_109_DATA, + DENALI_PHY_110_DATA, + DENALI_PHY_111_DATA, + DENALI_PHY_112_DATA, + DENALI_PHY_113_DATA, + DENALI_PHY_114_DATA, + DENALI_PHY_115_DATA, + DENALI_PHY_116_DATA, + DENALI_PHY_117_DATA, + DENALI_PHY_118_DATA, + DENALI_PHY_119_DATA, + DENALI_PHY_120_DATA, + DENALI_PHY_121_DATA, + DENALI_PHY_122_DATA, + DENALI_PHY_123_DATA, + DENALI_PHY_124_DATA, + DENALI_PHY_125_DATA, + DENALI_PHY_126_DATA, + DENALI_PHY_127_DATA, + DENALI_PHY_128_DATA, + DENALI_PHY_129_DATA, + DENALI_PHY_130_DATA, + DENALI_PHY_131_DATA, + DENALI_PHY_132_DATA, + DENALI_PHY_133_DATA, + DENALI_PHY_134_DATA, + DENALI_PHY_135_DATA, + DENALI_PHY_136_DATA, + DENALI_PHY_137_DATA, + DENALI_PHY_138_DATA, + DENALI_PHY_139_DATA, + DENALI_PHY_140_DATA, + DENALI_PHY_141_DATA, + DENALI_PHY_142_DATA, + DENALI_PHY_143_DATA, + DENALI_PHY_144_DATA, + DENALI_PHY_145_DATA, + DENALI_PHY_146_DATA, + DENALI_PHY_147_DATA, + DENALI_PHY_148_DATA, + DENALI_PHY_149_DATA, + DENALI_PHY_150_DATA, + DENALI_PHY_151_DATA, + DENALI_PHY_152_DATA, + DENALI_PHY_153_DATA, + DENALI_PHY_154_DATA, + DENALI_PHY_155_DATA, + DENALI_PHY_156_DATA, + DENALI_PHY_157_DATA, + DENALI_PHY_158_DATA, + DENALI_PHY_159_DATA, + DENALI_PHY_160_DATA, + DENALI_PHY_161_DATA, + DENALI_PHY_162_DATA, + DENALI_PHY_163_DATA, + DENALI_PHY_164_DATA, + DENALI_PHY_165_DATA, + DENALI_PHY_166_DATA, + DENALI_PHY_167_DATA, + DENALI_PHY_168_DATA, + DENALI_PHY_169_DATA, + DENALI_PHY_170_DATA, + DENALI_PHY_171_DATA, + DENALI_PHY_172_DATA, + DENALI_PHY_173_DATA, + DENALI_PHY_174_DATA, + DENALI_PHY_175_DATA, + DENALI_PHY_176_DATA, + DENALI_PHY_177_DATA, + DENALI_PHY_178_DATA, + DENALI_PHY_179_DATA, + DENALI_PHY_180_DATA, + DENALI_PHY_181_DATA, + DENALI_PHY_182_DATA, + DENALI_PHY_183_DATA, + DENALI_PHY_184_DATA, + DENALI_PHY_185_DATA, + DENALI_PHY_186_DATA, + DENALI_PHY_187_DATA, + DENALI_PHY_188_DATA, + DENALI_PHY_189_DATA, + DENALI_PHY_190_DATA, + DENALI_PHY_191_DATA, + DENALI_PHY_192_DATA, + DENALI_PHY_193_DATA, + DENALI_PHY_194_DATA, + DENALI_PHY_195_DATA, + DENALI_PHY_196_DATA, + DENALI_PHY_197_DATA, + DENALI_PHY_198_DATA, + DENALI_PHY_199_DATA, + DENALI_PHY_200_DATA, + DENALI_PHY_201_DATA, + DENALI_PHY_202_DATA, + DENALI_PHY_203_DATA, + DENALI_PHY_204_DATA, + DENALI_PHY_205_DATA, + DENALI_PHY_206_DATA, + DENALI_PHY_207_DATA, + DENALI_PHY_208_DATA, + DENALI_PHY_209_DATA, + DENALI_PHY_210_DATA, + DENALI_PHY_211_DATA, + DENALI_PHY_212_DATA, + DENALI_PHY_213_DATA, + DENALI_PHY_214_DATA, + DENALI_PHY_215_DATA, + DENALI_PHY_216_DATA, + DENALI_PHY_217_DATA, + DENALI_PHY_218_DATA, + DENALI_PHY_219_DATA, + DENALI_PHY_220_DATA, + DENALI_PHY_221_DATA, + DENALI_PHY_222_DATA, + DENALI_PHY_223_DATA, + DENALI_PHY_224_DATA, + DENALI_PHY_225_DATA, + DENALI_PHY_226_DATA, + DENALI_PHY_227_DATA, + DENALI_PHY_228_DATA, + DENALI_PHY_229_DATA, + DENALI_PHY_230_DATA, + DENALI_PHY_231_DATA, + DENALI_PHY_232_DATA, + DENALI_PHY_233_DATA, + DENALI_PHY_234_DATA, + DENALI_PHY_235_DATA, + DENALI_PHY_236_DATA, + DENALI_PHY_237_DATA, + DENALI_PHY_238_DATA, + DENALI_PHY_239_DATA, + DENALI_PHY_240_DATA, + DENALI_PHY_241_DATA, + DENALI_PHY_242_DATA, + DENALI_PHY_243_DATA, + DENALI_PHY_244_DATA, + DENALI_PHY_245_DATA, + DENALI_PHY_246_DATA, + DENALI_PHY_247_DATA, + DENALI_PHY_248_DATA, + DENALI_PHY_249_DATA, + DENALI_PHY_250_DATA, + DENALI_PHY_251_DATA, + DENALI_PHY_252_DATA, + DENALI_PHY_253_DATA, + DENALI_PHY_254_DATA, + DENALI_PHY_255_DATA, + DENALI_PHY_256_DATA, + DENALI_PHY_257_DATA, + DENALI_PHY_258_DATA, + DENALI_PHY_259_DATA, + DENALI_PHY_260_DATA, + DENALI_PHY_261_DATA, + DENALI_PHY_262_DATA, + DENALI_PHY_263_DATA, + DENALI_PHY_264_DATA, + DENALI_PHY_265_DATA, + DENALI_PHY_266_DATA, + DENALI_PHY_267_DATA, + DENALI_PHY_268_DATA, + DENALI_PHY_269_DATA, + DENALI_PHY_270_DATA, + DENALI_PHY_271_DATA, + DENALI_PHY_272_DATA, + DENALI_PHY_273_DATA, + DENALI_PHY_274_DATA, + DENALI_PHY_275_DATA, + DENALI_PHY_276_DATA, + DENALI_PHY_277_DATA, + DENALI_PHY_278_DATA, + DENALI_PHY_279_DATA, + DENALI_PHY_280_DATA, + DENALI_PHY_281_DATA, + DENALI_PHY_282_DATA, + DENALI_PHY_283_DATA, + DENALI_PHY_284_DATA, + DENALI_PHY_285_DATA, + DENALI_PHY_286_DATA, + DENALI_PHY_287_DATA, + DENALI_PHY_288_DATA, + DENALI_PHY_289_DATA, + DENALI_PHY_290_DATA, + DENALI_PHY_291_DATA, + DENALI_PHY_292_DATA, + DENALI_PHY_293_DATA, + DENALI_PHY_294_DATA, + DENALI_PHY_295_DATA, + DENALI_PHY_296_DATA, + DENALI_PHY_297_DATA, + DENALI_PHY_298_DATA, + DENALI_PHY_299_DATA, + DENALI_PHY_300_DATA, + DENALI_PHY_301_DATA, + DENALI_PHY_302_DATA, + DENALI_PHY_303_DATA, + DENALI_PHY_304_DATA, + DENALI_PHY_305_DATA, + DENALI_PHY_306_DATA, + DENALI_PHY_307_DATA, + DENALI_PHY_308_DATA, + DENALI_PHY_309_DATA, + DENALI_PHY_310_DATA, + DENALI_PHY_311_DATA, + DENALI_PHY_312_DATA, + DENALI_PHY_313_DATA, + DENALI_PHY_314_DATA, + DENALI_PHY_315_DATA, + DENALI_PHY_316_DATA, + DENALI_PHY_317_DATA, + DENALI_PHY_318_DATA, + DENALI_PHY_319_DATA, + DENALI_PHY_320_DATA, + DENALI_PHY_321_DATA, + DENALI_PHY_322_DATA, + DENALI_PHY_323_DATA, + DENALI_PHY_324_DATA, + DENALI_PHY_325_DATA, + DENALI_PHY_326_DATA, + DENALI_PHY_327_DATA, + DENALI_PHY_328_DATA, + DENALI_PHY_329_DATA, + DENALI_PHY_330_DATA, + DENALI_PHY_331_DATA, + DENALI_PHY_332_DATA, + DENALI_PHY_333_DATA, + DENALI_PHY_334_DATA, + DENALI_PHY_335_DATA, + DENALI_PHY_336_DATA, + DENALI_PHY_337_DATA, + DENALI_PHY_338_DATA, + DENALI_PHY_339_DATA, + DENALI_PHY_340_DATA, + DENALI_PHY_341_DATA, + DENALI_PHY_342_DATA, + DENALI_PHY_343_DATA, + DENALI_PHY_344_DATA, + DENALI_PHY_345_DATA, + DENALI_PHY_346_DATA, + DENALI_PHY_347_DATA, + DENALI_PHY_348_DATA, + DENALI_PHY_349_DATA, + DENALI_PHY_350_DATA, + DENALI_PHY_351_DATA, + DENALI_PHY_352_DATA, + DENALI_PHY_353_DATA, + DENALI_PHY_354_DATA, + DENALI_PHY_355_DATA, + DENALI_PHY_356_DATA, + DENALI_PHY_357_DATA, + DENALI_PHY_358_DATA, + DENALI_PHY_359_DATA, + DENALI_PHY_360_DATA, + DENALI_PHY_361_DATA, + DENALI_PHY_362_DATA, + DENALI_PHY_363_DATA, + DENALI_PHY_364_DATA, + DENALI_PHY_365_DATA, + DENALI_PHY_366_DATA, + DENALI_PHY_367_DATA, + DENALI_PHY_368_DATA, + DENALI_PHY_369_DATA, + DENALI_PHY_370_DATA, + DENALI_PHY_371_DATA, + DENALI_PHY_372_DATA, + DENALI_PHY_373_DATA, + DENALI_PHY_374_DATA, + DENALI_PHY_375_DATA, + DENALI_PHY_376_DATA, + DENALI_PHY_377_DATA, + DENALI_PHY_378_DATA, + DENALI_PHY_379_DATA, + DENALI_PHY_380_DATA, + DENALI_PHY_381_DATA, + DENALI_PHY_382_DATA, + DENALI_PHY_383_DATA, + DENALI_PHY_384_DATA, + DENALI_PHY_385_DATA, + DENALI_PHY_386_DATA, + DENALI_PHY_387_DATA, + DENALI_PHY_388_DATA, + DENALI_PHY_389_DATA, + DENALI_PHY_390_DATA, + DENALI_PHY_391_DATA, + DENALI_PHY_392_DATA, + DENALI_PHY_393_DATA, + DENALI_PHY_394_DATA, + DENALI_PHY_395_DATA, + DENALI_PHY_396_DATA, + DENALI_PHY_397_DATA, + DENALI_PHY_398_DATA, + DENALI_PHY_399_DATA, + DENALI_PHY_400_DATA, + DENALI_PHY_401_DATA, + DENALI_PHY_402_DATA, + DENALI_PHY_403_DATA, + DENALI_PHY_404_DATA, + DENALI_PHY_405_DATA, + DENALI_PHY_406_DATA, + DENALI_PHY_407_DATA, + DENALI_PHY_408_DATA, + DENALI_PHY_409_DATA, + DENALI_PHY_410_DATA, + DENALI_PHY_411_DATA, + DENALI_PHY_412_DATA, + DENALI_PHY_413_DATA, + DENALI_PHY_414_DATA, + DENALI_PHY_415_DATA, + DENALI_PHY_416_DATA, + DENALI_PHY_417_DATA, + DENALI_PHY_418_DATA, + DENALI_PHY_419_DATA, + DENALI_PHY_420_DATA, + DENALI_PHY_421_DATA, + DENALI_PHY_422_DATA, + DENALI_PHY_423_DATA, + DENALI_PHY_424_DATA, + DENALI_PHY_425_DATA, + DENALI_PHY_426_DATA, + DENALI_PHY_427_DATA, + DENALI_PHY_428_DATA, + DENALI_PHY_429_DATA, + DENALI_PHY_430_DATA, + DENALI_PHY_431_DATA, + DENALI_PHY_432_DATA, + DENALI_PHY_433_DATA, + DENALI_PHY_434_DATA, + DENALI_PHY_435_DATA, + DENALI_PHY_436_DATA, + DENALI_PHY_437_DATA, + DENALI_PHY_438_DATA, + DENALI_PHY_439_DATA, + DENALI_PHY_440_DATA, + DENALI_PHY_441_DATA, + DENALI_PHY_442_DATA, + DENALI_PHY_443_DATA, + DENALI_PHY_444_DATA, + DENALI_PHY_445_DATA, + DENALI_PHY_446_DATA, + DENALI_PHY_447_DATA, + DENALI_PHY_448_DATA, + DENALI_PHY_449_DATA, + DENALI_PHY_450_DATA, + DENALI_PHY_451_DATA, + DENALI_PHY_452_DATA, + DENALI_PHY_453_DATA, + DENALI_PHY_454_DATA, + DENALI_PHY_455_DATA, + DENALI_PHY_456_DATA, + DENALI_PHY_457_DATA, + DENALI_PHY_458_DATA, + DENALI_PHY_459_DATA, + DENALI_PHY_460_DATA, + DENALI_PHY_461_DATA, + DENALI_PHY_462_DATA, + DENALI_PHY_463_DATA, + DENALI_PHY_464_DATA, + DENALI_PHY_465_DATA, + DENALI_PHY_466_DATA, + DENALI_PHY_467_DATA, + DENALI_PHY_468_DATA, + DENALI_PHY_469_DATA, + DENALI_PHY_470_DATA, + DENALI_PHY_471_DATA, + DENALI_PHY_472_DATA, + DENALI_PHY_473_DATA, + DENALI_PHY_474_DATA, + DENALI_PHY_475_DATA, + DENALI_PHY_476_DATA, + DENALI_PHY_477_DATA, + DENALI_PHY_478_DATA, + DENALI_PHY_479_DATA, + DENALI_PHY_480_DATA, + DENALI_PHY_481_DATA, + DENALI_PHY_482_DATA, + DENALI_PHY_483_DATA, + DENALI_PHY_484_DATA, + DENALI_PHY_485_DATA, + DENALI_PHY_486_DATA, + DENALI_PHY_487_DATA, + DENALI_PHY_488_DATA, + DENALI_PHY_489_DATA, + DENALI_PHY_490_DATA, + DENALI_PHY_491_DATA, + DENALI_PHY_492_DATA, + DENALI_PHY_493_DATA, + DENALI_PHY_494_DATA, + DENALI_PHY_495_DATA, + DENALI_PHY_496_DATA, + DENALI_PHY_497_DATA, + DENALI_PHY_498_DATA, + DENALI_PHY_499_DATA, + DENALI_PHY_500_DATA, + DENALI_PHY_501_DATA, + DENALI_PHY_502_DATA, + DENALI_PHY_503_DATA, + DENALI_PHY_504_DATA, + DENALI_PHY_505_DATA, + DENALI_PHY_506_DATA, + DENALI_PHY_507_DATA, + DENALI_PHY_508_DATA, + DENALI_PHY_509_DATA, + DENALI_PHY_510_DATA, + DENALI_PHY_511_DATA, + DENALI_PHY_512_DATA, + DENALI_PHY_513_DATA, + DENALI_PHY_514_DATA, + DENALI_PHY_515_DATA, + DENALI_PHY_516_DATA, + DENALI_PHY_517_DATA, + DENALI_PHY_518_DATA, + DENALI_PHY_519_DATA, + DENALI_PHY_520_DATA, + DENALI_PHY_521_DATA, + DENALI_PHY_522_DATA, + DENALI_PHY_523_DATA, + DENALI_PHY_524_DATA, + DENALI_PHY_525_DATA, + DENALI_PHY_526_DATA, + DENALI_PHY_527_DATA, + DENALI_PHY_528_DATA, + DENALI_PHY_529_DATA, + DENALI_PHY_530_DATA, + DENALI_PHY_531_DATA, + DENALI_PHY_532_DATA, + DENALI_PHY_533_DATA, + DENALI_PHY_534_DATA, + DENALI_PHY_535_DATA, + DENALI_PHY_536_DATA, + DENALI_PHY_537_DATA, + DENALI_PHY_538_DATA, + DENALI_PHY_539_DATA, + DENALI_PHY_540_DATA, + DENALI_PHY_541_DATA, + DENALI_PHY_542_DATA, + DENALI_PHY_543_DATA, + DENALI_PHY_544_DATA, + DENALI_PHY_545_DATA, + DENALI_PHY_546_DATA, + DENALI_PHY_547_DATA, + DENALI_PHY_548_DATA, + DENALI_PHY_549_DATA, + DENALI_PHY_550_DATA, + DENALI_PHY_551_DATA, + DENALI_PHY_552_DATA, + DENALI_PHY_553_DATA, + DENALI_PHY_554_DATA, + DENALI_PHY_555_DATA, + DENALI_PHY_556_DATA, + DENALI_PHY_557_DATA, + DENALI_PHY_558_DATA, + DENALI_PHY_559_DATA, + DENALI_PHY_560_DATA, + DENALI_PHY_561_DATA, + DENALI_PHY_562_DATA, + DENALI_PHY_563_DATA, + DENALI_PHY_564_DATA, + DENALI_PHY_565_DATA, + DENALI_PHY_566_DATA, + DENALI_PHY_567_DATA, + DENALI_PHY_568_DATA, + DENALI_PHY_569_DATA, + DENALI_PHY_570_DATA, + DENALI_PHY_571_DATA, + DENALI_PHY_572_DATA, + DENALI_PHY_573_DATA, + DENALI_PHY_574_DATA, + DENALI_PHY_575_DATA, + DENALI_PHY_576_DATA, + DENALI_PHY_577_DATA, + DENALI_PHY_578_DATA, + DENALI_PHY_579_DATA, + DENALI_PHY_580_DATA, + DENALI_PHY_581_DATA, + DENALI_PHY_582_DATA, + DENALI_PHY_583_DATA, + DENALI_PHY_584_DATA, + DENALI_PHY_585_DATA, + DENALI_PHY_586_DATA, + DENALI_PHY_587_DATA, + DENALI_PHY_588_DATA, + DENALI_PHY_589_DATA, + DENALI_PHY_590_DATA, + DENALI_PHY_591_DATA, + DENALI_PHY_592_DATA, + DENALI_PHY_593_DATA, + DENALI_PHY_594_DATA, + DENALI_PHY_595_DATA, + DENALI_PHY_596_DATA, + DENALI_PHY_597_DATA, + DENALI_PHY_598_DATA, + DENALI_PHY_599_DATA, + DENALI_PHY_600_DATA, + DENALI_PHY_601_DATA, + DENALI_PHY_602_DATA, + DENALI_PHY_603_DATA, + DENALI_PHY_604_DATA, + DENALI_PHY_605_DATA, + DENALI_PHY_606_DATA, + DENALI_PHY_607_DATA, + DENALI_PHY_608_DATA, + DENALI_PHY_609_DATA, + DENALI_PHY_610_DATA, + DENALI_PHY_611_DATA, + DENALI_PHY_612_DATA, + DENALI_PHY_613_DATA, + DENALI_PHY_614_DATA, + DENALI_PHY_615_DATA, + DENALI_PHY_616_DATA, + DENALI_PHY_617_DATA, + DENALI_PHY_618_DATA, + DENALI_PHY_619_DATA, + DENALI_PHY_620_DATA, + DENALI_PHY_621_DATA, + DENALI_PHY_622_DATA, + DENALI_PHY_623_DATA, + DENALI_PHY_624_DATA, + DENALI_PHY_625_DATA, + DENALI_PHY_626_DATA, + DENALI_PHY_627_DATA, + DENALI_PHY_628_DATA, + DENALI_PHY_629_DATA, + DENALI_PHY_630_DATA, + DENALI_PHY_631_DATA, + DENALI_PHY_632_DATA, + DENALI_PHY_633_DATA, + DENALI_PHY_634_DATA, + DENALI_PHY_635_DATA, + DENALI_PHY_636_DATA, + DENALI_PHY_637_DATA, + DENALI_PHY_638_DATA, + DENALI_PHY_639_DATA, + DENALI_PHY_640_DATA, + DENALI_PHY_641_DATA, + DENALI_PHY_642_DATA, + DENALI_PHY_643_DATA, + DENALI_PHY_644_DATA, + DENALI_PHY_645_DATA, + DENALI_PHY_646_DATA, + DENALI_PHY_647_DATA, + DENALI_PHY_648_DATA, + DENALI_PHY_649_DATA, + DENALI_PHY_650_DATA, + DENALI_PHY_651_DATA, + DENALI_PHY_652_DATA, + DENALI_PHY_653_DATA, + DENALI_PHY_654_DATA, + DENALI_PHY_655_DATA, + DENALI_PHY_656_DATA, + DENALI_PHY_657_DATA, + DENALI_PHY_658_DATA, + DENALI_PHY_659_DATA, + DENALI_PHY_660_DATA, + DENALI_PHY_661_DATA, + DENALI_PHY_662_DATA, + DENALI_PHY_663_DATA, + DENALI_PHY_664_DATA, + DENALI_PHY_665_DATA, + DENALI_PHY_666_DATA, + DENALI_PHY_667_DATA, + DENALI_PHY_668_DATA, + DENALI_PHY_669_DATA, + DENALI_PHY_670_DATA, + DENALI_PHY_671_DATA, + DENALI_PHY_672_DATA, + DENALI_PHY_673_DATA, + DENALI_PHY_674_DATA, + DENALI_PHY_675_DATA, + DENALI_PHY_676_DATA, + DENALI_PHY_677_DATA, + DENALI_PHY_678_DATA, + DENALI_PHY_679_DATA, + DENALI_PHY_680_DATA, + DENALI_PHY_681_DATA, + DENALI_PHY_682_DATA, + DENALI_PHY_683_DATA, + DENALI_PHY_684_DATA, + DENALI_PHY_685_DATA, + DENALI_PHY_686_DATA, + DENALI_PHY_687_DATA, + DENALI_PHY_688_DATA, + DENALI_PHY_689_DATA, + DENALI_PHY_690_DATA, + DENALI_PHY_691_DATA, + DENALI_PHY_692_DATA, + DENALI_PHY_693_DATA, + DENALI_PHY_694_DATA, + DENALI_PHY_695_DATA, + DENALI_PHY_696_DATA, + DENALI_PHY_697_DATA, + DENALI_PHY_698_DATA, + DENALI_PHY_699_DATA, + DENALI_PHY_700_DATA, + DENALI_PHY_701_DATA, + DENALI_PHY_702_DATA, + DENALI_PHY_703_DATA, + DENALI_PHY_704_DATA, + DENALI_PHY_705_DATA, + DENALI_PHY_706_DATA, + DENALI_PHY_707_DATA, + DENALI_PHY_708_DATA, + DENALI_PHY_709_DATA, + DENALI_PHY_710_DATA, + DENALI_PHY_711_DATA, + DENALI_PHY_712_DATA, + DENALI_PHY_713_DATA, + DENALI_PHY_714_DATA, + DENALI_PHY_715_DATA, + DENALI_PHY_716_DATA, + DENALI_PHY_717_DATA, + DENALI_PHY_718_DATA, + DENALI_PHY_719_DATA, + DENALI_PHY_720_DATA, + DENALI_PHY_721_DATA, + DENALI_PHY_722_DATA, + DENALI_PHY_723_DATA, + DENALI_PHY_724_DATA, + DENALI_PHY_725_DATA, + DENALI_PHY_726_DATA, + DENALI_PHY_727_DATA, + DENALI_PHY_728_DATA, + DENALI_PHY_729_DATA, + DENALI_PHY_730_DATA, + DENALI_PHY_731_DATA, + DENALI_PHY_732_DATA, + DENALI_PHY_733_DATA, + DENALI_PHY_734_DATA, + DENALI_PHY_735_DATA, + DENALI_PHY_736_DATA, + DENALI_PHY_737_DATA, + DENALI_PHY_738_DATA, + DENALI_PHY_739_DATA, + DENALI_PHY_740_DATA, + DENALI_PHY_741_DATA, + DENALI_PHY_742_DATA, + DENALI_PHY_743_DATA, + DENALI_PHY_744_DATA, + DENALI_PHY_745_DATA, + DENALI_PHY_746_DATA, + DENALI_PHY_747_DATA, + DENALI_PHY_748_DATA, + DENALI_PHY_749_DATA, + DENALI_PHY_750_DATA, + DENALI_PHY_751_DATA, + DENALI_PHY_752_DATA, + DENALI_PHY_753_DATA, + DENALI_PHY_754_DATA, + DENALI_PHY_755_DATA, + DENALI_PHY_756_DATA, + DENALI_PHY_757_DATA, + DENALI_PHY_758_DATA, + DENALI_PHY_759_DATA, + DENALI_PHY_760_DATA, + DENALI_PHY_761_DATA, + DENALI_PHY_762_DATA, + DENALI_PHY_763_DATA, + DENALI_PHY_764_DATA, + DENALI_PHY_765_DATA, + DENALI_PHY_766_DATA, + DENALI_PHY_767_DATA, + DENALI_PHY_768_DATA, + DENALI_PHY_769_DATA, + DENALI_PHY_770_DATA, + DENALI_PHY_771_DATA, + DENALI_PHY_772_DATA, + DENALI_PHY_773_DATA, + DENALI_PHY_774_DATA, + DENALI_PHY_775_DATA, + DENALI_PHY_776_DATA, + DENALI_PHY_777_DATA, + DENALI_PHY_778_DATA, + DENALI_PHY_779_DATA, + DENALI_PHY_780_DATA, + DENALI_PHY_781_DATA, + DENALI_PHY_782_DATA, + DENALI_PHY_783_DATA, + DENALI_PHY_784_DATA, + DENALI_PHY_785_DATA, + DENALI_PHY_786_DATA, + DENALI_PHY_787_DATA, + DENALI_PHY_788_DATA, + DENALI_PHY_789_DATA, + DENALI_PHY_790_DATA, + DENALI_PHY_791_DATA, + DENALI_PHY_792_DATA, + DENALI_PHY_793_DATA, + DENALI_PHY_794_DATA, + DENALI_PHY_795_DATA, + DENALI_PHY_796_DATA, + DENALI_PHY_797_DATA, + DENALI_PHY_798_DATA, + DENALI_PHY_799_DATA, + DENALI_PHY_800_DATA, + DENALI_PHY_801_DATA, + DENALI_PHY_802_DATA, + DENALI_PHY_803_DATA, + DENALI_PHY_804_DATA, + DENALI_PHY_805_DATA, + DENALI_PHY_806_DATA, + DENALI_PHY_807_DATA, + DENALI_PHY_808_DATA, + DENALI_PHY_809_DATA, + DENALI_PHY_810_DATA, + DENALI_PHY_811_DATA, + DENALI_PHY_812_DATA, + DENALI_PHY_813_DATA, + DENALI_PHY_814_DATA, + DENALI_PHY_815_DATA, + DENALI_PHY_816_DATA, + DENALI_PHY_817_DATA, + DENALI_PHY_818_DATA, + DENALI_PHY_819_DATA, + DENALI_PHY_820_DATA, + DENALI_PHY_821_DATA, + DENALI_PHY_822_DATA, + DENALI_PHY_823_DATA, + DENALI_PHY_824_DATA, + DENALI_PHY_825_DATA, + DENALI_PHY_826_DATA, + DENALI_PHY_827_DATA, + DENALI_PHY_828_DATA, + DENALI_PHY_829_DATA, + DENALI_PHY_830_DATA, + DENALI_PHY_831_DATA, + DENALI_PHY_832_DATA, + DENALI_PHY_833_DATA, + DENALI_PHY_834_DATA, + DENALI_PHY_835_DATA, + DENALI_PHY_836_DATA, + DENALI_PHY_837_DATA, + DENALI_PHY_838_DATA, + DENALI_PHY_839_DATA, + DENALI_PHY_840_DATA, + DENALI_PHY_841_DATA, + DENALI_PHY_842_DATA, + DENALI_PHY_843_DATA, + DENALI_PHY_844_DATA, + DENALI_PHY_845_DATA, + DENALI_PHY_846_DATA, + DENALI_PHY_847_DATA, + DENALI_PHY_848_DATA, + DENALI_PHY_849_DATA, + DENALI_PHY_850_DATA, + DENALI_PHY_851_DATA, + DENALI_PHY_852_DATA, + DENALI_PHY_853_DATA, + DENALI_PHY_854_DATA, + DENALI_PHY_855_DATA, + DENALI_PHY_856_DATA, + DENALI_PHY_857_DATA, + DENALI_PHY_858_DATA, + DENALI_PHY_859_DATA, + DENALI_PHY_860_DATA, + DENALI_PHY_861_DATA, + DENALI_PHY_862_DATA, + DENALI_PHY_863_DATA, + DENALI_PHY_864_DATA, + DENALI_PHY_865_DATA, + DENALI_PHY_866_DATA, + DENALI_PHY_867_DATA, + DENALI_PHY_868_DATA, + DENALI_PHY_869_DATA, + DENALI_PHY_870_DATA, + DENALI_PHY_871_DATA, + DENALI_PHY_872_DATA, + DENALI_PHY_873_DATA, + DENALI_PHY_874_DATA, + DENALI_PHY_875_DATA, + DENALI_PHY_876_DATA, + DENALI_PHY_877_DATA, + DENALI_PHY_878_DATA, + DENALI_PHY_879_DATA, + DENALI_PHY_880_DATA, + DENALI_PHY_881_DATA, + DENALI_PHY_882_DATA, + DENALI_PHY_883_DATA, + DENALI_PHY_884_DATA, + DENALI_PHY_885_DATA, + DENALI_PHY_886_DATA, + DENALI_PHY_887_DATA, + DENALI_PHY_888_DATA, + DENALI_PHY_889_DATA, + DENALI_PHY_890_DATA, + DENALI_PHY_891_DATA, + DENALI_PHY_892_DATA, + DENALI_PHY_893_DATA, + DENALI_PHY_894_DATA, + DENALI_PHY_895_DATA, + DENALI_PHY_896_DATA, + DENALI_PHY_897_DATA, + DENALI_PHY_898_DATA, + DENALI_PHY_899_DATA, + DENALI_PHY_900_DATA, + DENALI_PHY_901_DATA, + DENALI_PHY_902_DATA, + DENALI_PHY_903_DATA, + DENALI_PHY_904_DATA, + DENALI_PHY_905_DATA, + DENALI_PHY_906_DATA, + DENALI_PHY_907_DATA, + DENALI_PHY_908_DATA, + DENALI_PHY_909_DATA, + DENALI_PHY_910_DATA, + DENALI_PHY_911_DATA, + DENALI_PHY_912_DATA, + DENALI_PHY_913_DATA, + DENALI_PHY_914_DATA, + DENALI_PHY_915_DATA, + DENALI_PHY_916_DATA, + DENALI_PHY_917_DATA, + DENALI_PHY_918_DATA, + DENALI_PHY_919_DATA, + DENALI_PHY_920_DATA, + DENALI_PHY_921_DATA, + DENALI_PHY_922_DATA, + DENALI_PHY_923_DATA, + DENALI_PHY_924_DATA, + DENALI_PHY_925_DATA, + DENALI_PHY_926_DATA, + DENALI_PHY_927_DATA, + DENALI_PHY_928_DATA, + DENALI_PHY_929_DATA, + DENALI_PHY_930_DATA, + DENALI_PHY_931_DATA, + DENALI_PHY_932_DATA, + DENALI_PHY_933_DATA, + DENALI_PHY_934_DATA, + DENALI_PHY_935_DATA, + DENALI_PHY_936_DATA, + DENALI_PHY_937_DATA, + DENALI_PHY_938_DATA, + DENALI_PHY_939_DATA, + DENALI_PHY_940_DATA, + DENALI_PHY_941_DATA, + DENALI_PHY_942_DATA, + DENALI_PHY_943_DATA, + DENALI_PHY_944_DATA, + DENALI_PHY_945_DATA, + DENALI_PHY_946_DATA, + DENALI_PHY_947_DATA, + DENALI_PHY_948_DATA, + DENALI_PHY_949_DATA, + DENALI_PHY_950_DATA, + DENALI_PHY_951_DATA, + DENALI_PHY_952_DATA, + DENALI_PHY_953_DATA, + DENALI_PHY_954_DATA, + DENALI_PHY_955_DATA, + DENALI_PHY_956_DATA, + DENALI_PHY_957_DATA, + DENALI_PHY_958_DATA, + DENALI_PHY_959_DATA, + DENALI_PHY_960_DATA, + DENALI_PHY_961_DATA, + DENALI_PHY_962_DATA, + DENALI_PHY_963_DATA, + DENALI_PHY_964_DATA, + DENALI_PHY_965_DATA, + DENALI_PHY_966_DATA, + DENALI_PHY_967_DATA, + DENALI_PHY_968_DATA, + DENALI_PHY_969_DATA, + DENALI_PHY_970_DATA, + DENALI_PHY_971_DATA, + DENALI_PHY_972_DATA, + DENALI_PHY_973_DATA, + DENALI_PHY_974_DATA, + DENALI_PHY_975_DATA, + DENALI_PHY_976_DATA, + DENALI_PHY_977_DATA, + DENALI_PHY_978_DATA, + DENALI_PHY_979_DATA, + DENALI_PHY_980_DATA, + DENALI_PHY_981_DATA, + DENALI_PHY_982_DATA, + DENALI_PHY_983_DATA, + DENALI_PHY_984_DATA, + DENALI_PHY_985_DATA, + DENALI_PHY_986_DATA, + DENALI_PHY_987_DATA, + DENALI_PHY_988_DATA, + DENALI_PHY_989_DATA, + DENALI_PHY_990_DATA, + DENALI_PHY_991_DATA, + DENALI_PHY_992_DATA, + DENALI_PHY_993_DATA, + DENALI_PHY_994_DATA, + DENALI_PHY_995_DATA, + DENALI_PHY_996_DATA, + DENALI_PHY_997_DATA, + DENALI_PHY_998_DATA, + DENALI_PHY_999_DATA, + DENALI_PHY_1000_DATA, + DENALI_PHY_1001_DATA, + DENALI_PHY_1002_DATA, + DENALI_PHY_1003_DATA, + DENALI_PHY_1004_DATA, + DENALI_PHY_1005_DATA, + DENALI_PHY_1006_DATA, + DENALI_PHY_1007_DATA, + DENALI_PHY_1008_DATA, + DENALI_PHY_1009_DATA, + DENALI_PHY_1010_DATA, + DENALI_PHY_1011_DATA, + DENALI_PHY_1012_DATA, + DENALI_PHY_1013_DATA, + DENALI_PHY_1014_DATA, + DENALI_PHY_1015_DATA, + DENALI_PHY_1016_DATA, + DENALI_PHY_1017_DATA, + DENALI_PHY_1018_DATA, + DENALI_PHY_1019_DATA, + DENALI_PHY_1020_DATA, + DENALI_PHY_1021_DATA, + DENALI_PHY_1022_DATA, + DENALI_PHY_1023_DATA, + DENALI_PHY_1024_DATA, + DENALI_PHY_1025_DATA, + DENALI_PHY_1026_DATA, + DENALI_PHY_1027_DATA, + DENALI_PHY_1028_DATA, + DENALI_PHY_1029_DATA, + DENALI_PHY_1030_DATA, + DENALI_PHY_1031_DATA, + DENALI_PHY_1032_DATA, + DENALI_PHY_1033_DATA, + DENALI_PHY_1034_DATA, + DENALI_PHY_1035_DATA, + DENALI_PHY_1036_DATA, + DENALI_PHY_1037_DATA, + DENALI_PHY_1038_DATA, + DENALI_PHY_1039_DATA, + DENALI_PHY_1040_DATA, + DENALI_PHY_1041_DATA, + DENALI_PHY_1042_DATA, + DENALI_PHY_1043_DATA, + DENALI_PHY_1044_DATA, + DENALI_PHY_1045_DATA, + DENALI_PHY_1046_DATA, + DENALI_PHY_1047_DATA, + DENALI_PHY_1048_DATA, + DENALI_PHY_1049_DATA, + DENALI_PHY_1050_DATA, + DENALI_PHY_1051_DATA, + DENALI_PHY_1052_DATA, + DENALI_PHY_1053_DATA, + DENALI_PHY_1054_DATA, + DENALI_PHY_1055_DATA, + DENALI_PHY_1056_DATA, + DENALI_PHY_1057_DATA, + DENALI_PHY_1058_DATA, + DENALI_PHY_1059_DATA, + DENALI_PHY_1060_DATA, + DENALI_PHY_1061_DATA, + DENALI_PHY_1062_DATA, + DENALI_PHY_1063_DATA, + DENALI_PHY_1064_DATA, + DENALI_PHY_1065_DATA, + DENALI_PHY_1066_DATA, + DENALI_PHY_1067_DATA, + DENALI_PHY_1068_DATA, + DENALI_PHY_1069_DATA, + DENALI_PHY_1070_DATA, + DENALI_PHY_1071_DATA, + DENALI_PHY_1072_DATA, + DENALI_PHY_1073_DATA, + DENALI_PHY_1074_DATA, + DENALI_PHY_1075_DATA, + DENALI_PHY_1076_DATA, + DENALI_PHY_1077_DATA, + DENALI_PHY_1078_DATA, + DENALI_PHY_1079_DATA, + DENALI_PHY_1080_DATA, + DENALI_PHY_1081_DATA, + DENALI_PHY_1082_DATA, + DENALI_PHY_1083_DATA, + DENALI_PHY_1084_DATA, + DENALI_PHY_1085_DATA, + DENALI_PHY_1086_DATA, + DENALI_PHY_1087_DATA, + DENALI_PHY_1088_DATA, + DENALI_PHY_1089_DATA, + DENALI_PHY_1090_DATA, + DENALI_PHY_1091_DATA, + DENALI_PHY_1092_DATA, + DENALI_PHY_1093_DATA, + DENALI_PHY_1094_DATA, + DENALI_PHY_1095_DATA, + DENALI_PHY_1096_DATA, + DENALI_PHY_1097_DATA, + DENALI_PHY_1098_DATA, + DENALI_PHY_1099_DATA, + DENALI_PHY_1100_DATA, + DENALI_PHY_1101_DATA, + DENALI_PHY_1102_DATA, + DENALI_PHY_1103_DATA, + DENALI_PHY_1104_DATA, + DENALI_PHY_1105_DATA, + DENALI_PHY_1106_DATA, + DENALI_PHY_1107_DATA, + DENALI_PHY_1108_DATA, + DENALI_PHY_1109_DATA, + DENALI_PHY_1110_DATA, + DENALI_PHY_1111_DATA, + DENALI_PHY_1112_DATA, + DENALI_PHY_1113_DATA, + DENALI_PHY_1114_DATA, + DENALI_PHY_1115_DATA, + DENALI_PHY_1116_DATA, + DENALI_PHY_1117_DATA, + DENALI_PHY_1118_DATA, + DENALI_PHY_1119_DATA, + DENALI_PHY_1120_DATA, + DENALI_PHY_1121_DATA, + DENALI_PHY_1122_DATA, + DENALI_PHY_1123_DATA, + DENALI_PHY_1124_DATA, + DENALI_PHY_1125_DATA, + DENALI_PHY_1126_DATA, + DENALI_PHY_1127_DATA, + DENALI_PHY_1128_DATA, + DENALI_PHY_1129_DATA, + DENALI_PHY_1130_DATA, + DENALI_PHY_1131_DATA, + DENALI_PHY_1132_DATA, + DENALI_PHY_1133_DATA, + DENALI_PHY_1134_DATA, + DENALI_PHY_1135_DATA, + DENALI_PHY_1136_DATA, + DENALI_PHY_1137_DATA, + DENALI_PHY_1138_DATA, + DENALI_PHY_1139_DATA, + DENALI_PHY_1140_DATA, + DENALI_PHY_1141_DATA, + DENALI_PHY_1142_DATA, + DENALI_PHY_1143_DATA, + DENALI_PHY_1144_DATA, + DENALI_PHY_1145_DATA, + DENALI_PHY_1146_DATA, + DENALI_PHY_1147_DATA, + DENALI_PHY_1148_DATA, + DENALI_PHY_1149_DATA, + DENALI_PHY_1150_DATA, + DENALI_PHY_1151_DATA, + DENALI_PHY_1152_DATA, + DENALI_PHY_1153_DATA, + DENALI_PHY_1154_DATA, + DENALI_PHY_1155_DATA, + DENALI_PHY_1156_DATA, + DENALI_PHY_1157_DATA, + DENALI_PHY_1158_DATA, + DENALI_PHY_1159_DATA, + DENALI_PHY_1160_DATA, + DENALI_PHY_1161_DATA, + DENALI_PHY_1162_DATA, + DENALI_PHY_1163_DATA, + DENALI_PHY_1164_DATA, + DENALI_PHY_1165_DATA, + DENALI_PHY_1166_DATA, + DENALI_PHY_1167_DATA, + DENALI_PHY_1168_DATA, + DENALI_PHY_1169_DATA, + DENALI_PHY_1170_DATA, + DENALI_PHY_1171_DATA, + DENALI_PHY_1172_DATA, + DENALI_PHY_1173_DATA, + DENALI_PHY_1174_DATA, + DENALI_PHY_1175_DATA, + DENALI_PHY_1176_DATA, + DENALI_PHY_1177_DATA, + DENALI_PHY_1178_DATA, + DENALI_PHY_1179_DATA, + DENALI_PHY_1180_DATA, + DENALI_PHY_1181_DATA, + DENALI_PHY_1182_DATA, + DENALI_PHY_1183_DATA, + DENALI_PHY_1184_DATA, + DENALI_PHY_1185_DATA, + DENALI_PHY_1186_DATA, + DENALI_PHY_1187_DATA, + DENALI_PHY_1188_DATA, + DENALI_PHY_1189_DATA, + DENALI_PHY_1190_DATA, + DENALI_PHY_1191_DATA, + DENALI_PHY_1192_DATA, + DENALI_PHY_1193_DATA, + DENALI_PHY_1194_DATA, + DENALI_PHY_1195_DATA, + DENALI_PHY_1196_DATA, + DENALI_PHY_1197_DATA, + DENALI_PHY_1198_DATA, + DENALI_PHY_1199_DATA, + DENALI_PHY_1200_DATA, + DENALI_PHY_1201_DATA, + DENALI_PHY_1202_DATA, + DENALI_PHY_1203_DATA, + DENALI_PHY_1204_DATA, + DENALI_PHY_1205_DATA, + DENALI_PHY_1206_DATA, + DENALI_PHY_1207_DATA, + DENALI_PHY_1208_DATA, + DENALI_PHY_1209_DATA, + DENALI_PHY_1210_DATA, + DENALI_PHY_1211_DATA, + DENALI_PHY_1212_DATA, + DENALI_PHY_1213_DATA, + DENALI_PHY_1214_DATA, +}; +const uint32_t denali_ddr_ctl_data[265] = { + DENALI_CTL_00_DATA, + DENALI_CTL_01_DATA, + DENALI_CTL_02_DATA, + DENALI_CTL_03_DATA, + DENALI_CTL_04_DATA, + DENALI_CTL_05_DATA, + DENALI_CTL_06_DATA, + DENALI_CTL_07_DATA, + DENALI_CTL_08_DATA, + DENALI_CTL_09_DATA, + DENALI_CTL_10_DATA, + DENALI_CTL_11_DATA, + DENALI_CTL_12_DATA, + DENALI_CTL_13_DATA, + DENALI_CTL_14_DATA, + DENALI_CTL_15_DATA, + DENALI_CTL_16_DATA, + DENALI_CTL_17_DATA, + DENALI_CTL_18_DATA, + DENALI_CTL_19_DATA, + DENALI_CTL_20_DATA, + DENALI_CTL_21_DATA, + DENALI_CTL_22_DATA, + DENALI_CTL_23_DATA, + DENALI_CTL_24_DATA, + DENALI_CTL_25_DATA, + DENALI_CTL_26_DATA, + DENALI_CTL_27_DATA, + DENALI_CTL_28_DATA, + DENALI_CTL_29_DATA, + DENALI_CTL_30_DATA, + DENALI_CTL_31_DATA, + DENALI_CTL_32_DATA, + DENALI_CTL_33_DATA, + DENALI_CTL_34_DATA, + DENALI_CTL_35_DATA, + DENALI_CTL_36_DATA, + DENALI_CTL_37_DATA, + DENALI_CTL_38_DATA, + DENALI_CTL_39_DATA, + DENALI_CTL_40_DATA, + DENALI_CTL_41_DATA, + DENALI_CTL_42_DATA, + DENALI_CTL_43_DATA, + DENALI_CTL_44_DATA, + DENALI_CTL_45_DATA, + DENALI_CTL_46_DATA, + DENALI_CTL_47_DATA, + DENALI_CTL_48_DATA, + DENALI_CTL_49_DATA, + DENALI_CTL_50_DATA, + DENALI_CTL_51_DATA, + DENALI_CTL_52_DATA, + DENALI_CTL_53_DATA, + DENALI_CTL_54_DATA, + DENALI_CTL_55_DATA, + DENALI_CTL_56_DATA, + DENALI_CTL_57_DATA, + DENALI_CTL_58_DATA, + DENALI_CTL_59_DATA, + DENALI_CTL_60_DATA, + DENALI_CTL_61_DATA, + DENALI_CTL_62_DATA, + DENALI_CTL_63_DATA, + DENALI_CTL_64_DATA, + DENALI_CTL_65_DATA, + DENALI_CTL_66_DATA, + DENALI_CTL_67_DATA, + DENALI_CTL_68_DATA, + DENALI_CTL_69_DATA, + DENALI_CTL_70_DATA, + DENALI_CTL_71_DATA, + DENALI_CTL_72_DATA, + DENALI_CTL_73_DATA, + DENALI_CTL_74_DATA, + DENALI_CTL_75_DATA, + DENALI_CTL_76_DATA, + DENALI_CTL_77_DATA, + DENALI_CTL_78_DATA, + DENALI_CTL_79_DATA, + DENALI_CTL_80_DATA, + DENALI_CTL_81_DATA, + DENALI_CTL_82_DATA, + DENALI_CTL_83_DATA, + DENALI_CTL_84_DATA, + DENALI_CTL_85_DATA, + DENALI_CTL_86_DATA, + DENALI_CTL_87_DATA, + DENALI_CTL_88_DATA, + DENALI_CTL_89_DATA, + DENALI_CTL_90_DATA, + DENALI_CTL_91_DATA, + DENALI_CTL_92_DATA, + DENALI_CTL_93_DATA, + DENALI_CTL_94_DATA, + DENALI_CTL_95_DATA, + DENALI_CTL_96_DATA, + DENALI_CTL_97_DATA, + DENALI_CTL_98_DATA, + DENALI_CTL_99_DATA, + DENALI_CTL_100_DATA, + DENALI_CTL_101_DATA, + DENALI_CTL_102_DATA, + DENALI_CTL_103_DATA, + DENALI_CTL_104_DATA, + DENALI_CTL_105_DATA, + DENALI_CTL_106_DATA, + DENALI_CTL_107_DATA, + DENALI_CTL_108_DATA, + DENALI_CTL_109_DATA, + DENALI_CTL_110_DATA, + DENALI_CTL_111_DATA, + DENALI_CTL_112_DATA, + DENALI_CTL_113_DATA, + DENALI_CTL_114_DATA, + DENALI_CTL_115_DATA, + DENALI_CTL_116_DATA, + DENALI_CTL_117_DATA, + DENALI_CTL_118_DATA, + DENALI_CTL_119_DATA, + DENALI_CTL_120_DATA, + DENALI_CTL_121_DATA, + DENALI_CTL_122_DATA, + DENALI_CTL_123_DATA, + DENALI_CTL_124_DATA, + DENALI_CTL_125_DATA, + DENALI_CTL_126_DATA, + DENALI_CTL_127_DATA, + DENALI_CTL_128_DATA, + DENALI_CTL_129_DATA, + DENALI_CTL_130_DATA, + DENALI_CTL_131_DATA, + DENALI_CTL_132_DATA, + DENALI_CTL_133_DATA, + DENALI_CTL_134_DATA, + DENALI_CTL_135_DATA, + DENALI_CTL_136_DATA, + DENALI_CTL_137_DATA, + DENALI_CTL_138_DATA, + DENALI_CTL_139_DATA, + DENALI_CTL_140_DATA, + DENALI_CTL_141_DATA, + DENALI_CTL_142_DATA, + DENALI_CTL_143_DATA, + DENALI_CTL_144_DATA, + DENALI_CTL_145_DATA, + DENALI_CTL_146_DATA, + DENALI_CTL_147_DATA, + DENALI_CTL_148_DATA, + DENALI_CTL_149_DATA, + DENALI_CTL_150_DATA, + DENALI_CTL_151_DATA, + DENALI_CTL_152_DATA, + DENALI_CTL_153_DATA, + DENALI_CTL_154_DATA, + DENALI_CTL_155_DATA, + DENALI_CTL_156_DATA, + DENALI_CTL_157_DATA, + DENALI_CTL_158_DATA, + DENALI_CTL_159_DATA, + DENALI_CTL_160_DATA, + DENALI_CTL_161_DATA, + DENALI_CTL_162_DATA, + DENALI_CTL_163_DATA, + DENALI_CTL_164_DATA, + DENALI_CTL_165_DATA, + DENALI_CTL_166_DATA, + DENALI_CTL_167_DATA, + DENALI_CTL_168_DATA, + DENALI_CTL_169_DATA, + DENALI_CTL_170_DATA, + DENALI_CTL_171_DATA, + DENALI_CTL_172_DATA, + DENALI_CTL_173_DATA, + DENALI_CTL_174_DATA, + DENALI_CTL_175_DATA, + DENALI_CTL_176_DATA, + DENALI_CTL_177_DATA, + DENALI_CTL_178_DATA, + DENALI_CTL_179_DATA, + DENALI_CTL_180_DATA, + DENALI_CTL_181_DATA, + DENALI_CTL_182_DATA, + DENALI_CTL_183_DATA, + DENALI_CTL_184_DATA, + DENALI_CTL_185_DATA, + DENALI_CTL_186_DATA, + DENALI_CTL_187_DATA, + DENALI_CTL_188_DATA, + DENALI_CTL_189_DATA, + DENALI_CTL_190_DATA, + DENALI_CTL_191_DATA, + DENALI_CTL_192_DATA, + DENALI_CTL_193_DATA, + DENALI_CTL_194_DATA, + DENALI_CTL_195_DATA, + DENALI_CTL_196_DATA, + DENALI_CTL_197_DATA, + DENALI_CTL_198_DATA, + DENALI_CTL_199_DATA, + DENALI_CTL_200_DATA, + DENALI_CTL_201_DATA, + DENALI_CTL_202_DATA, + DENALI_CTL_203_DATA, + DENALI_CTL_204_DATA, + DENALI_CTL_205_DATA, + DENALI_CTL_206_DATA, + DENALI_CTL_207_DATA, + DENALI_CTL_208_DATA, + DENALI_CTL_209_DATA, + DENALI_CTL_210_DATA, + DENALI_CTL_211_DATA, + DENALI_CTL_212_DATA, + DENALI_CTL_213_DATA, + DENALI_CTL_214_DATA, + DENALI_CTL_215_DATA, + DENALI_CTL_216_DATA, + DENALI_CTL_217_DATA, + DENALI_CTL_218_DATA, + DENALI_CTL_219_DATA, + DENALI_CTL_220_DATA, + DENALI_CTL_221_DATA, + DENALI_CTL_222_DATA, + DENALI_CTL_223_DATA, + DENALI_CTL_224_DATA, + DENALI_CTL_225_DATA, + DENALI_CTL_226_DATA, + DENALI_CTL_227_DATA, + DENALI_CTL_228_DATA, + DENALI_CTL_229_DATA, + DENALI_CTL_230_DATA, + DENALI_CTL_231_DATA, + DENALI_CTL_232_DATA, + DENALI_CTL_233_DATA, + DENALI_CTL_234_DATA, + DENALI_CTL_235_DATA, + DENALI_CTL_236_DATA, + DENALI_CTL_237_DATA, + DENALI_CTL_238_DATA, + DENALI_CTL_239_DATA, + DENALI_CTL_240_DATA, + DENALI_CTL_241_DATA, + DENALI_CTL_242_DATA, + DENALI_CTL_243_DATA, + DENALI_CTL_244_DATA, + DENALI_CTL_245_DATA, + DENALI_CTL_246_DATA, + DENALI_CTL_247_DATA, + DENALI_CTL_248_DATA, + DENALI_CTL_249_DATA, + DENALI_CTL_250_DATA, + DENALI_CTL_251_DATA, + DENALI_CTL_252_DATA, + DENALI_CTL_253_DATA, + DENALI_CTL_254_DATA, + DENALI_CTL_255_DATA, + DENALI_CTL_256_DATA, + DENALI_CTL_257_DATA, + DENALI_CTL_258_DATA, + DENALI_CTL_259_DATA, + DENALI_CTL_260_DATA, + DENALI_CTL_261_DATA, + DENALI_CTL_262_DATA, + DENALI_CTL_263_DATA, + DENALI_CTL_264_DATA, +}; diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c new file mode 100644 index 0000000..167844d --- /dev/null +++ b/src/soc/sifive/fu740/gpio.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <stdint.h> +#include <arch/mmio.h> +#include <delay.h> +#include <assert.h> +#include <device/mmio.h> +#include <gpio.h> + +#define SIFIVE_GPIO_INPUT_VAL (FU740_GPIO + 0x00) +#define SIFIVE_GPIO_INPUT_EN (FU740_GPIO + 0x04) +#define SIFIVE_GPIO_OUTPUT_EN (FU740_GPIO + 0x08) +#define SIFIVE_GPIO_OUTPUT_VAL (FU740_GPIO + 0x0C) +#define SIFIVE_GPIO_PUE (FU740_GPIO + 0x10) +#define SIFIVE_GPIO_DS (FU740_GPIO + 0x14) +#define SIFIVE_GPIO_RISE_IE (FU740_GPIO + 0x18) +#define SIFIVE_GPIO_RISE_IP (FU740_GPIO + 0x1C) +#define SIFIVE_GPIO_FALL_IE (FU740_GPIO + 0x20) +#define SIFIVE_GPIO_FALL_IP (FU740_GPIO + 0x24) +#define SIFIVE_GPIO_HIGH_IE (FU740_GPIO + 0x28) +#define SIFIVE_GPIO_HIGH_IP (FU740_GPIO + 0x2C) +#define SIFIVE_GPIO_LOW_IE (FU740_GPIO + 0x30) +#define SIFIVE_GPIO_LOW_IP (FU740_GPIO + 0x34) +#define SIFIVE_GPIO_IOF_EN (FU740_GPIO + 0x38) +#define SIFIVE_GPIO_IOF_SEL (FU740_GPIO + 0x3C) +#define SIFIVE_GPIO_OUT_XOR (FU740_GPIO + 0x40) + +void gpio_set(gpio_t gpio, int value) +{ + uint32_t output_val = read32((void *)SIFIVE_GPIO_OUTPUT_VAL); + + if (value) + output_val |= (1 << gpio); + else + output_val &= ~(1 << gpio); + + write32((void *)SIFIVE_GPIO_OUTPUT_VAL, output_val); +} + +int gpio_get(gpio_t gpio) +{ + uint32_t input_val = read32((void *)SIFIVE_GPIO_INPUT_VAL); + return !!(input_val & (1 << gpio)); +} + +void gpio_set_direction(gpio_t gpio, enum gpio_direction gpio_dir) +{ + uint32_t input_en = read32((void *)SIFIVE_GPIO_INPUT_EN); + uint32_t output_en = read32((void *)SIFIVE_GPIO_OUTPUT_EN); + + if (gpio_dir == GPIO_OUTPUT) { + input_en &= ~(1 << gpio); + output_en |= (1 << gpio); + } else if (gpio_dir == GPIO_INPUT) { + input_en |= (1 << gpio); + output_en &= ~(1 << gpio); + } + + write32((void *)SIFIVE_GPIO_INPUT_EN, input_en); + write32((void *)SIFIVE_GPIO_OUTPUT_EN, output_en); +} diff --git a/src/soc/sifive/fu740/include/soc/addressmap.h b/src/soc/sifive/fu740/include/soc/addressmap.h new file mode 100644 index 0000000..a4b0d54 --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/addressmap.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// reference: fu740-c000 manual chapter 5: Memory Map +// Table 15: (TODO: subject for common code: none of these changed compared to fu540) +#define FU740_ROM 0x00001000 +#define FU740_DTIM 0x01000000 +#define FU740_CLINT 0x02000000 +#define FU740_L2LIM 0x08000000 +#define FU740_PRCI 0x10000000 +#define FU740_UART0 0x10010000 +#define FU740_UART1 0x10011000 +#define FU740_QSPI0 0x10040000 +#define FU740_QSPI1 0x10041000 +#define FU740_QSPI2 0x10050000 // in unmatched board schematics it's called SPI0 +#define FU740_GPIO 0x10060000 +#define FU740_OTP 0x10070000 +#define FU740_PINCTRL 0x10080000 +#define FU740_DDRCTRL 0x100b0000 +#define FU740_DDRPHY 0x100b2000 +#define FU740_DDRMGMT 0x100c0000 +#define FU740_QSPI0FLASH 0x20000000 +#define FU740_QSPI1FLASH 0x30000000 +#define FU740_DRAM 0x80000000 + +#define PCIE_MGMT 0x100D0000 +#define PCIE_CONFIG 0x000D_F000_0000 +#define PCIE_DBI 0x000E_0000_0000 + +#define FU740_I2C_0 0x10030000 +#define FU740_I2C_1 0x10031000 + +// Reset Vector - 4 +#define FU740_ROM1 0x00001000 +// After reset vector it will jump directly to this address if ZSBL is used (ZSBL code) +#define FU740_ROM2 0x00010000 +#define FU740_MSEL FU740_ROM // mode select is always at start of ROM + +// naming changed a bit between FU540 and FU740 manuals +// Ethernet MAC -> Ethernet +// Ethernet Management -> GEMGXL MGMT +#define SIFIVE_ETHERNET_MAC 0x10090000 +#define SIFIVE_ETHERNET_MGMT 0x100A0000 + +#define FU740_UART(i) (FU740_UART0 + 0x1000 * i) diff --git a/src/soc/sifive/fu740/include/soc/clock.h b/src/soc/sifive/fu740/include/soc/clock.h new file mode 100644 index 0000000..01cb1b3 --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/clock.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SIFIVE_FU740_CLOCK_H__ +#define __SOC_SIFIVE_FU740_CLOCK_H__ + +void clock_init(void); +int clock_get_pclk(void); + +#endif /* __SOC_SIFIVE_FU740_CLOCK_H__ */ diff --git a/src/soc/sifive/fu740/include/soc/gpio.h b/src/soc/sifive/fu740/include/soc/gpio.h new file mode 100644 index 0000000..b0466cc --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/gpio.h @@ -0,0 +1,36 @@ +#ifndef _SOC_SIFIVE_FU740_GPIO_H_ +#define _SOC_SIFIVE_FU740_GPIO_H_ + +#include <stdint.h> + +//TODO these are mainboard specific +enum gpio { + J29_1, + PMICINTB, + PMICSHDN, + J8_1, + J8_3, + PCIE_PWREN, // connected to power rails of PCIe connectors + THERM, + UBRDG_RSTN, + PCIE_PERSTN, // connected to PERST pin of PCIe connectors + ULPI_RSTN, + J8_2, + UHUB_RSTN, + GEMGXL_RST, + J8_4, + EN_VDD_SD, + SD_CD, +}; + +// this is to satisfy src/include/gpio.h +typedef enum gpio gpio_t; + +enum gpio_direction { + GPIO_INPUT, + GPIO_OUTPUT, +}; + +void gpio_set_direction(gpio_t gpio, enum gpio_direction gpio_dir); + +#endif // _SOC_SIFIVE_FU740_GPIO_H_ diff --git a/src/soc/sifive/fu740/include/soc/otp.h b/src/soc/sifive/fu740/include/soc/otp.h new file mode 100644 index 0000000..0405fda --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/otp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SIFIVE_FU740_OTP_H__ +#define __SOC_SIFIVE_FU740_OTP_H__ + +#include <stdint.h> + +u32 otp_read_word(u16 idx); +u32 otp_read_serial(void); + +#endif /* __SOC_SIFIVE_FU740_OTP_H__ */ diff --git a/src/soc/sifive/fu740/include/soc/sdram.h b/src/soc/sifive/fu740/include/soc/sdram.h new file mode 100644 index 0000000..50193b6 --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/sdram.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SIFIVE_FU740_SDRAM_H__ +#define __SOC_SIFIVE_FU740_SDRAM_H__ + +#include <types.h> + +void sdram_init(void); +size_t sdram_size(void); + +#endif diff --git a/src/soc/sifive/fu740/include/soc/spi.h b/src/soc/sifive/fu740/include/soc/spi.h new file mode 100644 index 0000000..80e52bb --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/spi.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SIFIVE_FU740_SPI_H__ +#define __SOC_SIFIVE_FU740_SPI_H__ + +#include <spi-generic.h> + +// Frame Format Register Register (fmt) + +#define FU740_SPI_PROTO_S 0 // Data Pins: MOSI MISO +#define FU740_SPI_PROTO_D 1 // Data Pins: DQ0 DQ1 +#define FU740_SPI_PROTO_Q 2 // Data Pins: DQ0 DQ1 DQ2 DQ3 + +#define FU740_SPI_ENDIAN_BIG 0 // send MSB first +#define FU740_SPI_ENDIAN_LITTLE 1 // send LSB first + +// Serial Clock Mode Register (sckmode) + +#define FU740_SPI_PHA_LOW 0 // inactive state of SCK is logical 0 +#define FU740_SPI_PHA_HIGH 1 // inactive state of SCK is logical 1 + +#define FU740_SPI_POL_LEADING 0 // data is sampled on leading edge of sck +#define FU740_SPI_POL_TRAILING 1 // data is sampled on trailing edge of sck + +// ffmt register (SPI Flash Instruction Format Register) +struct fu740_spi_ffmt_config { + unsigned int cmd_en; // enable sending of command + unsigned int addr_len; // number of address bytes (0-4) + unsigned int pad_cnt; // number of dummy cycles + unsigned int cmd_proto; // protocol for transmitting command + unsigned int addr_proto; // protocol for transmitting address and padding + unsigned int data_proto; // protocol for receiving data bytes + unsigned int cmd_code; // value of command byte + unsigned int pad_code; // first 8 bits to transmit during dummy cycles +}; + +struct fu740_spi_fmt_config { + unsigned int protocol; // FU740_SPI_PROTO_S, FU740_SPI_PROTO_D, FU740_SPI_PROTO_Q + unsigned int endianness; // 0 = MSB, 1 = LSB + unsigned int io_dir; // Rx, Tx + unsigned int bits_per_frame; // up to 8bits +}; + +struct fu740_spi_config { + unsigned int freq; // speed of spi interface + unsigned int pha; // serial clock phase + unsigned int pol; // serial clock polarity + struct fu740_spi_fmt_config fmt_config; // frame format config + struct fu740_spi_ffmt_config ffmt_config; // flash instruction format +}; + +extern struct fu740_spi_config fu740_spi_configs[]; + +int fu740_spi_setup(const struct spi_slave *slave); + +#endif /* __SOC_SIFIVE_FU740_SPI_H__ */ diff --git a/src/soc/sifive/fu740/include/soc/ux00ddr.h b/src/soc/sifive/fu740/include/soc/ux00ddr.h new file mode 100644 index 0000000..4393469 --- /dev/null +++ b/src/soc/sifive/fu740/include/soc/ux00ddr.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See the file LICENSE for further information */ +#ifndef _SIFIVE_UX00DDR_H +#define _SIFIVE_UX00DDR_H +#ifndef __ASSEMBLER__ + +//TODO refactor + +#include <stdint.h> +#include <stddef.h> + +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define DRAM_CLASS_OFFSET 8 +#define DRAM_CLASS_DDR4 0xA +#define OPTIMAL_RMODW_EN_OFFSET 0 +#define DISABLE_RD_INTERLEAVE_OFFSET 16 +#define OUT_OF_RANGE_OFFSET 1 +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2 +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 +#define MC_INIT_COMPLETE_OFFSET 8 +#define LEVELING_OPERATION_COMPLETED_OFFSET 22 +#define DFI_PHY_WRLELV_MODE_OFFSET 24 +#define DFI_PHY_RDLVL_MODE_OFFSET 24 +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 +#define VREF_EN_OFFSET 24 +#define PORT_ADDR_PROTECTION_EN_OFFSET 0 +#define AXI0_ADDRESS_RANGE_ENABLE 8 +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24 +#define RDLVL_EN_OFFSET 16 +#define RDLVL_GATE_EN_OFFSET 24 +#define WRLVL_EN_OFFSET 0 +#define PHY_RX_CAL_DQ0_0_OFFSET 0 +#define PHY_RX_CAL_DQ1_0_OFFSET 16 + +static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) +{ + unsigned int i; + for (i=1152;i<=1214;i++) { + uint32_t physet = physettings[i]; + /*if (physet!=0)*/ ddrphyreg[i] = physet; + } + for (i=0;i<=1151;i++) { + uint32_t physet = physettings[i]; + /*if (physet!=0)*/ ddrphyreg[i] = physet; + } +} +static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) { + volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr; + volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t)); + unsigned int i; + for (i=0;i<=264;i++) { + uint32_t ctlset = ctlsettings[i]; + /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset; + } + phy_reset(ddrphyreg, physettings); +} +static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) { + // START register at ddrctl register base offset 0 + uint32_t regdata = _REG32(0<<2, ahbregaddr); + regdata |= 0x1; + _REG32(0<<2, ahbregaddr) = regdata; + // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 + while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {} + // Disable the BusBlocker in front of the controller AXI slave ports + volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr; + filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2); + // ^^ RWX + TOR +} +static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) { + // Mask off Bit 8 of Interrupt Status + // Bit [8] The MC initialization has been completed + _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET); +} +static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { + // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status + // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred + // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred + _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); +} +static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { + // Mask off Bit 7 of Interrupt Status + // Bit [7] An error occurred on the port command channel + _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); +} +static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) { + // Mask off Bit 22 of Interrupt Status + // Bit [22] The leveling operation has completed + _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET); +} +static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) { + _REG32(209<<2, ahbregaddr) = 0x0; + size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1; + _REG32(210<<2, ahbregaddr) = ((uint32_t) end_addr_16Kblocks); + _REG32(212<<2, ahbregaddr) = 0x0; + _REG32(214<<2, ahbregaddr) = 0x0; + _REG32(216<<2, ahbregaddr) = 0x0; + _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); + _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF; + _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE); + _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET); +} +static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) +{ + _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET); +} +static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) +{ + _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET)); +} +static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) +{ + _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET)); +} +static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) +{ + _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET); + _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET); +} +static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) +{ + _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET); + _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET); +} +static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) +{ + _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET); +} +static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) +{ + return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF); +} +static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) +{ + // return bitmask of failed lanes + size_t ddrphyreg = ahbregaddr + 0x2000; + uint64_t fails=0; + uint32_t slicebase = 0; + uint32_t dq = 0; + // check errata condition + for (uint32_t slice = 0; slice < 8; slice++) { + uint32_t regbase = slicebase + 34; + for (uint32_t reg = 0 ; reg < 4; reg++) { + uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg); + for (uint32_t bit = 0; bit < 2; bit++) { + uint32_t phy_rx_cal_dqn_0_offset; + if (bit==0) { + phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET; + } else { + phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET; + } + uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F; + uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F; + uint8_t failc0 = ((down == 0) && (up == 0x3F)); + uint8_t failc1 = ((up == 0) && (down == 0x3F)); + // print error message on failure + if (failc0 || failc1) { + //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); + fails |= (1<<dq); + /* char slicelsc = '0'; */ + /* char slicemsc = '0'; */ + /* slicelsc += (dq % 10); */ + /* slicemsc += (dq / 10); */ + //uart_puts((void*) UART0_CTRL_ADDR, "S "); + //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc); + //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc); + //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U"); + //else uart_puts((void*) UART0_CTRL_ADDR, "D"); + //uart_puts((void*) UART0_CTRL_ADDR, "\n"); + } + dq++; + } + } + slicebase+=128; + } + return (0); +} +#endif +#endif diff --git a/src/soc/sifive/fu740/memlayout.ld b/src/soc/sifive/fu740/memlayout.ld new file mode 100644 index 0000000..5f9394b --- /dev/null +++ b/src/soc/sifive/fu740/memlayout.ld @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <soc/addressmap.h> + +#include <arch/header.ld> + +#define L2LIM_START(addr) REGION_START(l2lim, addr) +#define L2LIM_END(addr) REGION_END(l2lim, addr) + +SECTIONS +{ +#if CONFIG(SEPARATE_ROMSTAGE) + //TODO add code to replace closed source ZSBL + #error "separate romstage is not supported" +#else + L2LIM_START(FU740_L2LIM) + /* The 64K size is not allocated. It's just for basic size checking. */ + BOOTBLOCK(FU740_L2LIM, 64K) +#endif + . = ALIGN(4K); + CAR_STACK(., 12K) // considering each harts stack is a pagesize (4K), we can potentially have up to 16 harts regarding stack space //TODO reduce it, since fu740 doesn't even have/support 16 harts + PRERAM_CBMEM_CONSOLE(., 8K) + CBFS_MCACHE(., 8K) + FMAP_CACHE(., 2K) + PRERAM_CBFS_CACHE(., 128K) + L2LIM_END(FU740_L2LIM + 2M) + + DRAM_START(FU740_DRAM) + OPENSBI(., 256K) + //REGION(opensbi, FU740_DRAM, 256K, 4K) + /* The 256K size is not allocated. It's just for basic size checking. */ + RAMSTAGE(., 256K) + . = ALIGN(4K); + MEM_STACK(., 20K) + POSTRAM_CBFS_CACHE(., 32M - 256K - 256K - 20K) +} diff --git a/src/soc/sifive/fu740/otp.c b/src/soc/sifive/fu740/otp.c new file mode 100644 index 0000000..e00086a --- /dev/null +++ b/src/soc/sifive/fu740/otp.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <device/mmio.h> +#include <console/console.h> +#include <console/uart.h> +#include <soc/addressmap.h> +#include <soc/otp.h> + +/* + * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse + * One-Time-Programmable (OTP) memory used within the SiFive FU740. + * It is documented in the FU740 manual here: + * https://www.sifive.com/documentation/chips/freedom-u740-c000-manual/ + */ + +struct sifive_otp_registers { + u32 pa; /* Address input */ + u32 paio; /* Program address input */ + u32 pas; /* Program redundancy cell selection input */ + u32 pce; /* OTP Macro enable input */ + u32 pclk; /* Clock input */ + u32 pdin; /* Write data input */ + u32 pdout; /* Read data output */ + u32 pdstb; /* Deep standby mode enable input (active low) */ + u32 pprog; /* Program mode enable input */ + u32 ptc; /* Test column enable input */ + u32 ptm; /* Test mode enable input */ + u32 ptm_rep;/* Repair function test mode enable input */ + u32 ptr; /* Test row enable input */ + u32 ptrim; /* Repair function enable input */ + u32 pwe; /* Write enable input (defines program cycle) */ +} __packed; + +/* + * Read a 32 bit value addressed by its index from the OTP. + * The FU740 stores 4096x32 bit (16KiB) values. + * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB) + */ + +u32 otp_read_word(u16 idx) +{ + u32 w; + + if (idx >= 0x1000) + die("otp: idx out of bounds"); + + struct sifive_otp_registers *regs = (void *)(FU740_OTP); + + // wake up from stand-by + write32(&regs->pdstb, 0x01); + + // enable repair function + write32(&regs->ptrim, 0x01); + + // enable input + write32(&regs->pce, 0x01); + + // address to read + write32(&regs->pa, idx); + + // cycle clock to read + write32(&regs->pclk, 0x01); + mdelay(1); + + write32(&regs->pclk, 0x00); + mdelay(1); + + w = read32(&regs->pdout); + + // shut down + write32(&regs->pce, 0x00); + write32(&regs->ptrim, 0x00); + write32(&regs->pdstb, 0x00); + + return w; +} + +u32 otp_read_serial(void) +{ + u32 serial = 0; + u32 serial_n = 0; + for (int i = 0xfe; i > 0; i -= 2) { + serial = otp_read_word(i); + serial_n = otp_read_word(i+1); + if (serial == ~serial_n) + break; + } + return serial; +} diff --git a/src/soc/sifive/fu740/regconfig-ctl.h b/src/soc/sifive/fu740/regconfig-ctl.h new file mode 100644 index 0000000..6e398a5 --- /dev/null +++ b/src/soc/sifive/fu740/regconfig-ctl.h @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Only a very small amount of registers is documented inside the FU740-C000 Manual and the + * rest are basically magic values + * source: u-boot + * (C) Copyright 2020 SiFive, Inc + */ + +#define DENALI_CTL_00_DATA 0x00000a00 +#define DENALI_CTL_01_DATA 0x00000000 +#define DENALI_CTL_02_DATA 0x00000000 +#define DENALI_CTL_03_DATA 0x00000000 +#define DENALI_CTL_04_DATA 0x00000000 +#define DENALI_CTL_05_DATA 0x00000000 +#define DENALI_CTL_06_DATA 0x0000000a +#define DENALI_CTL_07_DATA 0x0002d362 +#define DENALI_CTL_08_DATA 0x00071073 +#define DENALI_CTL_09_DATA 0x0a1c0255 +#define DENALI_CTL_10_DATA 0x1c1c0400 +#define DENALI_CTL_11_DATA 0x0404c90b +#define DENALI_CTL_12_DATA 0x2b050405 +#define DENALI_CTL_13_DATA 0x0d0c081e +#define DENALI_CTL_14_DATA 0x08090914 +#define DENALI_CTL_15_DATA 0x00fde718 +#define DENALI_CTL_16_DATA 0x00180a05 +#define DENALI_CTL_17_DATA 0x008b130d +#define DENALI_CTL_18_DATA 0x01000118 +#define DENALI_CTL_19_DATA 0x0d032001 +#define DENALI_CTL_20_DATA 0x00000000 +#define DENALI_CTL_21_DATA 0x00000101 +#define DENALI_CTL_22_DATA 0x00000000 +#define DENALI_CTL_23_DATA 0x0a000000 +#define DENALI_CTL_24_DATA 0x00000000 +#define DENALI_CTL_25_DATA 0x01450100 +#define DENALI_CTL_26_DATA 0x00001c36 +#define DENALI_CTL_27_DATA 0x00000005 +#define DENALI_CTL_28_DATA 0x00170006 +#define DENALI_CTL_29_DATA 0x014e0400 +#define DENALI_CTL_30_DATA 0x03010000 +#define DENALI_CTL_31_DATA 0x000a0e00 +#define DENALI_CTL_32_DATA 0x04030200 +#define DENALI_CTL_33_DATA 0x0000031f +#define DENALI_CTL_34_DATA 0x00070004 +#define DENALI_CTL_35_DATA 0x00000000 +#define DENALI_CTL_36_DATA 0x00000000 +#define DENALI_CTL_37_DATA 0x00000000 +#define DENALI_CTL_38_DATA 0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 +#define DENALI_CTL_40_DATA 0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 +#define DENALI_CTL_43_DATA 0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 +#define DENALI_CTL_45_DATA 0x00000000 +#define DENALI_CTL_46_DATA 0x00000000 +#define DENALI_CTL_47_DATA 0x00000000 +#define DENALI_CTL_48_DATA 0x00000000 +#define DENALI_CTL_49_DATA 0x00000000 +#define DENALI_CTL_50_DATA 0x00000000 +#define DENALI_CTL_51_DATA 0x00000000 +#define DENALI_CTL_52_DATA 0x00000000 +#define DENALI_CTL_53_DATA 0x00000000 +#define DENALI_CTL_54_DATA 0x00000000 +#define DENALI_CTL_55_DATA 0x00000000 +#define DENALI_CTL_56_DATA 0x00000000 +#define DENALI_CTL_57_DATA 0x00000000 +#define DENALI_CTL_58_DATA 0x00000000 +#define DENALI_CTL_59_DATA 0x00000000 +#define DENALI_CTL_60_DATA 0x00000424 +#define DENALI_CTL_61_DATA 0x00000201 +#define DENALI_CTL_62_DATA 0x00001008 +#define DENALI_CTL_63_DATA 0x00000000 +#define DENALI_CTL_64_DATA 0x00000200 +#define DENALI_CTL_65_DATA 0x00000800 +#define DENALI_CTL_66_DATA 0x00000481 +#define DENALI_CTL_67_DATA 0x00000400 +#define DENALI_CTL_68_DATA 0x00000424 +#define DENALI_CTL_69_DATA 0x00000201 +#define DENALI_CTL_70_DATA 0x00001008 +#define DENALI_CTL_71_DATA 0x00000000 +#define DENALI_CTL_72_DATA 0x00000200 +#define DENALI_CTL_73_DATA 0x00000800 +#define DENALI_CTL_74_DATA 0x00000481 +#define DENALI_CTL_75_DATA 0x00000400 +#define DENALI_CTL_76_DATA 0x01010000 +#define DENALI_CTL_77_DATA 0x00000000 +#define DENALI_CTL_78_DATA 0x00000000 +#define DENALI_CTL_79_DATA 0x00000000 +#define DENALI_CTL_80_DATA 0x00000000 +#define DENALI_CTL_81_DATA 0x00000000 +#define DENALI_CTL_82_DATA 0x00000000 +#define DENALI_CTL_83_DATA 0x00000000 +#define DENALI_CTL_84_DATA 0x00000000 +#define DENALI_CTL_85_DATA 0x00000000 +#define DENALI_CTL_86_DATA 0x00000000 +#define DENALI_CTL_87_DATA 0x00000000 +#define DENALI_CTL_88_DATA 0x00000000 +#define DENALI_CTL_89_DATA 0x00000000 +#define DENALI_CTL_90_DATA 0x00000000 +#define DENALI_CTL_91_DATA 0x00000000 +#define DENALI_CTL_92_DATA 0x00000000 +#define DENALI_CTL_93_DATA 0x00000000 +#define DENALI_CTL_94_DATA 0x00000000 +#define DENALI_CTL_95_DATA 0x00000000 +#define DENALI_CTL_96_DATA 0x00000000 +#define DENALI_CTL_97_DATA 0x00000000 +#define DENALI_CTL_98_DATA 0x00000000 +#define DENALI_CTL_99_DATA 0x00000000 +#define DENALI_CTL_100_DATA 0x00000000 +#define DENALI_CTL_101_DATA 0x00000000 +#define DENALI_CTL_102_DATA 0x00000000 +#define DENALI_CTL_103_DATA 0x00000000 +#define DENALI_CTL_104_DATA 0x00000000 +#define DENALI_CTL_105_DATA 0x00000003 +#define DENALI_CTL_106_DATA 0x00000000 +#define DENALI_CTL_107_DATA 0x00000000 +#define DENALI_CTL_108_DATA 0x00000000 +#define DENALI_CTL_109_DATA 0x00000000 +#define DENALI_CTL_110_DATA 0x01000000 +#define DENALI_CTL_111_DATA 0x00040000 +#define DENALI_CTL_112_DATA 0x00800200 +#define DENALI_CTL_113_DATA 0x00000200 +#define DENALI_CTL_114_DATA 0x00000040 +#define DENALI_CTL_115_DATA 0x01000100 +#define DENALI_CTL_116_DATA 0x0a000002 +#define DENALI_CTL_117_DATA 0x0101ffff +#define DENALI_CTL_118_DATA 0x01010101 +#define DENALI_CTL_119_DATA 0x01010101 +#define DENALI_CTL_120_DATA 0x0000010b +#define DENALI_CTL_121_DATA 0x00000c03 +#define DENALI_CTL_122_DATA 0x00000000 +#define DENALI_CTL_123_DATA 0x00000000 +#define DENALI_CTL_124_DATA 0x00000000 +#define DENALI_CTL_125_DATA 0x00000000 +#define DENALI_CTL_126_DATA 0x00030300 +#define DENALI_CTL_127_DATA 0x00000000 +#define DENALI_CTL_128_DATA 0x00010101 +#define DENALI_CTL_129_DATA 0x00000000 +#define DENALI_CTL_130_DATA 0x00000000 +#define DENALI_CTL_131_DATA 0x00000000 +#define DENALI_CTL_132_DATA 0x00000000 +#define DENALI_CTL_133_DATA 0x00000000 +#define DENALI_CTL_134_DATA 0x00000000 +#define DENALI_CTL_135_DATA 0x00000000 +#define DENALI_CTL_136_DATA 0x00000000 +#define DENALI_CTL_137_DATA 0x00000000 +#define DENALI_CTL_138_DATA 0x00000000 +#define DENALI_CTL_139_DATA 0x00000000 +#define DENALI_CTL_140_DATA 0x00000000 +#define DENALI_CTL_141_DATA 0x00000000 +#define DENALI_CTL_142_DATA 0x00000000 +#define DENALI_CTL_143_DATA 0x00000000 +#define DENALI_CTL_144_DATA 0x00000000 +#define DENALI_CTL_145_DATA 0x00000000 +#define DENALI_CTL_146_DATA 0x00000000 +#define DENALI_CTL_147_DATA 0x00000000 +#define DENALI_CTL_148_DATA 0x00000000 +#define DENALI_CTL_149_DATA 0x00000000 +#define DENALI_CTL_150_DATA 0x00000000 +#define DENALI_CTL_151_DATA 0x00000000 +#define DENALI_CTL_152_DATA 0x00000000 +#define DENALI_CTL_153_DATA 0x00000000 +#define DENALI_CTL_154_DATA 0x00000000 +#define DENALI_CTL_155_DATA 0x00000000 +#define DENALI_CTL_156_DATA 0x00000000 +#define DENALI_CTL_157_DATA 0x00000000 +#define DENALI_CTL_158_DATA 0x00000000 +#define DENALI_CTL_159_DATA 0x00000000 +#define DENALI_CTL_160_DATA 0x00000000 +#define DENALI_CTL_161_DATA 0x02010102 +#define DENALI_CTL_162_DATA 0x0108070d +#define DENALI_CTL_163_DATA 0x05050300 +#define DENALI_CTL_164_DATA 0x04000503 +#define DENALI_CTL_165_DATA 0x00000000 +#define DENALI_CTL_166_DATA 0x00000000 +#define DENALI_CTL_167_DATA 0x00000000 +#define DENALI_CTL_168_DATA 0x00000000 +#define DENALI_CTL_169_DATA 0x280d0000 +#define DENALI_CTL_170_DATA 0x01000000 +#define DENALI_CTL_171_DATA 0x00000000 +#define DENALI_CTL_172_DATA 0x00030001 +#define DENALI_CTL_173_DATA 0x00000000 +#define DENALI_CTL_174_DATA 0x00000000 +#define DENALI_CTL_175_DATA 0x00000000 +#define DENALI_CTL_176_DATA 0x00000000 +#define DENALI_CTL_177_DATA 0x00000000 +#define DENALI_CTL_178_DATA 0x00000000 +#define DENALI_CTL_179_DATA 0x00000000 +#define DENALI_CTL_180_DATA 0x00000000 +#define DENALI_CTL_181_DATA 0x01000000 +#define DENALI_CTL_182_DATA 0x00000001 +#define DENALI_CTL_183_DATA 0x00000100 +#define DENALI_CTL_184_DATA 0x00010303 +#define DENALI_CTL_185_DATA 0x67676701 +#define DENALI_CTL_186_DATA 0x67676767 +#define DENALI_CTL_187_DATA 0x67676767 +#define DENALI_CTL_188_DATA 0x67676767 +#define DENALI_CTL_189_DATA 0x67676767 +#define DENALI_CTL_190_DATA 0x67676767 +#define DENALI_CTL_191_DATA 0x67676767 +#define DENALI_CTL_192_DATA 0x67676767 +#define DENALI_CTL_193_DATA 0x67676767 +#define DENALI_CTL_194_DATA 0x01000067 +#define DENALI_CTL_195_DATA 0x00000001 +#define DENALI_CTL_196_DATA 0x00000101 +#define DENALI_CTL_197_DATA 0x00000000 +#define DENALI_CTL_198_DATA 0x00000000 +#define DENALI_CTL_199_DATA 0x00000000 +#define DENALI_CTL_200_DATA 0x00000000 +#define DENALI_CTL_201_DATA 0x00000000 +#define DENALI_CTL_202_DATA 0x00000000 +#define DENALI_CTL_203_DATA 0x00000000 +#define DENALI_CTL_204_DATA 0x00000000 +#define DENALI_CTL_205_DATA 0x00000000 +#define DENALI_CTL_206_DATA 0x00000000 +#define DENALI_CTL_207_DATA 0x00000000 +#define DENALI_CTL_208_DATA 0x00000001 +#define DENALI_CTL_209_DATA 0x00000000 +#define DENALI_CTL_210_DATA 0x007fffff +#define DENALI_CTL_211_DATA 0x00000000 +#define DENALI_CTL_212_DATA 0x007fffff +#define DENALI_CTL_213_DATA 0x00000000 +#define DENALI_CTL_214_DATA 0x007fffff +#define DENALI_CTL_215_DATA 0x00000000 +#define DENALI_CTL_216_DATA 0x007fffff +#define DENALI_CTL_217_DATA 0x00000000 +#define DENALI_CTL_218_DATA 0x007fffff +#define DENALI_CTL_219_DATA 0x00000000 +#define DENALI_CTL_220_DATA 0x007fffff +#define DENALI_CTL_221_DATA 0x00000000 +#define DENALI_CTL_222_DATA 0x007fffff +#define DENALI_CTL_223_DATA 0x00000000 +#define DENALI_CTL_224_DATA 0x037fffff +#define DENALI_CTL_225_DATA 0xffffffff +#define DENALI_CTL_226_DATA 0x000f000f +#define DENALI_CTL_227_DATA 0x00ffff03 +#define DENALI_CTL_228_DATA 0x000fffff +#define DENALI_CTL_229_DATA 0x0003000f +#define DENALI_CTL_230_DATA 0xffffffff +#define DENALI_CTL_231_DATA 0x000f000f +#define DENALI_CTL_232_DATA 0x00ffff03 +#define DENALI_CTL_233_DATA 0x000fffff +#define DENALI_CTL_234_DATA 0x0003000f +#define DENALI_CTL_235_DATA 0xffffffff +#define DENALI_CTL_236_DATA 0x000f000f +#define DENALI_CTL_237_DATA 0x00ffff03 +#define DENALI_CTL_238_DATA 0x000fffff +#define DENALI_CTL_239_DATA 0x0003000f +#define DENALI_CTL_240_DATA 0xffffffff +#define DENALI_CTL_241_DATA 0x000f000f +#define DENALI_CTL_242_DATA 0x00ffff03 +#define DENALI_CTL_243_DATA 0x000fffff +#define DENALI_CTL_244_DATA 0x6407000f +#define DENALI_CTL_245_DATA 0x01640001 +#define DENALI_CTL_246_DATA 0x00000000 +#define DENALI_CTL_247_DATA 0x00000000 +#define DENALI_CTL_248_DATA 0x00001800 +#define DENALI_CTL_249_DATA 0x00386c05 +#define DENALI_CTL_250_DATA 0x02000200 +#define DENALI_CTL_251_DATA 0x02000200 +#define DENALI_CTL_252_DATA 0x0000386c +#define DENALI_CTL_253_DATA 0x00023438 +#define DENALI_CTL_254_DATA 0x02020d0f +#define DENALI_CTL_255_DATA 0x00140303 +#define DENALI_CTL_256_DATA 0x00000000 +#define DENALI_CTL_257_DATA 0x00000000 +#define DENALI_CTL_258_DATA 0x00001403 +#define DENALI_CTL_259_DATA 0x00000000 +#define DENALI_CTL_260_DATA 0x00000000 +#define DENALI_CTL_261_DATA 0x00000000 +#define DENALI_CTL_262_DATA 0x00000000 +#define DENALI_CTL_263_DATA 0x0c010000 +#define DENALI_CTL_264_DATA 0x00000008 diff --git a/src/soc/sifive/fu740/regconfig-phy.h b/src/soc/sifive/fu740/regconfig-phy.h new file mode 100644 index 0000000..a173aec --- /dev/null +++ b/src/soc/sifive/fu740/regconfig-phy.h @@ -0,0 +1,1224 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Only a very small amount of registers is documented inside the FU740-C000 Manual and the + * rest are basically magic values + * source: u-boot + * (C) Copyright 2020 SiFive, Inc + */ + +#define DENALI_PHY_00_DATA 0x01375642 +#define DENALI_PHY_01_DATA 0x0004c008 +#define DENALI_PHY_02_DATA 0x000000da +#define DENALI_PHY_03_DATA 0x00000000 +#define DENALI_PHY_04_DATA 0x00000000 +#define DENALI_PHY_05_DATA 0x00010000 +#define DENALI_PHY_06_DATA 0x01DDDD90 +#define DENALI_PHY_07_DATA 0x01DDDD90 +#define DENALI_PHY_08_DATA 0x01030001 +#define DENALI_PHY_09_DATA 0x01000000 +#define DENALI_PHY_10_DATA 0x00c00000 +#define DENALI_PHY_11_DATA 0x00000007 +#define DENALI_PHY_12_DATA 0x00000000 +#define DENALI_PHY_13_DATA 0x00000000 +#define DENALI_PHY_14_DATA 0x04000408 +#define DENALI_PHY_15_DATA 0x00000408 +#define DENALI_PHY_16_DATA 0x00e4e400 +#define DENALI_PHY_17_DATA 0x00000000 +#define DENALI_PHY_18_DATA 0x00000000 +#define DENALI_PHY_19_DATA 0x00000000 +#define DENALI_PHY_20_DATA 0x00000000 +#define DENALI_PHY_21_DATA 0x00000000 +#define DENALI_PHY_22_DATA 0x00000000 +#define DENALI_PHY_23_DATA 0x00000000 +#define DENALI_PHY_24_DATA 0x00000000 +#define DENALI_PHY_25_DATA 0x00000000 +#define DENALI_PHY_26_DATA 0x00000000 +#define DENALI_PHY_27_DATA 0x00000000 +#define DENALI_PHY_28_DATA 0x00000000 +#define DENALI_PHY_29_DATA 0x00000000 +#define DENALI_PHY_30_DATA 0x00000000 +#define DENALI_PHY_31_DATA 0x00000000 +#define DENALI_PHY_32_DATA 0x00000000 +#define DENALI_PHY_33_DATA 0x00200000 +#define DENALI_PHY_34_DATA 0x00000000 +#define DENALI_PHY_35_DATA 0x00000000 +#define DENALI_PHY_36_DATA 0x00000000 +#define DENALI_PHY_37_DATA 0x00000000 +#define DENALI_PHY_38_DATA 0x00000000 +#define DENALI_PHY_39_DATA 0x00000000 +#define DENALI_PHY_40_DATA 0x02800280 +#define DENALI_PHY_41_DATA 0x02800280 +#define DENALI_PHY_42_DATA 0x02800280 +#define DENALI_PHY_43_DATA 0x02800280 +#define DENALI_PHY_44_DATA 0x00000280 +#define DENALI_PHY_45_DATA 0x00000000 +#define DENALI_PHY_46_DATA 0x00000000 +#define DENALI_PHY_47_DATA 0x00000000 +#define DENALI_PHY_48_DATA 0x00000000 +#define DENALI_PHY_49_DATA 0x00000000 +#define DENALI_PHY_50_DATA 0x00800080 +#define DENALI_PHY_51_DATA 0x00800080 +#define DENALI_PHY_52_DATA 0x00800080 +#define DENALI_PHY_53_DATA 0x00800080 +#define DENALI_PHY_54_DATA 0x00800080 +#define DENALI_PHY_55_DATA 0x00800080 +#define DENALI_PHY_56_DATA 0x00800080 +#define DENALI_PHY_57_DATA 0x00800080 +#define DENALI_PHY_58_DATA 0x00800080 +#define DENALI_PHY_59_DATA 0x000100da +#define DENALI_PHY_60_DATA 0x01ff0010 +#define DENALI_PHY_61_DATA 0x00000000 +#define DENALI_PHY_62_DATA 0x00000000 +#define DENALI_PHY_63_DATA 0x00000002 +#define DENALI_PHY_64_DATA 0x51313152 +#define DENALI_PHY_65_DATA 0x80013130 +#define DENALI_PHY_66_DATA 0x02000080 +#define DENALI_PHY_67_DATA 0x00100001 +#define DENALI_PHY_68_DATA 0x0c064208 +#define DENALI_PHY_69_DATA 0x000f0c0f +#define DENALI_PHY_70_DATA 0x01000140 +#define DENALI_PHY_71_DATA 0x0000000c +#define DENALI_PHY_72_DATA 0x00000000 +#define DENALI_PHY_73_DATA 0x00000000 +#define DENALI_PHY_74_DATA 0x00000000 +#define DENALI_PHY_75_DATA 0x00000000 +#define DENALI_PHY_76_DATA 0x00000000 +#define DENALI_PHY_77_DATA 0x00000000 +#define DENALI_PHY_78_DATA 0x00000000 +#define DENALI_PHY_79_DATA 0x00000000 +#define DENALI_PHY_80_DATA 0x00000000 +#define DENALI_PHY_81_DATA 0x00000000 +#define DENALI_PHY_82_DATA 0x00000000 +#define DENALI_PHY_83_DATA 0x00000000 +#define DENALI_PHY_84_DATA 0x00000000 +#define DENALI_PHY_85_DATA 0x00000000 +#define DENALI_PHY_86_DATA 0x00000000 +#define DENALI_PHY_87_DATA 0x00000000 +#define DENALI_PHY_88_DATA 0x00000000 +#define DENALI_PHY_89_DATA 0x00000000 +#define DENALI_PHY_90_DATA 0x00000000 +#define DENALI_PHY_91_DATA 0x00000000 +#define DENALI_PHY_92_DATA 0x00000000 +#define DENALI_PHY_93_DATA 0x00000000 +#define DENALI_PHY_94_DATA 0x00000000 +#define DENALI_PHY_95_DATA 0x00000000 +#define DENALI_PHY_96_DATA 0x00000000 +#define DENALI_PHY_97_DATA 0x00000000 +#define DENALI_PHY_98_DATA 0x00000000 +#define DENALI_PHY_99_DATA 0x00000000 +#define DENALI_PHY_100_DATA 0x00000000 +#define DENALI_PHY_101_DATA 0x00000000 +#define DENALI_PHY_102_DATA 0x00000000 +#define DENALI_PHY_103_DATA 0x00000000 +#define DENALI_PHY_104_DATA 0x00000000 +#define DENALI_PHY_105_DATA 0x00000000 +#define DENALI_PHY_106_DATA 0x00000000 +#define DENALI_PHY_107_DATA 0x00000000 +#define DENALI_PHY_108_DATA 0x00000000 +#define DENALI_PHY_109_DATA 0x00000000 +#define DENALI_PHY_110_DATA 0x00000000 +#define DENALI_PHY_111_DATA 0x00000000 +#define DENALI_PHY_112_DATA 0x00000000 +#define DENALI_PHY_113_DATA 0x00000000 +#define DENALI_PHY_114_DATA 0x00000000 +#define DENALI_PHY_115_DATA 0x00000000 +#define DENALI_PHY_116_DATA 0x00000000 +#define DENALI_PHY_117_DATA 0x00000000 +#define DENALI_PHY_118_DATA 0x00000000 +#define DENALI_PHY_119_DATA 0x00000000 +#define DENALI_PHY_120_DATA 0x00000000 +#define DENALI_PHY_121_DATA 0x00000000 +#define DENALI_PHY_122_DATA 0x00000000 +#define DENALI_PHY_123_DATA 0x00000000 +#define DENALI_PHY_124_DATA 0x00000000 +#define DENALI_PHY_125_DATA 0x00000000 +#define DENALI_PHY_126_DATA 0x00000000 +#define DENALI_PHY_127_DATA 0x00000000 +#define DENALI_PHY_128_DATA 0x40263571 +#define DENALI_PHY_129_DATA 0x0004c008 +#define DENALI_PHY_130_DATA 0x000000da +#define DENALI_PHY_131_DATA 0x00000000 +#define DENALI_PHY_132_DATA 0x00000000 +#define DENALI_PHY_133_DATA 0x00010000 +#define DENALI_PHY_134_DATA 0x01DDDD90 +#define DENALI_PHY_135_DATA 0x01DDDD90 +#define DENALI_PHY_136_DATA 0x01030001 +#define DENALI_PHY_137_DATA 0x01000000 +#define DENALI_PHY_138_DATA 0x00c00000 +#define DENALI_PHY_139_DATA 0x00000007 +#define DENALI_PHY_140_DATA 0x00000000 +#define DENALI_PHY_141_DATA 0x00000000 +#define DENALI_PHY_142_DATA 0x04000408 +#define DENALI_PHY_143_DATA 0x00000408 +#define DENALI_PHY_144_DATA 0x00e4e400 +#define DENALI_PHY_145_DATA 0x00000000 +#define DENALI_PHY_146_DATA 0x00000000 +#define DENALI_PHY_147_DATA 0x00000000 +#define DENALI_PHY_148_DATA 0x00000000 +#define DENALI_PHY_149_DATA 0x00000000 +#define DENALI_PHY_150_DATA 0x00000000 +#define DENALI_PHY_151_DATA 0x00000000 +#define DENALI_PHY_152_DATA 0x00000000 +#define DENALI_PHY_153_DATA 0x00000000 +#define DENALI_PHY_154_DATA 0x00000000 +#define DENALI_PHY_155_DATA 0x00000000 +#define DENALI_PHY_156_DATA 0x00000000 +#define DENALI_PHY_157_DATA 0x00000000 +#define DENALI_PHY_158_DATA 0x00000000 +#define DENALI_PHY_159_DATA 0x00000000 +#define DENALI_PHY_160_DATA 0x00000000 +#define DENALI_PHY_161_DATA 0x00200000 +#define DENALI_PHY_162_DATA 0x00000000 +#define DENALI_PHY_163_DATA 0x00000000 +#define DENALI_PHY_164_DATA 0x00000000 +#define DENALI_PHY_165_DATA 0x00000000 +#define DENALI_PHY_166_DATA 0x00000000 +#define DENALI_PHY_167_DATA 0x00000000 +#define DENALI_PHY_168_DATA 0x02800280 +#define DENALI_PHY_169_DATA 0x02800280 +#define DENALI_PHY_170_DATA 0x02800280 +#define DENALI_PHY_171_DATA 0x02800280 +#define DENALI_PHY_172_DATA 0x00000280 +#define DENALI_PHY_173_DATA 0x00000000 +#define DENALI_PHY_174_DATA 0x00000000 +#define DENALI_PHY_175_DATA 0x00000000 +#define DENALI_PHY_176_DATA 0x00000000 +#define DENALI_PHY_177_DATA 0x00000000 +#define DENALI_PHY_178_DATA 0x00800080 +#define DENALI_PHY_179_DATA 0x00800080 +#define DENALI_PHY_180_DATA 0x00800080 +#define DENALI_PHY_181_DATA 0x00800080 +#define DENALI_PHY_182_DATA 0x00800080 +#define DENALI_PHY_183_DATA 0x00800080 +#define DENALI_PHY_184_DATA 0x00800080 +#define DENALI_PHY_185_DATA 0x00800080 +#define DENALI_PHY_186_DATA 0x00800080 +#define DENALI_PHY_187_DATA 0x000100da +#define DENALI_PHY_188_DATA 0x01ff0010 +#define DENALI_PHY_189_DATA 0x00000000 +#define DENALI_PHY_190_DATA 0x00000000 +#define DENALI_PHY_191_DATA 0x00000002 +#define DENALI_PHY_192_DATA 0x51313152 +#define DENALI_PHY_193_DATA 0x80013130 +#define DENALI_PHY_194_DATA 0x02000080 +#define DENALI_PHY_195_DATA 0x00100001 +#define DENALI_PHY_196_DATA 0x0c064208 +#define DENALI_PHY_197_DATA 0x000f0c0f +#define DENALI_PHY_198_DATA 0x01000140 +#define DENALI_PHY_199_DATA 0x0000000c +#define DENALI_PHY_200_DATA 0x00000000 +#define DENALI_PHY_201_DATA 0x00000000 +#define DENALI_PHY_202_DATA 0x00000000 +#define DENALI_PHY_203_DATA 0x00000000 +#define DENALI_PHY_204_DATA 0x00000000 +#define DENALI_PHY_205_DATA 0x00000000 +#define DENALI_PHY_206_DATA 0x00000000 +#define DENALI_PHY_207_DATA 0x00000000 +#define DENALI_PHY_208_DATA 0x00000000 +#define DENALI_PHY_209_DATA 0x00000000 +#define DENALI_PHY_210_DATA 0x00000000 +#define DENALI_PHY_211_DATA 0x00000000 +#define DENALI_PHY_212_DATA 0x00000000 +#define DENALI_PHY_213_DATA 0x00000000 +#define DENALI_PHY_214_DATA 0x00000000 +#define DENALI_PHY_215_DATA 0x00000000 +#define DENALI_PHY_216_DATA 0x00000000 +#define DENALI_PHY_217_DATA 0x00000000 +#define DENALI_PHY_218_DATA 0x00000000 +#define DENALI_PHY_219_DATA 0x00000000 +#define DENALI_PHY_220_DATA 0x00000000 +#define DENALI_PHY_221_DATA 0x00000000 +#define DENALI_PHY_222_DATA 0x00000000 +#define DENALI_PHY_223_DATA 0x00000000 +#define DENALI_PHY_224_DATA 0x00000000 +#define DENALI_PHY_225_DATA 0x00000000 +#define DENALI_PHY_226_DATA 0x00000000 +#define DENALI_PHY_227_DATA 0x00000000 +#define DENALI_PHY_228_DATA 0x00000000 +#define DENALI_PHY_229_DATA 0x00000000 +#define DENALI_PHY_230_DATA 0x00000000 +#define DENALI_PHY_231_DATA 0x00000000 +#define DENALI_PHY_232_DATA 0x00000000 +#define DENALI_PHY_233_DATA 0x00000000 +#define DENALI_PHY_234_DATA 0x00000000 +#define DENALI_PHY_235_DATA 0x00000000 +#define DENALI_PHY_236_DATA 0x00000000 +#define DENALI_PHY_237_DATA 0x00000000 +#define DENALI_PHY_238_DATA 0x00000000 +#define DENALI_PHY_239_DATA 0x00000000 +#define DENALI_PHY_240_DATA 0x00000000 +#define DENALI_PHY_241_DATA 0x00000000 +#define DENALI_PHY_242_DATA 0x00000000 +#define DENALI_PHY_243_DATA 0x00000000 +#define DENALI_PHY_244_DATA 0x00000000 +#define DENALI_PHY_245_DATA 0x00000000 +#define DENALI_PHY_246_DATA 0x00000000 +#define DENALI_PHY_247_DATA 0x00000000 +#define DENALI_PHY_248_DATA 0x00000000 +#define DENALI_PHY_249_DATA 0x00000000 +#define DENALI_PHY_250_DATA 0x00000000 +#define DENALI_PHY_251_DATA 0x00000000 +#define DENALI_PHY_252_DATA 0x00000000 +#define DENALI_PHY_253_DATA 0x00000000 +#define DENALI_PHY_254_DATA 0x00000000 +#define DENALI_PHY_255_DATA 0x00000000 +#define DENALI_PHY_256_DATA 0x46052371 +#define DENALI_PHY_257_DATA 0x0004c008 +#define DENALI_PHY_258_DATA 0x000000da +#define DENALI_PHY_259_DATA 0x00000000 +#define DENALI_PHY_260_DATA 0x00000000 +#define DENALI_PHY_261_DATA 0x00010000 +#define DENALI_PHY_262_DATA 0x01DDDD90 +#define DENALI_PHY_263_DATA 0x01DDDD90 +#define DENALI_PHY_264_DATA 0x01030001 +#define DENALI_PHY_265_DATA 0x01000000 +#define DENALI_PHY_266_DATA 0x00c00000 +#define DENALI_PHY_267_DATA 0x00000007 +#define DENALI_PHY_268_DATA 0x00000000 +#define DENALI_PHY_269_DATA 0x00000000 +#define DENALI_PHY_270_DATA 0x04000408 +#define DENALI_PHY_271_DATA 0x00000408 +#define DENALI_PHY_272_DATA 0x00e4e400 +#define DENALI_PHY_273_DATA 0x00000000 +#define DENALI_PHY_274_DATA 0x00000000 +#define DENALI_PHY_275_DATA 0x00000000 +#define DENALI_PHY_276_DATA 0x00000000 +#define DENALI_PHY_277_DATA 0x00000000 +#define DENALI_PHY_278_DATA 0x00000000 +#define DENALI_PHY_279_DATA 0x00000000 +#define DENALI_PHY_280_DATA 0x00000000 +#define DENALI_PHY_281_DATA 0x00000000 +#define DENALI_PHY_282_DATA 0x00000000 +#define DENALI_PHY_283_DATA 0x00000000 +#define DENALI_PHY_284_DATA 0x00000000 +#define DENALI_PHY_285_DATA 0x00000000 +#define DENALI_PHY_286_DATA 0x00000000 +#define DENALI_PHY_287_DATA 0x00000000 +#define DENALI_PHY_288_DATA 0x00000000 +#define DENALI_PHY_289_DATA 0x00200000 +#define DENALI_PHY_290_DATA 0x00000000 +#define DENALI_PHY_291_DATA 0x00000000 +#define DENALI_PHY_292_DATA 0x00000000 +#define DENALI_PHY_293_DATA 0x00000000 +#define DENALI_PHY_294_DATA 0x00000000 +#define DENALI_PHY_295_DATA 0x00000000 +#define DENALI_PHY_296_DATA 0x02800280 +#define DENALI_PHY_297_DATA 0x02800280 +#define DENALI_PHY_298_DATA 0x02800280 +#define DENALI_PHY_299_DATA 0x02800280 +#define DENALI_PHY_300_DATA 0x00000280 +#define DENALI_PHY_301_DATA 0x00000000 +#define DENALI_PHY_302_DATA 0x00000000 +#define DENALI_PHY_303_DATA 0x00000000 +#define DENALI_PHY_304_DATA 0x00000000 +#define DENALI_PHY_305_DATA 0x00000000 +#define DENALI_PHY_306_DATA 0x00800080 +#define DENALI_PHY_307_DATA 0x00800080 +#define DENALI_PHY_308_DATA 0x00800080 +#define DENALI_PHY_309_DATA 0x00800080 +#define DENALI_PHY_310_DATA 0x00800080 +#define DENALI_PHY_311_DATA 0x00800080 +#define DENALI_PHY_312_DATA 0x00800080 +#define DENALI_PHY_313_DATA 0x00800080 +#define DENALI_PHY_314_DATA 0x00800080 +#define DENALI_PHY_315_DATA 0x000100da +#define DENALI_PHY_316_DATA 0x01ff0010 +#define DENALI_PHY_317_DATA 0x00000000 +#define DENALI_PHY_318_DATA 0x00000000 +#define DENALI_PHY_319_DATA 0x00000002 +#define DENALI_PHY_320_DATA 0x51313152 +#define DENALI_PHY_321_DATA 0x80013130 +#define DENALI_PHY_322_DATA 0x02000080 +#define DENALI_PHY_323_DATA 0x00100001 +#define DENALI_PHY_324_DATA 0x0c064208 +#define DENALI_PHY_325_DATA 0x000f0c0f +#define DENALI_PHY_326_DATA 0x01000140 +#define DENALI_PHY_327_DATA 0x0000000c +#define DENALI_PHY_328_DATA 0x00000000 +#define DENALI_PHY_329_DATA 0x00000000 +#define DENALI_PHY_330_DATA 0x00000000 +#define DENALI_PHY_331_DATA 0x00000000 +#define DENALI_PHY_332_DATA 0x00000000 +#define DENALI_PHY_333_DATA 0x00000000 +#define DENALI_PHY_334_DATA 0x00000000 +#define DENALI_PHY_335_DATA 0x00000000 +#define DENALI_PHY_336_DATA 0x00000000 +#define DENALI_PHY_337_DATA 0x00000000 +#define DENALI_PHY_338_DATA 0x00000000 +#define DENALI_PHY_339_DATA 0x00000000 +#define DENALI_PHY_340_DATA 0x00000000 +#define DENALI_PHY_341_DATA 0x00000000 +#define DENALI_PHY_342_DATA 0x00000000 +#define DENALI_PHY_343_DATA 0x00000000 +#define DENALI_PHY_344_DATA 0x00000000 +#define DENALI_PHY_345_DATA 0x00000000 +#define DENALI_PHY_346_DATA 0x00000000 +#define DENALI_PHY_347_DATA 0x00000000 +#define DENALI_PHY_348_DATA 0x00000000 +#define DENALI_PHY_349_DATA 0x00000000 +#define DENALI_PHY_350_DATA 0x00000000 +#define DENALI_PHY_351_DATA 0x00000000 +#define DENALI_PHY_352_DATA 0x00000000 +#define DENALI_PHY_353_DATA 0x00000000 +#define DENALI_PHY_354_DATA 0x00000000 +#define DENALI_PHY_355_DATA 0x00000000 +#define DENALI_PHY_356_DATA 0x00000000 +#define DENALI_PHY_357_DATA 0x00000000 +#define DENALI_PHY_358_DATA 0x00000000 +#define DENALI_PHY_359_DATA 0x00000000 +#define DENALI_PHY_360_DATA 0x00000000 +#define DENALI_PHY_361_DATA 0x00000000 +#define DENALI_PHY_362_DATA 0x00000000 +#define DENALI_PHY_363_DATA 0x00000000 +#define DENALI_PHY_364_DATA 0x00000000 +#define DENALI_PHY_365_DATA 0x00000000 +#define DENALI_PHY_366_DATA 0x00000000 +#define DENALI_PHY_367_DATA 0x00000000 +#define DENALI_PHY_368_DATA 0x00000000 +#define DENALI_PHY_369_DATA 0x00000000 +#define DENALI_PHY_370_DATA 0x00000000 +#define DENALI_PHY_371_DATA 0x00000000 +#define DENALI_PHY_372_DATA 0x00000000 +#define DENALI_PHY_373_DATA 0x00000000 +#define DENALI_PHY_374_DATA 0x00000000 +#define DENALI_PHY_375_DATA 0x00000000 +#define DENALI_PHY_376_DATA 0x00000000 +#define DENALI_PHY_377_DATA 0x00000000 +#define DENALI_PHY_378_DATA 0x00000000 +#define DENALI_PHY_379_DATA 0x00000000 +#define DENALI_PHY_380_DATA 0x00000000 +#define DENALI_PHY_381_DATA 0x00000000 +#define DENALI_PHY_382_DATA 0x00000000 +#define DENALI_PHY_383_DATA 0x00000000 +#define DENALI_PHY_384_DATA 0x37651240 +#define DENALI_PHY_385_DATA 0x0004c008 +#define DENALI_PHY_386_DATA 0x000000da +#define DENALI_PHY_387_DATA 0x00000000 +#define DENALI_PHY_388_DATA 0x00000000 +#define DENALI_PHY_389_DATA 0x00010000 +#define DENALI_PHY_390_DATA 0x01DDDD90 +#define DENALI_PHY_391_DATA 0x01DDDD90 +#define DENALI_PHY_392_DATA 0x01030001 +#define DENALI_PHY_393_DATA 0x01000000 +#define DENALI_PHY_394_DATA 0x00c00000 +#define DENALI_PHY_395_DATA 0x00000007 +#define DENALI_PHY_396_DATA 0x00000000 +#define DENALI_PHY_397_DATA 0x00000000 +#define DENALI_PHY_398_DATA 0x04000408 +#define DENALI_PHY_399_DATA 0x00000408 +#define DENALI_PHY_400_DATA 0x00e4e400 +#define DENALI_PHY_401_DATA 0x00000000 +#define DENALI_PHY_402_DATA 0x00000000 +#define DENALI_PHY_403_DATA 0x00000000 +#define DENALI_PHY_404_DATA 0x00000000 +#define DENALI_PHY_405_DATA 0x00000000 +#define DENALI_PHY_406_DATA 0x00000000 +#define DENALI_PHY_407_DATA 0x00000000 +#define DENALI_PHY_408_DATA 0x00000000 +#define DENALI_PHY_409_DATA 0x00000000 +#define DENALI_PHY_410_DATA 0x00000000 +#define DENALI_PHY_411_DATA 0x00000000 +#define DENALI_PHY_412_DATA 0x00000000 +#define DENALI_PHY_413_DATA 0x00000000 +#define DENALI_PHY_414_DATA 0x00000000 +#define DENALI_PHY_415_DATA 0x00000000 +#define DENALI_PHY_416_DATA 0x00000000 +#define DENALI_PHY_417_DATA 0x00200000 +#define DENALI_PHY_418_DATA 0x00000000 +#define DENALI_PHY_419_DATA 0x00000000 +#define DENALI_PHY_420_DATA 0x00000000 +#define DENALI_PHY_421_DATA 0x00000000 +#define DENALI_PHY_422_DATA 0x00000000 +#define DENALI_PHY_423_DATA 0x00000000 +#define DENALI_PHY_424_DATA 0x02800280 +#define DENALI_PHY_425_DATA 0x02800280 +#define DENALI_PHY_426_DATA 0x02800280 +#define DENALI_PHY_427_DATA 0x02800280 +#define DENALI_PHY_428_DATA 0x00000280 +#define DENALI_PHY_429_DATA 0x00000000 +#define DENALI_PHY_430_DATA 0x00000000 +#define DENALI_PHY_431_DATA 0x00000000 +#define DENALI_PHY_432_DATA 0x00000000 +#define DENALI_PHY_433_DATA 0x00000000 +#define DENALI_PHY_434_DATA 0x00800080 +#define DENALI_PHY_435_DATA 0x00800080 +#define DENALI_PHY_436_DATA 0x00800080 +#define DENALI_PHY_437_DATA 0x00800080 +#define DENALI_PHY_438_DATA 0x00800080 +#define DENALI_PHY_439_DATA 0x00800080 +#define DENALI_PHY_440_DATA 0x00800080 +#define DENALI_PHY_441_DATA 0x00800080 +#define DENALI_PHY_442_DATA 0x00800080 +#define DENALI_PHY_443_DATA 0x000100da +#define DENALI_PHY_444_DATA 0x01ff0010 +#define DENALI_PHY_445_DATA 0x00000000 +#define DENALI_PHY_446_DATA 0x00000000 +#define DENALI_PHY_447_DATA 0x00000002 +#define DENALI_PHY_448_DATA 0x51313152 +#define DENALI_PHY_449_DATA 0x80013130 +#define DENALI_PHY_450_DATA 0x02000080 +#define DENALI_PHY_451_DATA 0x00100001 +#define DENALI_PHY_452_DATA 0x0c064208 +#define DENALI_PHY_453_DATA 0x000f0c0f +#define DENALI_PHY_454_DATA 0x01000140 +#define DENALI_PHY_455_DATA 0x0000000c +#define DENALI_PHY_456_DATA 0x00000000 +#define DENALI_PHY_457_DATA 0x00000000 +#define DENALI_PHY_458_DATA 0x00000000 +#define DENALI_PHY_459_DATA 0x00000000 +#define DENALI_PHY_460_DATA 0x00000000 +#define DENALI_PHY_461_DATA 0x00000000 +#define DENALI_PHY_462_DATA 0x00000000 +#define DENALI_PHY_463_DATA 0x00000000 +#define DENALI_PHY_464_DATA 0x00000000 +#define DENALI_PHY_465_DATA 0x00000000 +#define DENALI_PHY_466_DATA 0x00000000 +#define DENALI_PHY_467_DATA 0x00000000 +#define DENALI_PHY_468_DATA 0x00000000 +#define DENALI_PHY_469_DATA 0x00000000 +#define DENALI_PHY_470_DATA 0x00000000 +#define DENALI_PHY_471_DATA 0x00000000 +#define DENALI_PHY_472_DATA 0x00000000 +#define DENALI_PHY_473_DATA 0x00000000 +#define DENALI_PHY_474_DATA 0x00000000 +#define DENALI_PHY_475_DATA 0x00000000 +#define DENALI_PHY_476_DATA 0x00000000 +#define DENALI_PHY_477_DATA 0x00000000 +#define DENALI_PHY_478_DATA 0x00000000 +#define DENALI_PHY_479_DATA 0x00000000 +#define DENALI_PHY_480_DATA 0x00000000 +#define DENALI_PHY_481_DATA 0x00000000 +#define DENALI_PHY_482_DATA 0x00000000 +#define DENALI_PHY_483_DATA 0x00000000 +#define DENALI_PHY_484_DATA 0x00000000 +#define DENALI_PHY_485_DATA 0x00000000 +#define DENALI_PHY_486_DATA 0x00000000 +#define DENALI_PHY_487_DATA 0x00000000 +#define DENALI_PHY_488_DATA 0x00000000 +#define DENALI_PHY_489_DATA 0x00000000 +#define DENALI_PHY_490_DATA 0x00000000 +#define DENALI_PHY_491_DATA 0x00000000 +#define DENALI_PHY_492_DATA 0x00000000 +#define DENALI_PHY_493_DATA 0x00000000 +#define DENALI_PHY_494_DATA 0x00000000 +#define DENALI_PHY_495_DATA 0x00000000 +#define DENALI_PHY_496_DATA 0x00000000 +#define DENALI_PHY_497_DATA 0x00000000 +#define DENALI_PHY_498_DATA 0x00000000 +#define DENALI_PHY_499_DATA 0x00000000 +#define DENALI_PHY_500_DATA 0x00000000 +#define DENALI_PHY_501_DATA 0x00000000 +#define DENALI_PHY_502_DATA 0x00000000 +#define DENALI_PHY_503_DATA 0x00000000 +#define DENALI_PHY_504_DATA 0x00000000 +#define DENALI_PHY_505_DATA 0x00000000 +#define DENALI_PHY_506_DATA 0x00000000 +#define DENALI_PHY_507_DATA 0x00000000 +#define DENALI_PHY_508_DATA 0x00000000 +#define DENALI_PHY_509_DATA 0x00000000 +#define DENALI_PHY_510_DATA 0x00000000 +#define DENALI_PHY_511_DATA 0x00000000 +#define DENALI_PHY_512_DATA 0x34216750 +#define DENALI_PHY_513_DATA 0x0004c008 +#define DENALI_PHY_514_DATA 0x000000da +#define DENALI_PHY_515_DATA 0x00000000 +#define DENALI_PHY_516_DATA 0x00000000 +#define DENALI_PHY_517_DATA 0x00010000 +#define DENALI_PHY_518_DATA 0x01DDDD90 +#define DENALI_PHY_519_DATA 0x01DDDD90 +#define DENALI_PHY_520_DATA 0x01030001 +#define DENALI_PHY_521_DATA 0x01000000 +#define DENALI_PHY_522_DATA 0x00c00000 +#define DENALI_PHY_523_DATA 0x00000007 +#define DENALI_PHY_524_DATA 0x00000000 +#define DENALI_PHY_525_DATA 0x00000000 +#define DENALI_PHY_526_DATA 0x04000408 +#define DENALI_PHY_527_DATA 0x00000408 +#define DENALI_PHY_528_DATA 0x00e4e400 +#define DENALI_PHY_529_DATA 0x00000000 +#define DENALI_PHY_530_DATA 0x00000000 +#define DENALI_PHY_531_DATA 0x00000000 +#define DENALI_PHY_532_DATA 0x00000000 +#define DENALI_PHY_533_DATA 0x00000000 +#define DENALI_PHY_534_DATA 0x00000000 +#define DENALI_PHY_535_DATA 0x00000000 +#define DENALI_PHY_536_DATA 0x00000000 +#define DENALI_PHY_537_DATA 0x00000000 +#define DENALI_PHY_538_DATA 0x00000000 +#define DENALI_PHY_539_DATA 0x00000000 +#define DENALI_PHY_540_DATA 0x00000000 +#define DENALI_PHY_541_DATA 0x00000000 +#define DENALI_PHY_542_DATA 0x00000000 +#define DENALI_PHY_543_DATA 0x00000000 +#define DENALI_PHY_544_DATA 0x00000000 +#define DENALI_PHY_545_DATA 0x00200000 +#define DENALI_PHY_546_DATA 0x00000000 +#define DENALI_PHY_547_DATA 0x00000000 +#define DENALI_PHY_548_DATA 0x00000000 +#define DENALI_PHY_549_DATA 0x00000000 +#define DENALI_PHY_550_DATA 0x00000000 +#define DENALI_PHY_551_DATA 0x00000000 +#define DENALI_PHY_552_DATA 0x02800280 +#define DENALI_PHY_553_DATA 0x02800280 +#define DENALI_PHY_554_DATA 0x02800280 +#define DENALI_PHY_555_DATA 0x02800280 +#define DENALI_PHY_556_DATA 0x00000280 +#define DENALI_PHY_557_DATA 0x00000000 +#define DENALI_PHY_558_DATA 0x00000000 +#define DENALI_PHY_559_DATA 0x00000000 +#define DENALI_PHY_560_DATA 0x00000000 +#define DENALI_PHY_561_DATA 0x00000000 +#define DENALI_PHY_562_DATA 0x00800080 +#define DENALI_PHY_563_DATA 0x00800080 +#define DENALI_PHY_564_DATA 0x00800080 +#define DENALI_PHY_565_DATA 0x00800080 +#define DENALI_PHY_566_DATA 0x00800080 +#define DENALI_PHY_567_DATA 0x00800080 +#define DENALI_PHY_568_DATA 0x00800080 +#define DENALI_PHY_569_DATA 0x00800080 +#define DENALI_PHY_570_DATA 0x00800080 +#define DENALI_PHY_571_DATA 0x000100da +#define DENALI_PHY_572_DATA 0x01ff0010 +#define DENALI_PHY_573_DATA 0x00000000 +#define DENALI_PHY_574_DATA 0x00000000 +#define DENALI_PHY_575_DATA 0x00000002 +#define DENALI_PHY_576_DATA 0x51313152 +#define DENALI_PHY_577_DATA 0x80013130 +#define DENALI_PHY_578_DATA 0x02000080 +#define DENALI_PHY_579_DATA 0x00100001 +#define DENALI_PHY_580_DATA 0x0c064208 +#define DENALI_PHY_581_DATA 0x000f0c0f +#define DENALI_PHY_582_DATA 0x01000140 +#define DENALI_PHY_583_DATA 0x0000000c +#define DENALI_PHY_584_DATA 0x00000000 +#define DENALI_PHY_585_DATA 0x00000000 +#define DENALI_PHY_586_DATA 0x00000000 +#define DENALI_PHY_587_DATA 0x00000000 +#define DENALI_PHY_588_DATA 0x00000000 +#define DENALI_PHY_589_DATA 0x00000000 +#define DENALI_PHY_590_DATA 0x00000000 +#define DENALI_PHY_591_DATA 0x00000000 +#define DENALI_PHY_592_DATA 0x00000000 +#define DENALI_PHY_593_DATA 0x00000000 +#define DENALI_PHY_594_DATA 0x00000000 +#define DENALI_PHY_595_DATA 0x00000000 +#define DENALI_PHY_596_DATA 0x00000000 +#define DENALI_PHY_597_DATA 0x00000000 +#define DENALI_PHY_598_DATA 0x00000000 +#define DENALI_PHY_599_DATA 0x00000000 +#define DENALI_PHY_600_DATA 0x00000000 +#define DENALI_PHY_601_DATA 0x00000000 +#define DENALI_PHY_602_DATA 0x00000000 +#define DENALI_PHY_603_DATA 0x00000000 +#define DENALI_PHY_604_DATA 0x00000000 +#define DENALI_PHY_605_DATA 0x00000000 +#define DENALI_PHY_606_DATA 0x00000000 +#define DENALI_PHY_607_DATA 0x00000000 +#define DENALI_PHY_608_DATA 0x00000000 +#define DENALI_PHY_609_DATA 0x00000000 +#define DENALI_PHY_610_DATA 0x00000000 +#define DENALI_PHY_611_DATA 0x00000000 +#define DENALI_PHY_612_DATA 0x00000000 +#define DENALI_PHY_613_DATA 0x00000000 +#define DENALI_PHY_614_DATA 0x00000000 +#define DENALI_PHY_615_DATA 0x00000000 +#define DENALI_PHY_616_DATA 0x00000000 +#define DENALI_PHY_617_DATA 0x00000000 +#define DENALI_PHY_618_DATA 0x00000000 +#define DENALI_PHY_619_DATA 0x00000000 +#define DENALI_PHY_620_DATA 0x00000000 +#define DENALI_PHY_621_DATA 0x00000000 +#define DENALI_PHY_622_DATA 0x00000000 +#define DENALI_PHY_623_DATA 0x00000000 +#define DENALI_PHY_624_DATA 0x00000000 +#define DENALI_PHY_625_DATA 0x00000000 +#define DENALI_PHY_626_DATA 0x00000000 +#define DENALI_PHY_627_DATA 0x00000000 +#define DENALI_PHY_628_DATA 0x00000000 +#define DENALI_PHY_629_DATA 0x00000000 +#define DENALI_PHY_630_DATA 0x00000000 +#define DENALI_PHY_631_DATA 0x00000000 +#define DENALI_PHY_632_DATA 0x00000000 +#define DENALI_PHY_633_DATA 0x00000000 +#define DENALI_PHY_634_DATA 0x00000000 +#define DENALI_PHY_635_DATA 0x00000000 +#define DENALI_PHY_636_DATA 0x00000000 +#define DENALI_PHY_637_DATA 0x00000000 +#define DENALI_PHY_638_DATA 0x00000000 +#define DENALI_PHY_639_DATA 0x00000000 +#define DENALI_PHY_640_DATA 0x35176402 +#define DENALI_PHY_641_DATA 0x0004c008 +#define DENALI_PHY_642_DATA 0x000000da +#define DENALI_PHY_643_DATA 0x00000000 +#define DENALI_PHY_644_DATA 0x00000000 +#define DENALI_PHY_645_DATA 0x00010000 +#define DENALI_PHY_646_DATA 0x01DDDD90 +#define DENALI_PHY_647_DATA 0x01DDDD90 +#define DENALI_PHY_648_DATA 0x01030001 +#define DENALI_PHY_649_DATA 0x01000000 +#define DENALI_PHY_650_DATA 0x00c00000 +#define DENALI_PHY_651_DATA 0x00000007 +#define DENALI_PHY_652_DATA 0x00000000 +#define DENALI_PHY_653_DATA 0x00000000 +#define DENALI_PHY_654_DATA 0x04000408 +#define DENALI_PHY_655_DATA 0x00000408 +#define DENALI_PHY_656_DATA 0x00e4e400 +#define DENALI_PHY_657_DATA 0x00000000 +#define DENALI_PHY_658_DATA 0x00000000 +#define DENALI_PHY_659_DATA 0x00000000 +#define DENALI_PHY_660_DATA 0x00000000 +#define DENALI_PHY_661_DATA 0x00000000 +#define DENALI_PHY_662_DATA 0x00000000 +#define DENALI_PHY_663_DATA 0x00000000 +#define DENALI_PHY_664_DATA 0x00000000 +#define DENALI_PHY_665_DATA 0x00000000 +#define DENALI_PHY_666_DATA 0x00000000 +#define DENALI_PHY_667_DATA 0x00000000 +#define DENALI_PHY_668_DATA 0x00000000 +#define DENALI_PHY_669_DATA 0x00000000 +#define DENALI_PHY_670_DATA 0x00000000 +#define DENALI_PHY_671_DATA 0x00000000 +#define DENALI_PHY_672_DATA 0x00000000 +#define DENALI_PHY_673_DATA 0x00200000 +#define DENALI_PHY_674_DATA 0x00000000 +#define DENALI_PHY_675_DATA 0x00000000 +#define DENALI_PHY_676_DATA 0x00000000 +#define DENALI_PHY_677_DATA 0x00000000 +#define DENALI_PHY_678_DATA 0x00000000 +#define DENALI_PHY_679_DATA 0x00000000 +#define DENALI_PHY_680_DATA 0x02800280 +#define DENALI_PHY_681_DATA 0x02800280 +#define DENALI_PHY_682_DATA 0x02800280 +#define DENALI_PHY_683_DATA 0x02800280 +#define DENALI_PHY_684_DATA 0x00000280 +#define DENALI_PHY_685_DATA 0x00000000 +#define DENALI_PHY_686_DATA 0x00000000 +#define DENALI_PHY_687_DATA 0x00000000 +#define DENALI_PHY_688_DATA 0x00000000 +#define DENALI_PHY_689_DATA 0x00000000 +#define DENALI_PHY_690_DATA 0x00800080 +#define DENALI_PHY_691_DATA 0x00800080 +#define DENALI_PHY_692_DATA 0x00800080 +#define DENALI_PHY_693_DATA 0x00800080 +#define DENALI_PHY_694_DATA 0x00800080 +#define DENALI_PHY_695_DATA 0x00800080 +#define DENALI_PHY_696_DATA 0x00800080 +#define DENALI_PHY_697_DATA 0x00800080 +#define DENALI_PHY_698_DATA 0x00800080 +#define DENALI_PHY_699_DATA 0x000100da +#define DENALI_PHY_700_DATA 0x01ff0010 +#define DENALI_PHY_701_DATA 0x00000000 +#define DENALI_PHY_702_DATA 0x00000000 +#define DENALI_PHY_703_DATA 0x00000002 +#define DENALI_PHY_704_DATA 0x51313152 +#define DENALI_PHY_705_DATA 0x80013130 +#define DENALI_PHY_706_DATA 0x02000080 +#define DENALI_PHY_707_DATA 0x00100001 +#define DENALI_PHY_708_DATA 0x0c064208 +#define DENALI_PHY_709_DATA 0x000f0c0f +#define DENALI_PHY_710_DATA 0x01000140 +#define DENALI_PHY_711_DATA 0x0000000c +#define DENALI_PHY_712_DATA 0x00000000 +#define DENALI_PHY_713_DATA 0x00000000 +#define DENALI_PHY_714_DATA 0x00000000 +#define DENALI_PHY_715_DATA 0x00000000 +#define DENALI_PHY_716_DATA 0x00000000 +#define DENALI_PHY_717_DATA 0x00000000 +#define DENALI_PHY_718_DATA 0x00000000 +#define DENALI_PHY_719_DATA 0x00000000 +#define DENALI_PHY_720_DATA 0x00000000 +#define DENALI_PHY_721_DATA 0x00000000 +#define DENALI_PHY_722_DATA 0x00000000 +#define DENALI_PHY_723_DATA 0x00000000 +#define DENALI_PHY_724_DATA 0x00000000 +#define DENALI_PHY_725_DATA 0x00000000 +#define DENALI_PHY_726_DATA 0x00000000 +#define DENALI_PHY_727_DATA 0x00000000 +#define DENALI_PHY_728_DATA 0x00000000 +#define DENALI_PHY_729_DATA 0x00000000 +#define DENALI_PHY_730_DATA 0x00000000 +#define DENALI_PHY_731_DATA 0x00000000 +#define DENALI_PHY_732_DATA 0x00000000 +#define DENALI_PHY_733_DATA 0x00000000 +#define DENALI_PHY_734_DATA 0x00000000 +#define DENALI_PHY_735_DATA 0x00000000 +#define DENALI_PHY_736_DATA 0x00000000 +#define DENALI_PHY_737_DATA 0x00000000 +#define DENALI_PHY_738_DATA 0x00000000 +#define DENALI_PHY_739_DATA 0x00000000 +#define DENALI_PHY_740_DATA 0x00000000 +#define DENALI_PHY_741_DATA 0x00000000 +#define DENALI_PHY_742_DATA 0x00000000 +#define DENALI_PHY_743_DATA 0x00000000 +#define DENALI_PHY_744_DATA 0x00000000 +#define DENALI_PHY_745_DATA 0x00000000 +#define DENALI_PHY_746_DATA 0x00000000 +#define DENALI_PHY_747_DATA 0x00000000 +#define DENALI_PHY_748_DATA 0x00000000 +#define DENALI_PHY_749_DATA 0x00000000 +#define DENALI_PHY_750_DATA 0x00000000 +#define DENALI_PHY_751_DATA 0x00000000 +#define DENALI_PHY_752_DATA 0x00000000 +#define DENALI_PHY_753_DATA 0x00000000 +#define DENALI_PHY_754_DATA 0x00000000 +#define DENALI_PHY_755_DATA 0x00000000 +#define DENALI_PHY_756_DATA 0x00000000 +#define DENALI_PHY_757_DATA 0x00000000 +#define DENALI_PHY_758_DATA 0x00000000 +#define DENALI_PHY_759_DATA 0x00000000 +#define DENALI_PHY_760_DATA 0x00000000 +#define DENALI_PHY_761_DATA 0x00000000 +#define DENALI_PHY_762_DATA 0x00000000 +#define DENALI_PHY_763_DATA 0x00000000 +#define DENALI_PHY_764_DATA 0x00000000 +#define DENALI_PHY_765_DATA 0x00000000 +#define DENALI_PHY_766_DATA 0x00000000 +#define DENALI_PHY_767_DATA 0x00000000 +#define DENALI_PHY_768_DATA 0x10526347 +#define DENALI_PHY_769_DATA 0x0004c008 +#define DENALI_PHY_770_DATA 0x000000da +#define DENALI_PHY_771_DATA 0x00000000 +#define DENALI_PHY_772_DATA 0x00000000 +#define DENALI_PHY_773_DATA 0x00010000 +#define DENALI_PHY_774_DATA 0x01DDDD90 +#define DENALI_PHY_775_DATA 0x01DDDD90 +#define DENALI_PHY_776_DATA 0x01030001 +#define DENALI_PHY_777_DATA 0x01000000 +#define DENALI_PHY_778_DATA 0x00c00000 +#define DENALI_PHY_779_DATA 0x00000007 +#define DENALI_PHY_780_DATA 0x00000000 +#define DENALI_PHY_781_DATA 0x00000000 +#define DENALI_PHY_782_DATA 0x04000408 +#define DENALI_PHY_783_DATA 0x00000408 +#define DENALI_PHY_784_DATA 0x00e4e400 +#define DENALI_PHY_785_DATA 0x00000000 +#define DENALI_PHY_786_DATA 0x00000000 +#define DENALI_PHY_787_DATA 0x00000000 +#define DENALI_PHY_788_DATA 0x00000000 +#define DENALI_PHY_789_DATA 0x00000000 +#define DENALI_PHY_790_DATA 0x00000000 +#define DENALI_PHY_791_DATA 0x00000000 +#define DENALI_PHY_792_DATA 0x00000000 +#define DENALI_PHY_793_DATA 0x00000000 +#define DENALI_PHY_794_DATA 0x00000000 +#define DENALI_PHY_795_DATA 0x00000000 +#define DENALI_PHY_796_DATA 0x00000000 +#define DENALI_PHY_797_DATA 0x00000000 +#define DENALI_PHY_798_DATA 0x00000000 +#define DENALI_PHY_799_DATA 0x00000000 +#define DENALI_PHY_800_DATA 0x00000000 +#define DENALI_PHY_801_DATA 0x00200000 +#define DENALI_PHY_802_DATA 0x00000000 +#define DENALI_PHY_803_DATA 0x00000000 +#define DENALI_PHY_804_DATA 0x00000000 +#define DENALI_PHY_805_DATA 0x00000000 +#define DENALI_PHY_806_DATA 0x00000000 +#define DENALI_PHY_807_DATA 0x00000000 +#define DENALI_PHY_808_DATA 0x02800280 +#define DENALI_PHY_809_DATA 0x02800280 +#define DENALI_PHY_810_DATA 0x02800280 +#define DENALI_PHY_811_DATA 0x02800280 +#define DENALI_PHY_812_DATA 0x00000280 +#define DENALI_PHY_813_DATA 0x00000000 +#define DENALI_PHY_814_DATA 0x00000000 +#define DENALI_PHY_815_DATA 0x00000000 +#define DENALI_PHY_816_DATA 0x00000000 +#define DENALI_PHY_817_DATA 0x00000000 +#define DENALI_PHY_818_DATA 0x00800080 +#define DENALI_PHY_819_DATA 0x00800080 +#define DENALI_PHY_820_DATA 0x00800080 +#define DENALI_PHY_821_DATA 0x00800080 +#define DENALI_PHY_822_DATA 0x00800080 +#define DENALI_PHY_823_DATA 0x00800080 +#define DENALI_PHY_824_DATA 0x00800080 +#define DENALI_PHY_825_DATA 0x00800080 +#define DENALI_PHY_826_DATA 0x00800080 +#define DENALI_PHY_827_DATA 0x000100da +#define DENALI_PHY_828_DATA 0x01ff0010 +#define DENALI_PHY_829_DATA 0x00000000 +#define DENALI_PHY_830_DATA 0x00000000 +#define DENALI_PHY_831_DATA 0x00000002 +#define DENALI_PHY_832_DATA 0x51313152 +#define DENALI_PHY_833_DATA 0x80013130 +#define DENALI_PHY_834_DATA 0x02000080 +#define DENALI_PHY_835_DATA 0x00100001 +#define DENALI_PHY_836_DATA 0x0c064208 +#define DENALI_PHY_837_DATA 0x000f0c0f +#define DENALI_PHY_838_DATA 0x01000140 +#define DENALI_PHY_839_DATA 0x0000000c +#define DENALI_PHY_840_DATA 0x00000000 +#define DENALI_PHY_841_DATA 0x00000000 +#define DENALI_PHY_842_DATA 0x00000000 +#define DENALI_PHY_843_DATA 0x00000000 +#define DENALI_PHY_844_DATA 0x00000000 +#define DENALI_PHY_845_DATA 0x00000000 +#define DENALI_PHY_846_DATA 0x00000000 +#define DENALI_PHY_847_DATA 0x00000000 +#define DENALI_PHY_848_DATA 0x00000000 +#define DENALI_PHY_849_DATA 0x00000000 +#define DENALI_PHY_850_DATA 0x00000000 +#define DENALI_PHY_851_DATA 0x00000000 +#define DENALI_PHY_852_DATA 0x00000000 +#define DENALI_PHY_853_DATA 0x00000000 +#define DENALI_PHY_854_DATA 0x00000000 +#define DENALI_PHY_855_DATA 0x00000000 +#define DENALI_PHY_856_DATA 0x00000000 +#define DENALI_PHY_857_DATA 0x00000000 +#define DENALI_PHY_858_DATA 0x00000000 +#define DENALI_PHY_859_DATA 0x00000000 +#define DENALI_PHY_860_DATA 0x00000000 +#define DENALI_PHY_861_DATA 0x00000000 +#define DENALI_PHY_862_DATA 0x00000000 +#define DENALI_PHY_863_DATA 0x00000000 +#define DENALI_PHY_864_DATA 0x00000000 +#define DENALI_PHY_865_DATA 0x00000000 +#define DENALI_PHY_866_DATA 0x00000000 +#define DENALI_PHY_867_DATA 0x00000000 +#define DENALI_PHY_868_DATA 0x00000000 +#define DENALI_PHY_869_DATA 0x00000000 +#define DENALI_PHY_870_DATA 0x00000000 +#define DENALI_PHY_871_DATA 0x00000000 +#define DENALI_PHY_872_DATA 0x00000000 +#define DENALI_PHY_873_DATA 0x00000000 +#define DENALI_PHY_874_DATA 0x00000000 +#define DENALI_PHY_875_DATA 0x00000000 +#define DENALI_PHY_876_DATA 0x00000000 +#define DENALI_PHY_877_DATA 0x00000000 +#define DENALI_PHY_878_DATA 0x00000000 +#define DENALI_PHY_879_DATA 0x00000000 +#define DENALI_PHY_880_DATA 0x00000000 +#define DENALI_PHY_881_DATA 0x00000000 +#define DENALI_PHY_882_DATA 0x00000000 +#define DENALI_PHY_883_DATA 0x00000000 +#define DENALI_PHY_884_DATA 0x00000000 +#define DENALI_PHY_885_DATA 0x00000000 +#define DENALI_PHY_886_DATA 0x00000000 +#define DENALI_PHY_887_DATA 0x00000000 +#define DENALI_PHY_888_DATA 0x00000000 +#define DENALI_PHY_889_DATA 0x00000000 +#define DENALI_PHY_890_DATA 0x00000000 +#define DENALI_PHY_891_DATA 0x00000000 +#define DENALI_PHY_892_DATA 0x00000000 +#define DENALI_PHY_893_DATA 0x00000000 +#define DENALI_PHY_894_DATA 0x00000000 +#define DENALI_PHY_895_DATA 0x00000000 +#define DENALI_PHY_896_DATA 0x41753260 +#define DENALI_PHY_897_DATA 0x0004c008 +#define DENALI_PHY_898_DATA 0x000000da +#define DENALI_PHY_899_DATA 0x00000000 +#define DENALI_PHY_900_DATA 0x00000000 +#define DENALI_PHY_901_DATA 0x00010000 +#define DENALI_PHY_902_DATA 0x01DDDD90 +#define DENALI_PHY_903_DATA 0x01DDDD90 +#define DENALI_PHY_904_DATA 0x01030001 +#define DENALI_PHY_905_DATA 0x01000000 +#define DENALI_PHY_906_DATA 0x00c00000 +#define DENALI_PHY_907_DATA 0x00000007 +#define DENALI_PHY_908_DATA 0x00000000 +#define DENALI_PHY_909_DATA 0x00000000 +#define DENALI_PHY_910_DATA 0x04000408 +#define DENALI_PHY_911_DATA 0x00000408 +#define DENALI_PHY_912_DATA 0x00e4e400 +#define DENALI_PHY_913_DATA 0x00000000 +#define DENALI_PHY_914_DATA 0x00000000 +#define DENALI_PHY_915_DATA 0x00000000 +#define DENALI_PHY_916_DATA 0x00000000 +#define DENALI_PHY_917_DATA 0x00000000 +#define DENALI_PHY_918_DATA 0x00000000 +#define DENALI_PHY_919_DATA 0x00000000 +#define DENALI_PHY_920_DATA 0x00000000 +#define DENALI_PHY_921_DATA 0x00000000 +#define DENALI_PHY_922_DATA 0x00000000 +#define DENALI_PHY_923_DATA 0x00000000 +#define DENALI_PHY_924_DATA 0x00000000 +#define DENALI_PHY_925_DATA 0x00000000 +#define DENALI_PHY_926_DATA 0x00000000 +#define DENALI_PHY_927_DATA 0x00000000 +#define DENALI_PHY_928_DATA 0x00000000 +#define DENALI_PHY_929_DATA 0x00200000 +#define DENALI_PHY_930_DATA 0x00000000 +#define DENALI_PHY_931_DATA 0x00000000 +#define DENALI_PHY_932_DATA 0x00000000 +#define DENALI_PHY_933_DATA 0x00000000 +#define DENALI_PHY_934_DATA 0x00000000 +#define DENALI_PHY_935_DATA 0x00000000 +#define DENALI_PHY_936_DATA 0x02800280 +#define DENALI_PHY_937_DATA 0x02800280 +#define DENALI_PHY_938_DATA 0x02800280 +#define DENALI_PHY_939_DATA 0x02800280 +#define DENALI_PHY_940_DATA 0x00000280 +#define DENALI_PHY_941_DATA 0x00000000 +#define DENALI_PHY_942_DATA 0x00000000 +#define DENALI_PHY_943_DATA 0x00000000 +#define DENALI_PHY_944_DATA 0x00000000 +#define DENALI_PHY_945_DATA 0x00000000 +#define DENALI_PHY_946_DATA 0x00800080 +#define DENALI_PHY_947_DATA 0x00800080 +#define DENALI_PHY_948_DATA 0x00800080 +#define DENALI_PHY_949_DATA 0x00800080 +#define DENALI_PHY_950_DATA 0x00800080 +#define DENALI_PHY_951_DATA 0x00800080 +#define DENALI_PHY_952_DATA 0x00800080 +#define DENALI_PHY_953_DATA 0x00800080 +#define DENALI_PHY_954_DATA 0x00800080 +#define DENALI_PHY_955_DATA 0x000100da +#define DENALI_PHY_956_DATA 0x01ff0010 +#define DENALI_PHY_957_DATA 0x00000000 +#define DENALI_PHY_958_DATA 0x00000000 +#define DENALI_PHY_959_DATA 0x00000002 +#define DENALI_PHY_960_DATA 0x51313152 +#define DENALI_PHY_961_DATA 0x80013130 +#define DENALI_PHY_962_DATA 0x02000080 +#define DENALI_PHY_963_DATA 0x00100001 +#define DENALI_PHY_964_DATA 0x0c064208 +#define DENALI_PHY_965_DATA 0x000f0c0f +#define DENALI_PHY_966_DATA 0x01000140 +#define DENALI_PHY_967_DATA 0x0000000c +#define DENALI_PHY_968_DATA 0x00000000 +#define DENALI_PHY_969_DATA 0x00000000 +#define DENALI_PHY_970_DATA 0x00000000 +#define DENALI_PHY_971_DATA 0x00000000 +#define DENALI_PHY_972_DATA 0x00000000 +#define DENALI_PHY_973_DATA 0x00000000 +#define DENALI_PHY_974_DATA 0x00000000 +#define DENALI_PHY_975_DATA 0x00000000 +#define DENALI_PHY_976_DATA 0x00000000 +#define DENALI_PHY_977_DATA 0x00000000 +#define DENALI_PHY_978_DATA 0x00000000 +#define DENALI_PHY_979_DATA 0x00000000 +#define DENALI_PHY_980_DATA 0x00000000 +#define DENALI_PHY_981_DATA 0x00000000 +#define DENALI_PHY_982_DATA 0x00000000 +#define DENALI_PHY_983_DATA 0x00000000 +#define DENALI_PHY_984_DATA 0x00000000 +#define DENALI_PHY_985_DATA 0x00000000 +#define DENALI_PHY_986_DATA 0x00000000 +#define DENALI_PHY_987_DATA 0x00000000 +#define DENALI_PHY_988_DATA 0x00000000 +#define DENALI_PHY_989_DATA 0x00000000 +#define DENALI_PHY_990_DATA 0x00000000 +#define DENALI_PHY_991_DATA 0x00000000 +#define DENALI_PHY_992_DATA 0x00000000 +#define DENALI_PHY_993_DATA 0x00000000 +#define DENALI_PHY_994_DATA 0x00000000 +#define DENALI_PHY_995_DATA 0x00000000 +#define DENALI_PHY_996_DATA 0x00000000 +#define DENALI_PHY_997_DATA 0x00000000 +#define DENALI_PHY_998_DATA 0x00000000 +#define DENALI_PHY_999_DATA 0x00000000 +#define DENALI_PHY_1000_DATA 0x00000000 +#define DENALI_PHY_1001_DATA 0x00000000 +#define DENALI_PHY_1002_DATA 0x00000000 +#define DENALI_PHY_1003_DATA 0x00000000 +#define DENALI_PHY_1004_DATA 0x00000000 +#define DENALI_PHY_1005_DATA 0x00000000 +#define DENALI_PHY_1006_DATA 0x00000000 +#define DENALI_PHY_1007_DATA 0x00000000 +#define DENALI_PHY_1008_DATA 0x00000000 +#define DENALI_PHY_1009_DATA 0x00000000 +#define DENALI_PHY_1010_DATA 0x00000000 +#define DENALI_PHY_1011_DATA 0x00000000 +#define DENALI_PHY_1012_DATA 0x00000000 +#define DENALI_PHY_1013_DATA 0x00000000 +#define DENALI_PHY_1014_DATA 0x00000000 +#define DENALI_PHY_1015_DATA 0x00000000 +#define DENALI_PHY_1016_DATA 0x00000000 +#define DENALI_PHY_1017_DATA 0x00000000 +#define DENALI_PHY_1018_DATA 0x00000000 +#define DENALI_PHY_1019_DATA 0x00000000 +#define DENALI_PHY_1020_DATA 0x00000000 +#define DENALI_PHY_1021_DATA 0x00000000 +#define DENALI_PHY_1022_DATA 0x00000000 +#define DENALI_PHY_1023_DATA 0x00000000 +#define DENALI_PHY_1024_DATA 0x76543210 +#define DENALI_PHY_1025_DATA 0x0004c008 +#define DENALI_PHY_1026_DATA 0x000000da +#define DENALI_PHY_1027_DATA 0x00000000 +#define DENALI_PHY_1028_DATA 0x00000000 +#define DENALI_PHY_1029_DATA 0x00010000 +#define DENALI_PHY_1030_DATA 0x01665555 +#define DENALI_PHY_1031_DATA 0x01665555 +#define DENALI_PHY_1032_DATA 0x01030001 +#define DENALI_PHY_1033_DATA 0x01000000 +#define DENALI_PHY_1034_DATA 0x00c00000 +#define DENALI_PHY_1035_DATA 0x00000007 +#define DENALI_PHY_1036_DATA 0x00000000 +#define DENALI_PHY_1037_DATA 0x00000000 +#define DENALI_PHY_1038_DATA 0x04000408 +#define DENALI_PHY_1039_DATA 0x00000408 +#define DENALI_PHY_1040_DATA 0x00e4e400 +#define DENALI_PHY_1041_DATA 0x00000000 +#define DENALI_PHY_1042_DATA 0x00000000 +#define DENALI_PHY_1043_DATA 0x00000000 +#define DENALI_PHY_1044_DATA 0x00000000 +#define DENALI_PHY_1045_DATA 0x00000000 +#define DENALI_PHY_1046_DATA 0x00000000 +#define DENALI_PHY_1047_DATA 0x00000000 +#define DENALI_PHY_1048_DATA 0x00000000 +#define DENALI_PHY_1049_DATA 0x00000000 +#define DENALI_PHY_1050_DATA 0x00000000 +#define DENALI_PHY_1051_DATA 0x00000000 +#define DENALI_PHY_1052_DATA 0x00000000 +#define DENALI_PHY_1053_DATA 0x00000000 +#define DENALI_PHY_1054_DATA 0x00000000 +#define DENALI_PHY_1055_DATA 0x00000000 +#define DENALI_PHY_1056_DATA 0x00000000 +#define DENALI_PHY_1057_DATA 0x00200000 +#define DENALI_PHY_1058_DATA 0x00000000 +#define DENALI_PHY_1059_DATA 0x00000000 +#define DENALI_PHY_1060_DATA 0x00000000 +#define DENALI_PHY_1061_DATA 0x00000000 +#define DENALI_PHY_1062_DATA 0x00000000 +#define DENALI_PHY_1063_DATA 0x00000000 +#define DENALI_PHY_1064_DATA 0x02800280 +#define DENALI_PHY_1065_DATA 0x02800280 +#define DENALI_PHY_1066_DATA 0x02800280 +#define DENALI_PHY_1067_DATA 0x02800280 +#define DENALI_PHY_1068_DATA 0x00000280 +#define DENALI_PHY_1069_DATA 0x00000000 +#define DENALI_PHY_1070_DATA 0x00000000 +#define DENALI_PHY_1071_DATA 0x00000000 +#define DENALI_PHY_1072_DATA 0x00000000 +#define DENALI_PHY_1073_DATA 0x00000000 +#define DENALI_PHY_1074_DATA 0x00800080 +#define DENALI_PHY_1075_DATA 0x00800080 +#define DENALI_PHY_1076_DATA 0x00800080 +#define DENALI_PHY_1077_DATA 0x00800080 +#define DENALI_PHY_1078_DATA 0x00800080 +#define DENALI_PHY_1079_DATA 0x00800080 +#define DENALI_PHY_1080_DATA 0x00800080 +#define DENALI_PHY_1081_DATA 0x00800080 +#define DENALI_PHY_1082_DATA 0x00800080 +#define DENALI_PHY_1083_DATA 0x000100da +#define DENALI_PHY_1084_DATA 0x01ff0010 +#define DENALI_PHY_1085_DATA 0x00000000 +#define DENALI_PHY_1086_DATA 0x00000000 +#define DENALI_PHY_1087_DATA 0x00000002 +#define DENALI_PHY_1088_DATA 0x51313152 +#define DENALI_PHY_1089_DATA 0x80013130 +#define DENALI_PHY_1090_DATA 0x02000080 +#define DENALI_PHY_1091_DATA 0x00100001 +#define DENALI_PHY_1092_DATA 0x0c064208 +#define DENALI_PHY_1093_DATA 0x000f0c0f +#define DENALI_PHY_1094_DATA 0x01000140 +#define DENALI_PHY_1095_DATA 0x0000000c +#define DENALI_PHY_1096_DATA 0x00000000 +#define DENALI_PHY_1097_DATA 0x00000000 +#define DENALI_PHY_1098_DATA 0x00000000 +#define DENALI_PHY_1099_DATA 0x00000000 +#define DENALI_PHY_1100_DATA 0x00000000 +#define DENALI_PHY_1101_DATA 0x00000000 +#define DENALI_PHY_1102_DATA 0x00000000 +#define DENALI_PHY_1103_DATA 0x00000000 +#define DENALI_PHY_1104_DATA 0x00000000 +#define DENALI_PHY_1105_DATA 0x00000000 +#define DENALI_PHY_1106_DATA 0x00000000 +#define DENALI_PHY_1107_DATA 0x00000000 +#define DENALI_PHY_1108_DATA 0x00000000 +#define DENALI_PHY_1109_DATA 0x00000000 +#define DENALI_PHY_1110_DATA 0x00000000 +#define DENALI_PHY_1111_DATA 0x00000000 +#define DENALI_PHY_1112_DATA 0x00000000 +#define DENALI_PHY_1113_DATA 0x00000000 +#define DENALI_PHY_1114_DATA 0x00000000 +#define DENALI_PHY_1115_DATA 0x00000000 +#define DENALI_PHY_1116_DATA 0x00000000 +#define DENALI_PHY_1117_DATA 0x00000000 +#define DENALI_PHY_1118_DATA 0x00000000 +#define DENALI_PHY_1119_DATA 0x00000000 +#define DENALI_PHY_1120_DATA 0x00000000 +#define DENALI_PHY_1121_DATA 0x00000000 +#define DENALI_PHY_1122_DATA 0x00000000 +#define DENALI_PHY_1123_DATA 0x00000000 +#define DENALI_PHY_1124_DATA 0x00000000 +#define DENALI_PHY_1125_DATA 0x00000000 +#define DENALI_PHY_1126_DATA 0x00000000 +#define DENALI_PHY_1127_DATA 0x00000000 +#define DENALI_PHY_1128_DATA 0x00000000 +#define DENALI_PHY_1129_DATA 0x00000000 +#define DENALI_PHY_1130_DATA 0x00000000 +#define DENALI_PHY_1131_DATA 0x00000000 +#define DENALI_PHY_1132_DATA 0x00000000 +#define DENALI_PHY_1133_DATA 0x00000000 +#define DENALI_PHY_1134_DATA 0x00000000 +#define DENALI_PHY_1135_DATA 0x00000000 +#define DENALI_PHY_1136_DATA 0x00000000 +#define DENALI_PHY_1137_DATA 0x00000000 +#define DENALI_PHY_1138_DATA 0x00000000 +#define DENALI_PHY_1139_DATA 0x00000000 +#define DENALI_PHY_1140_DATA 0x00000000 +#define DENALI_PHY_1141_DATA 0x00000000 +#define DENALI_PHY_1142_DATA 0x00000000 +#define DENALI_PHY_1143_DATA 0x00000000 +#define DENALI_PHY_1144_DATA 0x00000000 +#define DENALI_PHY_1145_DATA 0x00000000 +#define DENALI_PHY_1146_DATA 0x00000000 +#define DENALI_PHY_1147_DATA 0x00000000 +#define DENALI_PHY_1148_DATA 0x00000000 +#define DENALI_PHY_1149_DATA 0x00000000 +#define DENALI_PHY_1150_DATA 0x00000000 +#define DENALI_PHY_1151_DATA 0x00000000 +#define DENALI_PHY_1152_DATA 0x00000000 +#define DENALI_PHY_1153_DATA 0x00000000 +#define DENALI_PHY_1154_DATA 0x00050000 +#define DENALI_PHY_1155_DATA 0x00000000 +#define DENALI_PHY_1156_DATA 0x00000000 +#define DENALI_PHY_1157_DATA 0x00000000 +#define DENALI_PHY_1158_DATA 0x00000100 +#define DENALI_PHY_1159_DATA 0x00000000 +#define DENALI_PHY_1160_DATA 0x00000000 +#define DENALI_PHY_1161_DATA 0x00506401 +#define DENALI_PHY_1162_DATA 0x01221102 +#define DENALI_PHY_1163_DATA 0x00000122 +#define DENALI_PHY_1164_DATA 0x00000000 +#define DENALI_PHY_1165_DATA 0x000B1F00 +#define DENALI_PHY_1166_DATA 0x0B1F0B1F +#define DENALI_PHY_1167_DATA 0x0B1F0B1F +#define DENALI_PHY_1168_DATA 0x0B1F0B1F +#define DENALI_PHY_1169_DATA 0x0B1F0B1F +#define DENALI_PHY_1170_DATA 0x00000B00 +#define DENALI_PHY_1171_DATA 0x42080010 +#define DENALI_PHY_1172_DATA 0x01000100 +#define DENALI_PHY_1173_DATA 0x01000100 +#define DENALI_PHY_1174_DATA 0x01000100 +#define DENALI_PHY_1175_DATA 0x01000100 +#define DENALI_PHY_1176_DATA 0x00000000 +#define DENALI_PHY_1177_DATA 0x00000000 +#define DENALI_PHY_1178_DATA 0x00000000 +#define DENALI_PHY_1179_DATA 0x00000000 +#define DENALI_PHY_1180_DATA 0x00000000 +#define DENALI_PHY_1181_DATA 0x00000803 +#define DENALI_PHY_1182_DATA 0x223FFF00 +#define DENALI_PHY_1183_DATA 0x000008FF +#define DENALI_PHY_1184_DATA 0x0000057F +#define DENALI_PHY_1185_DATA 0x0000057F +#define DENALI_PHY_1186_DATA 0x00037FFF +#define DENALI_PHY_1187_DATA 0x00037FFF +#define DENALI_PHY_1188_DATA 0x00004410 +#define DENALI_PHY_1189_DATA 0x00004410 +#define DENALI_PHY_1190_DATA 0x00004410 +#define DENALI_PHY_1191_DATA 0x00004410 +#define DENALI_PHY_1192_DATA 0x00004410 +#define DENALI_PHY_1193_DATA 0x00000111 +#define DENALI_PHY_1194_DATA 0x00000111 +#define DENALI_PHY_1195_DATA 0x00000000 +#define DENALI_PHY_1196_DATA 0x00000000 +#define DENALI_PHY_1197_DATA 0x00000000 +#define DENALI_PHY_1198_DATA 0x04000000 +#define DENALI_PHY_1199_DATA 0x00000000 +#define DENALI_PHY_1200_DATA 0x00000000 +#define DENALI_PHY_1201_DATA 0x00000108 +#define DENALI_PHY_1202_DATA 0x00000000 +#define DENALI_PHY_1203_DATA 0x00000000 +#define DENALI_PHY_1204_DATA 0x00000000 +#define DENALI_PHY_1205_DATA 0x00000001 +#define DENALI_PHY_1206_DATA 0x00000000 +#define DENALI_PHY_1207_DATA 0x00000000 +#define DENALI_PHY_1208_DATA 0x00000000 +#define DENALI_PHY_1209_DATA 0x00000000 +#define DENALI_PHY_1210_DATA 0x00000000 +#define DENALI_PHY_1211_DATA 0x00000000 +#define DENALI_PHY_1212_DATA 0x00020100 +#define DENALI_PHY_1213_DATA 0x00000000 +#define DENALI_PHY_1214_DATA 0x00000000 diff --git a/src/soc/sifive/fu740/sdram.c b/src/soc/sifive/fu740/sdram.c new file mode 100644 index 0000000..8b5415c --- /dev/null +++ b/src/soc/sifive/fu740/sdram.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/sdram.h> +#include <soc/addressmap.h> +#include <soc/ux00ddr.h> + +//TODO put this in common code + +extern const uint32_t denali_ddr_phy_data[1215]; +extern const uint32_t denali_ddr_ctl_data[265]; + +//TODO move to mainboard code +#define DDR_SIZE (16UL * 1024UL * 1024UL * 1024UL) + +#define FU740_PHYSICAL_FILTER 0x100b8000 // formerly called DDRBUSBLOCKER (fu540) + +void sdram_init(void) +{ + ux00ddr_writeregmap(FU740_DDRCTRL, denali_ddr_ctl_data, denali_ddr_phy_data); + ux00ddr_disableaxireadinterleave(FU740_DDRCTRL); + + ux00ddr_disableoptimalrmodw(FU740_DDRCTRL); + + ux00ddr_enablewriteleveling(FU740_DDRCTRL); + ux00ddr_enablereadleveling(FU740_DDRCTRL); + ux00ddr_enablereadlevelinggate(FU740_DDRCTRL); + if (ux00ddr_getdramclass(FU740_DDRCTRL) == DRAM_CLASS_DDR4) + ux00ddr_enablevreftraining(FU740_DDRCTRL); + + //mask off interrupts for leveling completion + ux00ddr_mask_leveling_completed_interrupt(FU740_DDRCTRL); + + ux00ddr_mask_mc_init_complete_interrupt(FU740_DDRCTRL); + ux00ddr_mask_outofrange_interrupts(FU740_DDRCTRL); + ux00ddr_setuprangeprotection(FU740_DDRCTRL, DDR_SIZE); + ux00ddr_mask_port_command_error_interrupt(FU740_DDRCTRL); + + const uint64_t ddr_size = DDR_SIZE; + const uint64_t ddr_end = FU740_DRAM + ddr_size; + ux00ddr_start(FU740_DDRCTRL, FU740_PHYSICAL_FILTER, ddr_end); + + ux00ddr_phy_fixup(FU740_DDRCTRL); +} + +size_t sdram_size(void) +{ + //TODO take it from physical filter register + return (uint64_t)16 * 1024 * 1024 * 1024; +} diff --git a/src/soc/sifive/fu740/spi.c b/src/soc/sifive/fu740/spi.c new file mode 100644 index 0000000..4f8c592 --- /dev/null +++ b/src/soc/sifive/fu740/spi.c @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/spi.h> +#include <soc/clock.h> +#include <soc/addressmap.h> +#include <delay.h> +#include <lib.h> + +#include "spi_internal.h" + +static struct fu740_spi_ctrl *fu740_spi_ctrls[] = { + (struct fu740_spi_ctrl *)FU740_QSPI0, + (struct fu740_spi_ctrl *)FU740_QSPI1, + (struct fu740_spi_ctrl *)FU740_QSPI2 +}; + +// Wait until SPI is ready for transmission and transmit byte. +static void fu740_spi_tx(volatile struct fu740_spi_ctrl *spictrl_reg, uint8_t in) +{ +#if __riscv_atomic + int32_t r; + do { + asm volatile ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (spictrl_reg->txdata.raw_bits) + : "r" (in) + ); + } while (r < 0); +#else + while ((int32_t) spictrl_reg->txdata.raw_bits < 0) + ; + spictrl_reg->txdata.data = in; +#endif +} + +// Wait until SPI receive queue has data and read byte. +static uint8_t fu740_spi_rx(volatile struct fu740_spi_ctrl *spictrl_reg) +{ + int32_t out; + while ((out = (int32_t) spictrl_reg->rxdata.raw_bits) < 0) + ; + return (uint8_t) out; +} + +static int fu740_spi_xfer(const struct spi_slave *slave, + const void *dout, size_t bytesout, + void *din, size_t bytesin) +{ + printk(BIOS_DEBUG, "%s 0, bytesin: %zu, bytesout: %zu, din: %p\n", __func__, bytesin, bytesout, din); + hexdump(dout, bytesout); + int s = bytesin; + void *d = din; + struct fu740_spi_ctrl *spictrl_reg = fu740_spi_ctrls[slave->bus]; + union fu740_spi_reg_fmt fmt; + fmt.raw_bits = read32(&spictrl_reg->fmt.raw_bits); + if (fmt.proto == FU740_SPI_PROTO_S) { + // working in full-duplex mode + // receiving data needs to be triggered by sending data + while (bytesout || bytesin) { + uint8_t in, out = 0; + if (bytesout) { + out = *(uint8_t *)dout++; + bytesout--; + } + fu740_spi_tx(spictrl_reg, out); + in = fu740_spi_rx(spictrl_reg); + if (bytesin) { + *(uint8_t *)din++ = in; + bytesin--; + } + } + hexdump(d, (s > 100) ? 100 : s); + } else { + // Working in half duplex + // send and receive can be done separately + if (dout && din) + return -1; + + if (dout) { + while (bytesout) { + fu740_spi_tx(spictrl_reg, *(uint8_t *)dout++); + bytesout--; + } + } + + if (din) { + while (bytesin) { + *(uint8_t *)din++ = fu740_spi_rx(spictrl_reg); + bytesin--; + } + } + } + return 0; +} + +static int fu740_spi_claim_bus(const struct spi_slave *slave) +{ + struct fu740_spi_ctrl *spictrl = fu740_spi_ctrls[slave->bus]; + union fu740_spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU740_SPI_CSMODE_HOLD; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); + return 0; +} + +static void fu740_spi_release_bus(const struct spi_slave *slave) +{ + struct fu740_spi_ctrl *spictrl = fu740_spi_ctrls[slave->bus]; + union fu740_spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU740_SPI_CSMODE_OFF; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); +} + +// reset spi flash chip +static void fu740_spi_reset(volatile struct fu740_spi_ctrl *spictrl_reg) { + fu740_spi_tx(spictrl_reg, 0x66); + fu740_spi_tx(spictrl_reg, 0x99); +} + +// setup the ffmt (SPI flash instruction format) register +__maybe_unused static int fu740_spi_setup_ffmt(volatile struct fu740_spi_ctrl *spictrl_reg, + const struct fu740_spi_config *config) +{ + //union fu740_spi_reg_fctrl fctrl; + union fu740_spi_reg_ffmt ffmt; + + printk(BIOS_DEBUG, "config->data_proto: %d, config->cmd_code: %d\n", + config->ffmt_config.data_proto, + config->ffmt_config.cmd_code); + + //TODO test without this here + fu740_spi_reset(spictrl_reg); + + ffmt.raw_bits = 0; + ffmt.cmd_en = 1; // enable sending of command + ffmt.addr_len = 3; // number of address bytes (0-4) + ffmt.pad_cnt = 0; // number of dummy cycles TODO maybe not working + ffmt.cmd_proto = FU740_SPI_PROTO_S; // protocol for transmitting command + ffmt.addr_proto = FU740_SPI_PROTO_S; // protocol for transmitting address and padding + ffmt.data_proto = config->ffmt_config.data_proto; // protocol for receiving data bytes + ffmt.cmd_code = config->ffmt_config.cmd_code; // value of command byte + ffmt.pad_code = 0; // First 8 bits to transmit during dummy cycles + write32(&spictrl_reg->ffmt.raw_bits, ffmt.raw_bits); + + // enable direct memory-mapped spi flash mode + //TODO put this in the mainboard code + //fctrl.raw_bits = 0; + //fctrl.en = 1; + //write32(&spictrl_reg->fctrl.raw_bits, fctrl.raw_bits); + + return 0; +} + +int fu740_spi_setup(const struct spi_slave *slave) { //, struct fu740_spi_ctrl *spictrl_reg, struct fu740_spi_config *config) { + + //union fu740_spi_reg_sckmode sckmode; + union fu740_spi_reg_csmode csmode; + //union fu740_spi_reg_fmt fmt; + union fu740_spi_reg_fctrl fctrl; + + struct fu740_spi_ctrl *spictrl_reg = fu740_spi_ctrls[slave->bus]; + struct fu740_spi_config *config = &fu740_spi_configs[slave->bus]; + + if ((config->pha > 1) + || (config->pol > 1) + || (config->fmt_config.protocol > 2) + || (config->fmt_config.endianness > 1) + || (config->fmt_config.bits_per_frame > 8)) + return -1; + + write32(&spictrl_reg->sckdiv, fu740_spi_min_clk_divisor(clock_get_pclk(), config->freq)); + + /* disable direct memory-mapped spi flash mode */ + //TODO test if we need to disable it before changing the settings + fctrl.raw_bits = 0; + fctrl.en = 0; + write32(&spictrl_reg->fctrl.raw_bits, fctrl.raw_bits); + + //sckmode.raw_bits = 0; + //sckmode.pha = 0; + //sckmode.pol = 0; + //write32(&spictrl_reg->sckmode.raw_bits, sckmode.raw_bits); + + //write32(&spictrl_reg->csdef, 0xffffffff); + + //csmode.raw_bits = 0; + //csmode.mode = FU740_SPI_CSMODE_AUTO; + //write32(&spictrl_reg->csmode.raw_bits, csmode.raw_bits); + + //fmt.raw_bits = 0; + //fmt.proto = 0; + //fmt.endian = 0; + //fmt.dir = 1; + //fmt.len = 8; + //write32(&spictrl_reg->fmt.raw_bits, fmt.raw_bits); + + //fu740_spi_setup_ffmt(spictrl_reg, config); + + csmode.raw_bits = 0; + csmode.mode = FU740_SPI_CSMODE_HOLD; + write32(&spictrl_reg->csmode.raw_bits, csmode.raw_bits); + char din[10]; + char dout[10] = { 0x66 }; + printk(BIOS_DEBUG, "%s 0\n", __func__); + slave->ctrlr->xfer(slave, dout, 1, din, 0); + printk(BIOS_DEBUG, "%s 1\n", __func__); + dout[0] = 0x99; + slave->ctrlr->xfer(slave, dout, 1, din, 0); + printk(BIOS_DEBUG, "%s 2\n", __func__); + int addr = 0x200; + dout[0] = 0x03; + dout[1] = (addr >> 16) & 0xFF; + dout[2] = (addr >> 8) & 0xFF; + dout[3] = addr & 0xFF; + slave->ctrlr->xfer(slave, dout, 4, din, 10); + printk(BIOS_DEBUG, "%s 3\n", __func__); + csmode.mode = FU740_SPI_CSMODE_AUTO; + write32(&spictrl_reg->csmode.raw_bits, csmode.raw_bits); + din[9] = 0; + printk(BIOS_DEBUG, "%s 4\n", __func__); + hexdump(din, 10); + return 0; +} + +struct spi_ctrlr fu740_spi_ctrlr = { + .xfer = fu740_spi_xfer, + .setup = fu740_spi_setup, + .claim_bus = fu740_spi_claim_bus, + .release_bus = fu740_spi_release_bus, + .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, //TODO +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .bus_start = 0, + .bus_end = 2, + .ctrlr = &fu740_spi_ctrlr, + } +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + diff --git a/src/soc/sifive/fu740/spi_internal.h b/src/soc/sifive/fu740/spi_internal.h new file mode 100644 index 0000000..4cc2861 --- /dev/null +++ b/src/soc/sifive/fu740/spi_internal.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ + +#include <stdint.h> + +#define _ASSERT_SIZEOF(type, size) _Static_assert( \ + sizeof(type) == (size), \ + #type " must be " #size " bytes wide") + +// Chip Select Mode Register (csmode) + +#define FU740_SPI_CSMODE_AUTO 0 +#define FU740_SPI_CSMODE_HOLD 2 +#define FU740_SPI_CSMODE_OFF 3 + +union fu740_spi_reg_sckmode { + struct { + uint32_t pha : 1; + uint32_t pol : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_sckmode, 4); + +union fu740_spi_reg_csmode { + struct { + uint32_t mode : 2; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_csmode, 4); + +union fu740_spi_reg_delay0 { + struct { + uint32_t cssck : 8; + uint32_t reserved0 : 8; + uint32_t sckcs : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_delay0, 4); + +union fu740_spi_reg_delay1 { + struct { + uint32_t intercs : 8; + uint32_t reserved0 : 8; + uint32_t interxfr : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_delay1, 4); + +union fu740_spi_reg_fmt { + struct { + uint32_t proto : 2; + uint32_t endian : 1; + uint32_t dir : 1; + uint32_t reserved0 : 12; + uint32_t len : 4; + uint32_t reserved1 : 12; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_fmt, 4); + +union fu740_spi_reg_txdata { + struct { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t full : 1; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_txdata, 4); + +union fu740_spi_reg_rxdata { + struct { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t empty : 1; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_rxdata, 4); + +union fu740_spi_reg_txmark { + struct { + uint32_t txmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_txmark, 4); + +union fu740_spi_reg_rxmark { + struct { + uint32_t rxmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_rxmark, 4); + +union fu740_spi_reg_fctrl { + struct { + uint32_t en : 1; + uint32_t reserved : 31; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_fctrl, 4); + +union fu740_spi_reg_ffmt { + struct { + uint32_t cmd_en : 1; + uint32_t addr_len : 3; + uint32_t pad_cnt : 4; + uint32_t cmd_proto : 2; + uint32_t addr_proto : 2; + uint32_t data_proto : 2; + uint32_t reserved : 2; + uint32_t cmd_code : 8; + uint32_t pad_code : 8; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_ffmt, 4); + +union fu740_spi_reg_ie { + struct { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +}; + +union fu740_spi_reg_ip { + struct { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +}; +_ASSERT_SIZEOF(union fu740_spi_reg_ie, 4); +_ASSERT_SIZEOF(union fu740_spi_reg_ip, 4); + +#undef _ASSERT_SIZEOF + +/** + * SPI control register memory map. + * + * All functions take a pointer to a SPI device's control registers. + */ +struct fu740_spi_ctrl { + uint32_t sckdiv; + union fu740_spi_reg_sckmode sckmode; + uint32_t reserved08; + uint32_t reserved0c; + + uint32_t csid; + uint32_t csdef; + union fu740_spi_reg_csmode csmode; + uint32_t reserved1c; + + uint32_t reserved20; + uint32_t reserved24; + union fu740_spi_reg_delay0 delay0; + union fu740_spi_reg_delay1 delay1; + + uint32_t reserved30; + uint32_t reserved34; + uint32_t reserved38; + uint32_t reserved3c; + + union fu740_spi_reg_fmt fmt; + uint32_t reserved44; + union fu740_spi_reg_txdata txdata; + union fu740_spi_reg_rxdata rxdata; + + union fu740_spi_reg_txmark txmark; + union fu740_spi_reg_rxmark rxmark; + uint32_t reserved58; + uint32_t reserved5c; + + union fu740_spi_reg_fctrl fctrl; + union fu740_spi_reg_ffmt ffmt; + uint32_t reserved68; + uint32_t reserved6c; + + union fu740_spi_reg_ie ie; + union fu740_spi_reg_ip ip; +}; + +/** + * Get smallest clock divisor that divides input_khz to a quotient less than or + * equal to max_target_khz; + */ +static inline unsigned int +fu740_spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz) +{ + // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1 + // + // The nearest integer solution for div requires rounding up as to not + // exceed max_target_khz. + // + // div = ceil(f_in / (2*f_sck)) - 1 + // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1 + // + // This should not overflow as long as (f_in - 1 + 2*f_sck) does not + // exceed 2^32 - 1, which is unlikely since we represent frequencies + // in kHz. + unsigned int quotient = + (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz); + // Avoid underflow + if (quotient == 0) + return 0; + return quotient - 1; +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ */ diff --git a/src/soc/sifive/fu740/uart.c b/src/soc/sifive/fu740/uart.c new file mode 100644 index 0000000..94a6d2d --- /dev/null +++ b/src/soc/sifive/fu740/uart.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <console/uart.h> +#include <commonlib/bsd/helpers.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + if (idx < 2) + return FU740_UART(idx); + else + return 0; +} + +unsigned int uart_platform_refclk(void) +{ + // peripheral clock is attached to UART subsystem + return clock_get_pclk(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibae3b8f1a534c4a5a8b26e723be7d59a92f788bf Gerrit-Change-Number: 79953 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: arch/riscv/Makefile.inc: Fix OpenSBI compilation
by Maximilian Brune (Code Review) 14 Jan '24

14 Jan '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79952?usp=email ) Change subject: arch/riscv/Makefile.inc: Fix OpenSBI compilation ...................................................................... arch/riscv/Makefile.inc: Fix OpenSBI compilation 1. romstage.S should only be included if we have a separate romstage 2. FW_JUMP and FW_DYNAMIC are opposing options and we only support FW_DYNAMIC Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8 --- M src/arch/riscv/Makefile.inc 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/79952/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index bbd3959..4438d49 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,7 +96,9 @@ ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) +ifeq ($(CONFIG_SEPARATE_ROMSTAGE),y) romstage-y += romstage.S +endif # Build the romstage @@ -157,16 +159,15 @@ mkdir -p $(OPENSBI_BUILD) $(MAKE) \ -C "$(OPENSBI_SOURCE)" \ - CC="$(GCC_ramstage) -fno-builtin" \ + CC="$(CC_ramstage) -fno-builtin" \ LD="$(LD_ramstage)" \ OBJCOPY="$(OBJCOPY_ramstage)" \ AR="$(AR_ramstage)" \ PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \ O="$(OPENSBI_BUILD)" \ - FW_JUMP=y \ + FW_JUMP=n \ FW_DYNAMIC=y \ FW_PAYLOAD=n \ - FW_PAYLOAD_OFFSET=0 \ FW_TEXT_START=$(CONFIG_OPENSBI_TEXT_START) $(OPENSBI): $(OPENSBI_TARGET) -- To view, visit https://review.coreboot.org/c/coreboot/+/79952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8 Gerrit-Change-Number: 79952 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mainboard: Drop redundant PciRpEnable from devicetrees
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Angel Pons, Christian Walter, Erik van den Bogaert, Felix Singer, Frans Hendriks, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nicholas Sudsgaard, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford, Werner Zeh. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79935?usp=email ) Change subject: mainboard: Drop redundant PciRpEnable from devicetrees ...................................................................... Patch Set 5: (3 comments) Patchset: PS4: > The patch still needs to be splitted up into the patches for each platform. There's already a comment open for that. > Please provide a single command for each platform in order to make that reproducible. Could be done with find and sed. It's not this easy because there are comments to be altered/moved, override tree entries to be added etc. > > Also, I would like to make sure that the devicetree configuration matches the configuration of the options. The devicetree reference names should help with that, but the conversion is still WIP for Skylake and Cannonlake. That's what is to be reviewed in general. PS4: > It still complains about volteer/variants/voema, but that looks more […] Turns out there are special rules when a device contains fw-config `probe' statements. I've fixed that but am unsure if the override device is necessary at all. File src/mainboard/google/volteer/variants/voema/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79935/comment/bb514556_9c22d97e : PS5, Line 106: # the same device if it has the same probes: Nick, could you check if overriding this device to `off` would be necessary? With this patch train, FSP would be configured properly if the device is assumed off, which might already be the case on Voema due to the probes. -- To view, visit https://review.coreboot.org/c/coreboot/+/79935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9641a1ed241084f37089094b2392c29e2ac0fd95 Gerrit-Change-Number: 79935 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 14 Jan 2024 15:50:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mainboard: Drop redundant PciRpEnable from devicetrees
by Nico Huber (Code Review) 14 Jan '24

14 Jan '24

Attention is currently required from: Angel Pons, Christian Walter, Erik van den Bogaert, Frans Hendriks, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nicholas Sudsgaard, Nick Vaccaro, Nico Huber, Patrick Rudolph, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford, Werner Zeh. Nico Huber has uploaded a new patch set (#5) to the change originally created by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/79935?usp=email ) Change subject: mainboard: Drop redundant PciRpEnable from devicetrees ...................................................................... mainboard: Drop redundant PciRpEnable from devicetrees This is the dirty work of the proposed changes: https://review.coreboot.org/c/coreboot/+/79921 (and related changes) This is still not complete, as I was not able to change some configurations. Specifically, in intel/coffeelake_rvp/variants, as I do not know the PCIe addresses of some of the enabled root ports. I tried to be careful, but I cannot guarantee that I did not mess up any configurations. I would appreciate anyone who can put some time into double-checking these changes. Change-Id: I9641a1ed241084f37089094b2392c29e2ac0fd95 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/boxy/overridetree.cb M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb M src/mainboard/google/dedede/variants/dexi/overridetree.cb M src/mainboard/google/dedede/variants/dibbi/overridetree.cb M src/mainboard/google/dedede/variants/dita/overridetree.cb M src/mainboard/google/dedede/variants/sasuke/overridetree.cb M src/mainboard/google/dedede/variants/sasukette/overridetree.cb M src/mainboard/google/dedede/variants/storo/overridetree.cb M src/mainboard/google/dedede/variants/taranza/overridetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb 101 files changed, 65 insertions(+), 464 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/79935/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9641a1ed241084f37089094b2392c29e2ac0fd95 Gerrit-Change-Number: 79935 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2024