coreboot-gerrit January 2024

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[S] Change in coreboot[main]: mb/lenovo/t430: Convert remaining PCI numbers into reference names
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79941?usp=email ) Change subject: mb/lenovo/t430: Convert remaining PCI numbers into reference names ...................................................................... mb/lenovo/t430: Convert remaining PCI numbers into reference names Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79941 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb 2 files changed, 7 insertions(+), 7 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index 698460b..2515150 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -4,8 +4,8 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable hotplug on Port 5 for Thunderbolt controller register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" - device pci 1c.4 on end # PCIe Port #5 Thunderbolt controller - device pci 1f.0 on + device ref pcie_rp5 on end # PCIe Port #5 Thunderbolt controller + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "has_bdc_detection" = "1" diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index fcd137f..3e13627 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -15,7 +15,7 @@ device domain 0 on subsystemid 0x17aa 0x2208 inherit - device pci 01.0 off end # PCIe Bridge for discrete graphics + device ref peg10 off end # PCIe Bridge for discrete graphics chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock) @@ -23,15 +23,15 @@ # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "0" device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.2 off end # PCIe Port #3 - device pci 1f.0 on + device ref pcie_rp3 off end # PCIe Port #3 + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config0" = "0xa6" @@ -42,7 +42,7 @@ register "has_bdc_detection" = "0" end end # LPC Controller - device pci 1f.6 off end # Thermal + device ref thermal off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79941?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e Gerrit-Change-Number: 79941 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/lenovo/t530: Convert remaining PCI numbers into reference names
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79937?usp=email ) Change subject: mb/lenovo/t530: Convert remaining PCI numbers into reference names ...................................................................... mb/lenovo/t530: Convert remaining PCI numbers into reference names Change-Id: Ied9f37355432d58f83cb8453111a261c4eddc14a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79937 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t530/variants/t530/overridetree.cb M src/mainboard/lenovo/t530/variants/w530/overridetree.cb 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index 98551ac..fda8aef 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -2,7 +2,7 @@ register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - device pci 1f.0 on # PCI-LPC bridge + device ref lpc on # PCI-LPC bridge chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "has_wwan_detection" = "1" diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 77b75fd..2029dc3 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -1,26 +1,26 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x17aa 0x21f5 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - device pci 16.3 on end # Management Engine KT - device pci 1c.0 on # PCIe Port #1 + device ref me_kt on end # Management Engine KT + device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x83" register "sdwppol" = "1" device pci 00.0 on end # Ricoh SD card reader end end - device pci 1f.0 on # PCI-LPC bridge + device ref lpc on # PCI-LPC bridge chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config1" = "0x01" register "config3" = "0xe2" end end - device pci 1f.6 off end # Thermal + device ref thermal off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied9f37355432d58f83cb8453111a261c4eddc14a Gerrit-Change-Number: 79937 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/lenovo/x220: Remove superfluous comments related to PCI devices
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79940?usp=email ) Change subject: mb/lenovo/x220: Remove superfluous comments related to PCI devices ...................................................................... mb/lenovo/x220: Remove superfluous comments related to PCI devices Since all devicetrees from lenovo/x220 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/variants/x1/overridetree.cb M src/mainboard/lenovo/x220/variants/x220/overridetree.cb 3 files changed, 33 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 866d6c3..233f690 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -38,9 +38,9 @@ device domain 0 on subsystemid 0x17aa 0x21db inherit - device ref host_bridge on end # host bridge - device ref peg10 off end # PCIe Bridge for discrete graphics - device ref igd on end # vga controller + device ref host_bridge on end + device ref peg10 off end + device ref igd on end chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -68,37 +68,37 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end device ref gbe on subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp2 on # PCIe Port #2 (wlan) + end + device ref ehci2 on end + device ref hda on end + device ref pcie_rp1 off end + device ref pcie_rp2 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort" "WIFI" "SlotDataBusWidth1X" end - device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp3 off end device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 + end device ref pcie_rp5 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end - end # PCIe Port #5 (SD) - device ref pcie_rp6 off end # PCIe Port #6 - device ref pcie_rp7 on end # PCIe Port #7 Optional XHCI controller - device ref pcie_rp8 off end # PCIe Port #8 - device ref ehci1 on end # USB2 EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on #LPC bridge + end + device ref pcie_rp6 off end + device ref pcie_rp7 on end # Optional XHCI controller + device ref pcie_rp8 off end + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "true" @@ -149,8 +149,8 @@ register "wwan_gpio_num" = "70" register "wwan_gpio_lvl" = "0" end - end # LPC bridge - device ref sata1 on end # SATA Controller 1 + end + device ref sata1 on end device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c @@ -163,9 +163,9 @@ device i2c 5e on end device i2c 5f on end end - end # SMBus - device ref sata2 off end # SATA Controller 2 - device ref thermal on end # Thermal + end + device ref sata2 off end + device ref thermal on end end end end diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index 2defac8..bf88150 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -21,10 +21,10 @@ # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp3 off end # PCIe Port #3 - device ref pcie_rp4 off end # PCIe Port #4 - device ref lpc on #LPC bridge + device ref pcie_rp1 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config2" = "0xe0" @@ -36,7 +36,7 @@ register "event5_enable" = "0x3c" register "evente_enable" = "0x3d" end - end # LPC bridge + end end end end diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index 9325480..b9caa25 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,13 +1,13 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device ref lpc on #LPC bridge + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "eventa_enable" = "0x01" register "eventb_enable" = "0xf0" end - end # LPC bridge + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79940?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701 Gerrit-Change-Number: 79940 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/lenovo/x220: Convert remaining PCI numbers into reference names
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79939?usp=email ) Change subject: mb/lenovo/x220: Convert remaining PCI numbers into reference names ...................................................................... mb/lenovo/x220: Convert remaining PCI numbers into reference names Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79939 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/x220/variants/x1/overridetree.cb M src/mainboard/lenovo/x220/variants/x220/overridetree.cb 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index d236139..2defac8 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -21,10 +21,10 @@ # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1f.0 on #LPC bridge + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref lpc on #LPC bridge chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config2" = "0xe0" diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index 8e939fd..9325480 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,7 +1,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device pci 1f.0 on #LPC bridge + device ref lpc on #LPC bridge chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "eventa_enable" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/79939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f Gerrit-Change-Number: 79939 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/asrock/b75m-itx: Use chipset dt reference names
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79971?usp=email ) Change subject: mb/asrock/b75m-itx: Use chipset dt reference names ...................................................................... mb/asrock/b75m-itx: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79971 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kevin Keijzer <kevin(a)quietlife.nl> Reviewed-by: Janik Haag Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asrock/b75m-itx/devicetree.cb 1 file changed, 26 insertions(+), 26 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Janik Haag: Looks good to me, but someone else must approve Kevin Keijzer: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 6d4ca2d..59645f0 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -7,13 +7,13 @@ register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on - device pci 00.0 on + device ref host_bridge on subsystemid 0x1849 0x0150 end - device pci 01.0 on + device ref peg10 on subsystemid 0x1849 0x0151 end - device pci 02.0 on + device ref igd on subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x @@ -28,42 +28,42 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on subsystemid 0x1849 0x1e31 end - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on subsystemid 0x1849 0x1e3a end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on subsystemid 0x1849 0x1e2d end - device pci 1b.0 on # HDA Audio controller + device ref hda on subsystemid 0x1849 0x8892 end - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on subsystemid 0x1849 0x1e10 end - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on # PCIe Port #4, Realtek PCIe GbE Controller + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 on # Realtek PCIe GbE Controller subsystemid 0x1849 0x1e16 device pci 00.0 on end # PCI 10ec:8168 end - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on # PCIe Port #6 + device ref pcie_rp5 off end + device ref pcie_rp6 on subsystemid 0x1849 0x1e1a end - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref ehci1 on subsystemid 0x1849 0x1e26 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_bridge off end + device ref lpc on subsystemid 0x1849 0x1e49 chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -117,14 +117,14 @@ end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on subsystemid 0x1849 0x1e02 end - device pci 1f.3 on # SMBus + device ref smbus on subsystemid 0x1849 0x1e22 end - device pci 1f.5 off end - device pci 1f.6 off end # Thermal + device ref sata2 off end + device ref thermal off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Gerrit-Change-Number: 79971 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Janik Haag Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/asus/h61-series: Remove superfluous comments related to PCI devices
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79970?usp=email ) Change subject: mb/asus/h61-series: Remove superfluous comments related to PCI devices ...................................................................... mb/asus/h61-series: Remove superfluous comments related to PCI devices Since all devicetrees from asus/h61_series are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79970 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb 6 files changed, 55 insertions(+), 55 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index cde0431..7f37acc 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -3,39 +3,39 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on - device ref host_bridge on end # Host bridge - device ref peg10 on end # PEG - device ref igd on end # iGPU + device ref host_bridge on end + device ref peg10 on end + device ref igd on end chip southbridge/intel/bd82x6x register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device ref mei1 on end # MEI #1 - device ref mei2 off end # MEI #2 - device ref me_ide_r off end # ME IDE-R - device ref me_kt off end # ME KT - device ref gbe off end # Intel GbE - device ref ehci2 on end # EHCI #2 - device ref hda on end # HD Audio + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on end + device ref hda on end - device ref pcie_rp1 off end # RP #1 - device ref pcie_rp2 off end # RP #2 - device ref pcie_rp3 off end # RP #3 - device ref pcie_rp4 off end # RP #4 - device ref pcie_rp5 off end # RP #5 - device ref pcie_rp6 off end # RP #6 - device ref pcie_rp7 off end # RP #7 - device ref pcie_rp8 off end # RP #8 + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref ehci1 on end # EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on end # LPC bridge - device ref sata1 on end # SATA (AHCI) - device ref smbus on end # SMBus - device ref sata2 off end # SATA (Legacy) - device ref thermal off end # Thermal + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on end + device ref sata1 on end # SATA (AHCI) + device ref smbus on end + device ref sata2 off end # SATA (Legacy) + device ref thermal off end end end end diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 066136cb..8558510 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,21 +5,21 @@ subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device ref hda on # High Definition Audio controller + device ref hda on subsystemid 0x1043 0x8445 end - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp2 off end # PCIe Port #2 - device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end device ref pcie_rp4 on end # PCIe x1 Slot 1 PCIE_1 device ref pcie_rp5 on end # PCIe x1 Slot 2 PCIE_2 device ref pcie_rp6 on # Realtek Gigabit NIC device pci 00.0 on end end - device ref pcie_rp7 off end # PCIe Port #7 - device ref pcie_rp8 off end # PCIe Port #8 + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge PCI-LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb index c4ff6b0..7612c55 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb @@ -6,7 +6,7 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM - device ref hda on # HD audio controller + device ref hda on subsystemid 0x1043 0x8445 end device ref pcie_rp1 on end # PCIe 1x slot (PCIEX1_1) @@ -18,13 +18,13 @@ device pci 00.0 on end end end - device ref pcie_rp4 off end # Unused PCIe port + device ref pcie_rp4 off end device ref pcie_rp5 on end # PCIe 1x slot (PCIEX1_3) - device ref pcie_rp6 off end # Unused PCIe port - device ref pcie_rp7 off end # Unused PCIe port - device ref pcie_rp8 off end # Unused PCIe port + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb index fc3313e..1aa08f26 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb @@ -6,16 +6,16 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device ref pcie_rp1 on end # RP #1 - device ref pcie_rp2 off end # RP #2 - device ref pcie_rp3 off end # RP #3 - device ref pcie_rp4 on end # RP #4: PCIEX1_1 - device ref pcie_rp5 on end # RP #5: PCIEX1_2 - device ref pcie_rp6 on end # RP #6: RTL8111 GbE NIC - device ref pcie_rp7 off end # RP #7 - device ref pcie_rp8 off end # RP #8 + device ref pcie_rp1 on end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 on end # PCIEX1_1 + device ref pcie_rp5 on end # PCIEX1_2 + device ref pcie_rp6 on end # RTL8111 GbE NIC + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb index 026bd81..59c2a14 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb @@ -7,7 +7,7 @@ device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) - device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" @@ -17,10 +17,10 @@ device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller device ref pcie_rp5 on end # PCIe x1 Port, x16 size (PCIEX16_2) device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller - device ref pcie_rp7 off end # Unused PCIe Port - device ref pcie_rp8 off end # Unused PCIe Port + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref lpc on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 9db03fc..ef22ce5 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -8,7 +8,7 @@ device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) - device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" @@ -16,10 +16,10 @@ end end device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller - device ref pcie_rp5 on end # RP #6: ASM1083 PCI Bridge + device ref pcie_rp5 on end # ASM1083 PCI Bridge device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller - device ref pcie_rp7 off end # Unused PCIe Port - device ref pcie_rp8 off end # Unused PCIe Port + device ref pcie_rp7 off end + device ref pcie_rp8 off end device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 -- To view, visit https://review.coreboot.org/c/coreboot/+/79970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Gerrit-Change-Number: 79970 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/asus/h61-series: Convert remaining PCI numbers into reference names
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79969?usp=email ) Change subject: mb/asus/h61-series: Convert remaining PCI numbers into reference names ...................................................................... mb/asus/h61-series: Convert remaining PCI numbers into reference names Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb 5 files changed, 47 insertions(+), 47 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index cb30fc3..066136cb 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,21 +5,21 @@ subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1b.0 on # High Definition Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x1043 0x8445 end - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe x1 Slot 1 PCIE_1 - device pci 1c.4 on end # PCIe x1 Slot 2 PCIE_2 - device pci 1c.5 on # Realtek Gigabit NIC + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe x1 Slot 1 PCIE_1 + device ref pcie_rp5 on end # PCIe x1 Slot 2 PCIE_2 + device ref pcie_rp6 on # Realtek Gigabit NIC device pci 00.0 on end end - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb index aa9f8c8..c4ff6b0 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb @@ -6,25 +6,25 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM - device pci 1b.0 on # HD audio controller + device ref hda on # HD audio controller subsystemid 0x1043 0x8445 end - device pci 1c.0 on end # PCIe 1x slot (PCIEX1_1) - device pci 1c.1 on end # PCIe 1x slot (PCIEX1_2) - device pci 1c.2 on # Realtek Gigabit Ethernet + device ref pcie_rp1 on end # PCIe 1x slot (PCIEX1_1) + device ref pcie_rp2 on end # PCIe 1x slot (PCIEX1_2) + device ref pcie_rp3 on # Realtek Gigabit Ethernet subsystemid 0x1043 0x8432 chip drivers/net register "customized_leds" = "0x00f6" device pci 00.0 on end end end - device pci 1c.3 off end # Unused PCIe port - device pci 1c.4 on end # PCIe 1x slot (PCIEX1_3) - device pci 1c.5 off end # Unused PCIe port - device pci 1c.6 off end # Unused PCIe port - device pci 1c.7 off end # Unused PCIe port + device ref pcie_rp4 off end # Unused PCIe port + device ref pcie_rp5 on end # PCIe 1x slot (PCIEX1_3) + device ref pcie_rp6 off end # Unused PCIe port + device ref pcie_rp7 off end # Unused PCIe port + device ref pcie_rp8 off end # Unused PCIe port - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb index 5d9635c..fc3313e 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb @@ -6,16 +6,16 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 on end # RP #4: PCIEX1_1 - device pci 1c.4 on end # RP #5: PCIEX1_2 - device pci 1c.5 on end # RP #6: RTL8111 GbE NIC - device pci 1c.6 off end # RP #7 - device pci 1c.7 off end # RP #8 + device ref pcie_rp1 on end # RP #1 + device ref pcie_rp2 off end # RP #2 + device ref pcie_rp3 off end # RP #3 + device ref pcie_rp4 on end # RP #4: PCIEX1_1 + device ref pcie_rp5 on end # RP #5: PCIEX1_2 + device ref pcie_rp6 on end # RP #6: RTL8111 GbE NIC + device ref pcie_rp7 off end # RP #7 + device ref pcie_rp8 off end # RP #8 - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb index d726131..026bd81 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb @@ -5,22 +5,22 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM - device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) - device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) + device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" device pci 00.0 on end end end - device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller - device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) - device pci 1c.5 on end # ASMedia ASM1062 SATA Controller - device pci 1c.6 off end # Unused PCIe Port - device pci 1c.7 off end # Unused PCIe Port + device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller + device ref pcie_rp5 on end # PCIe x1 Port, x16 size (PCIEX16_2) + device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller + device ref pcie_rp7 off end # Unused PCIe Port + device ref pcie_rp8 off end # Unused PCIe Port - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 1b78b9b..9db03fc 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -6,22 +6,22 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM - device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) - device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) + device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) + device ref pcie_rp3 on # Realtek RTL8111E Ethernet Controller chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" device pci 00.0 on end end end - device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller - device pci 1c.4 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.5 on end # ASMedia ASM1062 SATA Controller - device pci 1c.6 off end # Unused PCIe Port - device pci 1c.7 off end # Unused PCIe Port + device ref pcie_rp4 on end # ASMedia ASM1042 USB3 Controller + device ref pcie_rp5 on end # RP #6: ASM1083 PCI Bridge + device ref pcie_rp6 on end # ASMedia ASM1062 SATA Controller + device ref pcie_rp7 off end # Unused PCIe Port + device ref pcie_rp8 off end # Unused PCIe Port - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port -- To view, visit https://review.coreboot.org/c/coreboot/+/79969?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Gerrit-Change-Number: 79969 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79968?usp=email ) Change subject: mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt ...................................................................... mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt Since all devicetrees from asus/maximus_iv_gene-z are using the reference names for PCI devices, remove the equivalent comments documenting their function. Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79968 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb 1 file changed, 25 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 146ee6c..2642fbd 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -5,9 +5,9 @@ device domain 0 on subsystemid 0x1043 0x844d inherit - device ref host_bridge on end # Host bridge - device ref peg10 on end # PCIe bridge for discrete graphics - device ref igd on end # VGA controller + device ref host_bridge on end + device ref peg10 on end # discrete graphics + device ref igd on end chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM @@ -15,28 +15,28 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT - device ref gbe on # Intel Gigabit Ethernet + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe on subsystemid 0x1043 0x849c end - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on # HD audio controller + device ref ehci2 on end + device ref hda on subsystemid 0x1043 0x84dc end - device ref pcie_rp1 on end # PCIe port #1 - device ref pcie_rp2 off end # PCIe port #2 - device ref pcie_rp3 off end # PCIe port #3 - device ref pcie_rp4 off end # PCIe port #4 - device ref pcie_rp5 on end # PCIe port #5 - device ref pcie_rp6 on end # PCIe port #6 - device ref pcie_rp7 on end # PCIe port #7 - device ref pcie_rp8 off end # PCIe port #8 - device ref ehci1 on end # USB2 EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge + device ref pcie_rp1 on end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 off end + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel @@ -75,10 +75,10 @@ device pnp 2e.17 off end # GPIOA end end - device ref sata1 on end # SATA controller 1 - device ref smbus on end # SMBus - device ref sata2 off end # SATA controller 2 - device ref thermal off end # Thermal + device ref sata1 on end + device ref smbus on end + device ref sata2 off end + device ref thermal off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Gerrit-Change-Number: 79968 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/asus/p8x7x-series: Use chipset dt reference names
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79967?usp=email ) Change subject: mb/asus/p8x7x-series: Use chipset dt reference names ...................................................................... mb/asus/p8x7x-series: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79967 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 7 files changed, 83 insertions(+), 84 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index cd4336f..192b4bd 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -21,9 +21,9 @@ # from runtime code) device domain 0 on - device ref host_bridge on end # Host bridge - device ref peg10 on end # PCIEX16_1 - device ref igd on end # iGPU + device ref host_bridge on end + device ref peg10 on end # PCIEX16_1 + device ref igd on end chip southbridge/intel/bd82x6x register "sata_interface_speed_support" = "0x3" @@ -34,32 +34,31 @@ register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device ref xhci on end # xHCI - device ref mei1 on end # MEI #1 - device ref mei2 off end # MEI #2 - device ref me_ide_r off end # ME IDE-R - device ref me_kt off end # ME KT - device ref gbe off end # Intel GbE - device ref ehci2 on end # EHCI #2 - device ref hda on end # HD Audio + device ref xhci on end + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on end + device ref hda on end - device ref pcie_rp1 off end # RP #1 - device ref pcie_rp2 off end # RP #2 - device ref pcie_rp3 off end # RP #3 - device ref pcie_rp4 off end # RP #4 - device ref pcie_rp5 off end # RP #5 - device ref pcie_rp6 off end # RP #6 - device ref pcie_rp7 off end # RP #7 - device ref pcie_rp8 off end # RP #8 + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end - device ref ehci1 on end # EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge - end - device ref sata1 on end # SATA (AHCI) - device ref smbus on end # SMBus - device ref sata2 off end # SATA (Legacy) - device ref thermal off end # Thermal + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on end + device ref sata1 on end # SATA (AHCI) + device ref smbus on end + device ref sata2 off end # SATA (Legacy) + device ref thermal off end end end end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 4de539b..4b7bb1c 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -2,21 +2,21 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 01.1 on end # PCIEX16_2 (electrical x8) - device pci 06.0 on end # PCIEX16_3 (electrical x4) + device ref peg11 on end # PCIEX16_2 (electrical x8) + device ref peg60 on end # PCIEX16_3 (electrical x4) subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1: PCIEX16_4 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: PCIEX1_1 - device pci 1c.5 on end # RP #6: 82574 GbE #1 - device pci 1c.6 on end # RP #7: 82574 GbE #2 - device pci 1c.7 off end # RP #8: - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # PCIEX1_1 + device ref pcie_rp6 on end # 82574 GbE #1 + device ref pcie_rp7 on end # 82574 GbE #2 + device ref pcie_rp8 off end + device ref pci_bridge on end + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index f20b49c..dbf1f35 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -5,16 +5,16 @@ subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: AR8161 GbE NIC - device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.6 on end # RP #7: PCIEX1_1 - device pci 1c.7 on end # RP #8: PCIEX1_2 + device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # AR8161 GbE NIC + device ref pcie_rp6 on end # ASM1083 PCI Bridge + device ref pcie_rp7 on end # PCIEX1_1 + device ref pcie_rp8 on end # PCIEX1_2 - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index c9fd784..5d688fd 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -11,18 +11,18 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 (PCIe x1 slot) - device pci 1c.5 on # PCIe Port #6 (RTL8111F GbE NIC) + device ref pcie_rp1 on end # PCIe x4 slot + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # PCIe x1 slot + device ref pcie_rp6 on # RTL8111F GbE NIC subsystemid 0x1849 0x1e1a device pci 00.0 on end # make onboard end - device pci 1c.6 on end # PCIe Port #7 (PCI slot via ASM1083) - device pci 1c.7 off end # PCIe Port #8 - device pci 1f.0 on # LPC bridge + device ref pcie_rp7 on end # PCI slot via ASM1083 + device ref pcie_rp8 off end + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index d7aea49..da34af3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -13,16 +13,16 @@ register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "true" - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 - device pci 1c.1 on end # PCIe Port 2 RTL8111F - device pci 1c.2 off end # PCIe Port 3 unused - device pci 1c.3 off end # PCIe Port 4 unused - device pci 1c.4 off end # PCIe Port 5 unused - device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 - device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA - device pci 1c.7 off end # PCIe Port 8 unused + device ref pcie_rp1 on end # PCIEX_16_3 + device ref pcie_rp2 on end # RTL8111F + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 on end # ASM1042 USB3 + device ref pcie_rp7 on end # ASM1061 eSATA + device ref pcie_rp8 off end - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 off end # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb index 77484c7..043be06 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb @@ -3,19 +3,19 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x84ca inherit - device pci 01.1 on end # PCIEX_16_2 + device ref peg11 on end # PCIEX_16_2 chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x1 or x4) - device pci 1c.1 on end # PCIe Port 2 PCIEX_1_1 - device pci 1c.3 on end # PCIe Port 4 ASM1061 SATA or PCIEX_1_2 - device pci 1c.4 on end # PCIe Port 5 ASM1083 PCI Bridge - device pci 1c.6 on end # PCIe Port 7 Wi-Fi Go! - device pci 1c.7 on end # PCIe Port 8 ASM1042 USB3 + device ref gbe on end + device ref pcie_rp1 on end # PCIEX_16_3 (electrical x1 or x4) + device ref pcie_rp2 on end # PCIEX_1_1 + device ref pcie_rp4 on end # ASM1061 SATA or PCIEX_1_2 + device ref pcie_rp5 on end # ASM1083 PCI Bridge + device ref pcie_rp7 on end # Wi-Fi Go! + device ref pcie_rp8 on end # ASM1042 USB3 - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 6be23fa..0ae41b3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -6,16 +6,16 @@ chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: RTL8111 GbE NIC - device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.6 on end # RP #7: PCIEX1_1 - device pci 1c.7 on end # RP #8: PCIEX1_2 + device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end # RTL8111 GbE NIC + device ref pcie_rp6 on end # ASM1083 PCI Bridge + device ref pcie_rp7 on end # PCIEX1_1 + device ref pcie_rp8 on end # PCIEX1_2 - device pci 1f.0 on # LPC bridge + device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A -- To view, visit https://review.coreboot.org/c/coreboot/+/79967?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Gerrit-Change-Number: 79967 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/lenovo/t520: Remove superfluous comments related to PCI devices
by Felix Singer (Code Review) 14 Jan '24

14 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79966?usp=email ) Change subject: mb/lenovo/t520: Remove superfluous comments related to PCI devices ...................................................................... mb/lenovo/t520: Remove superfluous comments related to PCI devices Since all devicetrees from lenovo/t520 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t520/variants/t520/overridetree.cb M src/mainboard/lenovo/t520/variants/w520/overridetree.cb 3 files changed, 25 insertions(+), 25 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index de59198..a2e12c3 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -18,11 +18,11 @@ device domain 0 on subsystemid 0x17aa 0x21cf inherit - device ref host_bridge on end # host bridge + device ref host_bridge on end device ref peg10 on end # NVIDIA Copcie_rporation GF119M [NVS 4200M] device ref igd on subsystemid 0x17aa 0x21d1 - end # vga controller + end chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -50,27 +50,27 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device ref mei1 on end # Management Engine Interface 1 + device ref mei1 on end device ref mei2 off end device ref me_ide_r off end device ref me_kt off end - device ref gbe on # Intel Gigabit Ethernet + device ref gbe on subsystemid 0x17aa 0x21ce end - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN - device ref pcie_rp3 off end # PCIe Port #3 + device ref ehci2 on end + device ref hda on end + device ref pcie_rp1 off end + device ref pcie_rp2 on end # Integrated Wireless LAN + device ref pcie_rp3 off end device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 Express Card - device ref pcie_rp5 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device ref pcie_rp6 off end # PCIe Port #6 Intel Ethernet PHY - device ref pcie_rp7 off end # PCIe Port #7 - device ref pcie_rp8 off end # PCIe Port #8 - device ref ehci1 on end # USB2 EHCI #1 - device ref lpc on #LPC bridge + end + device ref pcie_rp5 on end # MMC/SDXC + IEEE1394 + device ref pcie_rp6 off end # Intel Ethernet PHY + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref ehci1 on end + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "true" @@ -129,9 +129,9 @@ register "has_thinker1" = "1" end - end # LPC bridge - device ref sata1 on end # SATA Controller 1 - device ref smbus on # SMBUS controller + end + device ref sata1 on end + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -143,9 +143,9 @@ device i2c 5e on end device i2c 5f on end end - end # SMBus - device ref sata2 off end # IDE controller - device ref thermal off end # Thermal controller + end + device ref sata2 off end + device ref thermal off end end end end diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb index b2c2839..52946d1 100644 --- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb @@ -2,14 +2,14 @@ register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device ref lpc on # LPC bridge + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "has_wwan_detection" = "1" register "wwan_gpio_num" = "70" register "wwan_gpio_lvl" = "0" end - end # LPC bridge + end end end end diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb index 84d4dd6..a01784e 100644 --- a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb @@ -2,7 +2,7 @@ register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device ref pcie_rp7 on end # PCIe Port #7 USB 3.0 + device ref pcie_rp7 on end # USB 3.0 end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79966?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7 Gerrit-Change-Number: 79966 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2024