coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify touchscreen enable delay to meet...
by Eric Lai (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Dtrain Hsu, Ian Feng, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79978?usp=email ) Change subject: mb/google/nissa/var/craaskov: Modify touchscreen enable delay to meet spec ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79978/comment/ef05ddf0_5d650a6e : PS1, Line 7: Modify touchscreen enable delay to meet spec nit: Modify ELAN touchscreen enable delay https://review.coreboot.org/c/coreboot/+/79978/comment/bda1d2fd_972032c1 : PS1, Line 9: Modify touchscreen enable_delay to 6ms to meet with spec. please also mention ELAN spec version here. -- To view, visit https://review.coreboot.org/c/coreboot/+/79978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Gerrit-Change-Number: 79978 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 07:00:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify touchscreen enable delay to meet...
by Rex Chou (Code Review) 15 Jan '24

15 Jan '24

Rex Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79978?usp=email ) Change subject: mb/google/nissa/var/craaskov: Modify touchscreen enable delay to meet spec ...................................................................... mb/google/nissa/var/craaskov: Modify touchscreen enable delay to meet spec Modify touchscreen enable_delay to 6ms to meet with spec. BUG=b:318443640 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79978/1 diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index be73526..a070b46 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -317,7 +317,7 @@ register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" + register "generic.enable_delay_ms" = "6" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_delay_ms" = "150" register "generic.stop_off_delay_ms" = "2" -- To view, visit https://review.coreboot.org/c/coreboot/+/79978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Gerrit-Change-Number: 79978 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Re-factor the Memory Setting
by Derek Huang (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Daniel Peng, Karthik Ramasubramanian. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79976?usp=email ) Change subject: mb/google/dedede/var/galtic: Re-factor the Memory Setting ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79976/comment/d82dd6f4_e4db8efd : PS2, Line 7: Re-factor the Memory Setting It looks to me that the CL correct the memory part which was used. There is no change to the memory setting. -- To view, visit https://review.coreboot.org/c/coreboot/+/79976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Gerrit-Change-Number: 79976 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 06:53:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: tree: Refactor region_end() to return last used address of a region
by Werner Zeh (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Jakub Czapiga, Jérémy Compostella, Werner Zeh. Hello Jakub Czapiga, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79977?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: tree: Refactor region_end() to return last used address of a region ...................................................................... tree: Refactor region_end() to return last used address of a region Currently, function region_end() does return the next address after the end of a given region. This is not only confusing (as the next address after a region is not part of this region anymore) but can lead to integer overflow if the region's end reaches SIZE_MAX. This possible overflow can then lead to not catching a region overlap as reported in a bug in [1]. This patch changes now the behavior of region_end() and makes it return the last valid address of a region. In addition, the integer overflow is checked and if it would happen, SIZE_MAX is returned (which truncates the region's end to SIZE_MAX for this corner case). And since region_end() now returns a different address, some unit-tests need adjustments. [1]: https://ticket.coreboot.org/issues/522 Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/spi/winbond.c M src/include/cpu/x86/smm.h M tests/commonlib/region-test.c M util/cbfstool/cse_serger.c 7 files changed, 33 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79977/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79977?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Gerrit-Change-Number: 79977 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: tree: Refactor region_end() to return last used address of a region
by Werner Zeh (Code Review) 15 Jan '24

15 Jan '24

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79977?usp=email ) Change subject: tree: Refactor region_end() to return last used address of a region ...................................................................... tree: Refactor region_end() to return last used address of a region Currently, function region_end() does return the next address after the end of a given region. This is not only confusing (as the next address after a region is not part of this region anymore) but can lead to integer overflow if the region's end reaches SIZE_MAX. This possible overflow can then lead to not catching a region overlap as reported in a bug in [1]. This patch changes now the behavior of region_end() and makes it return the last valid address of a region. In addition, the integer overflow is checked and if it would happen, SIZE_MAX is returned (which truncates the region's end to SIZE_MAX for this corner case). And since region_end() now returns a different address, some unit-tests need adjustments. [1]: https://ticket.coreboot.org/issues/522 Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/spi/winbond.c M src/include/cpu/x86/smm.h M tests/commonlib/region-test.c M util/cbfstool/cse_serger.c 7 files changed, 33 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79977/1 diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 25efcc8..af76026 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -114,13 +114,18 @@ static inline size_t region_end(const struct region *r) { - return region_offset(r) + region_sz(r); + if (region_sz(r) == 0) + return region_offset(r); + else if (((size_t)SIZE_MAX - region_sz(r)) < region_offset(r)) + return (size_t)SIZE_MAX; + else + return region_offset(r) + region_sz(r) - 1; } static inline bool region_overlap(const struct region *r1, const struct region *r2) { - return (region_end(r1) > region_offset(r2)) && - (region_offset(r1) < region_end(r2)); + return (region_end(r1) >= region_offset(r2)) && + (region_offset(r1) <= region_end(r2)); } static inline const struct region *region_device_region( diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 4153f0a..3737234 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -7,6 +7,9 @@ int region_is_subregion(const struct region *p, const struct region *c) { + if ((region_sz(p) == 0) || (region_sz(c) == 0)) + return 0; + if (region_offset(c) < region_offset(p)) return 0; @@ -142,8 +145,12 @@ .size = size, }; - if (!normalize_and_ok(&parent->region, &req)) + if (!normalize_and_ok(&parent->region, &req)) { + /* Make sure there are no random values in child's region. */ + child->region.offset = 0; + child->region.size = 0; return -1; + } /* Keep track of root region device. Note the offsets are relative * to the root device. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index d965593..262bb7b 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -335,8 +335,12 @@ mod_params->cbmemc_size = 0; } - for (int i = 0; i < loader_params->num_cpus; i++) - mod_params->save_state_top[i] = region_end(&cpus[i].ss); + for (int i = 0; i < loader_params->num_cpus; i++) { + mod_params->save_state_top[i] = region_end(&cpus[i].ss) + 1; + if (mod_params->save_state_top[i] < SIZE_MAX) { + mod_params->save_state_top[i]++; + } + } if (CONFIG(RUNTIME_CONFIGURABLE_SMM_LOGLEVEL)) mod_params->smm_log_level = mainboard_set_smm_log_level(); @@ -426,7 +430,8 @@ return -1; const struct region smram = { .offset = smram_base, .size = smram_size }; - const uintptr_t smram_top = region_end(&smram); + const uintptr_t smram_top = region_end(&smram) < SIZE_MAX ? + region_end(&smram) + 1 : region_end(&smram); const size_t stm_size = CONFIG(STM) ? CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE : 0; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 3137bfe..85b3f71 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -503,7 +503,7 @@ int ret; /* Need to touch TOP or BOTTOM */ - if (region_offset(region) != 0 && region_end(region) != flash->size) + if (region_offset(region) != 0 && region_end(region) != flash->size - 1) return -1; params = flash->part; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index dfb27cd..2d33205 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -139,7 +139,10 @@ { const struct region r = {(uintptr_t)ptr, len}; - return smm_region_overlaps_handler(&r); + if (region_sz(r) == 0) + return false; + else + return smm_region_overlaps_handler(&r); } /* SMM Module Loading API */ diff --git a/tests/commonlib/region-test.c b/tests/commonlib/region-test.c index 3280482..528a593 100644 --- a/tests/commonlib/region-test.c +++ b/tests/commonlib/region-test.c @@ -17,7 +17,7 @@ struct region outer = {.offset = VAL(2), .size = VAL(4)}; assert_int_equal(region_offset(&outer), VAL(2)); assert_int_equal(region_sz(&outer), VAL(4)); - assert_int_equal(region_end(&outer), VAL(6)); + assert_int_equal(region_end(&outer), VAL(6)-1); struct region inner = {.offset = VAL(3), .size = VAL(2)}; assert_true(region_is_subregion(&outer, &inner)); @@ -118,7 +118,7 @@ { assert_int_equal(region_device_offset(&mock_rdev), 0); assert_int_equal(region_device_sz(&mock_rdev), ~(size_t)0); - assert_int_equal(region_device_end(&mock_rdev), ~(size_t)0); + assert_int_equal(region_device_end(&mock_rdev), (~(size_t)0) - 1); } /* @@ -254,7 +254,7 @@ assert_int_equal(rdev_chain(&child, &mock_rdev, child_offs, child_size), 0); assert_int_equal(region_device_sz(&child), child_size); assert_int_equal(region_device_offset(&child), child_offs); - assert_int_equal(region_device_end(&child), child_offs + child_size); + assert_int_equal(region_device_end(&child), child_offs + child_size - 1); assert_int_equal(rdev_relative_offset(&mock_rdev, &child), child_offs); assert_int_equal(rdev_relative_offset(&child, &mock_rdev), -1); diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c index f53b390..b36f780 100644 --- a/util/cbfstool/cse_serger.c +++ b/util/cbfstool/cse_serger.c @@ -689,7 +689,7 @@ static int cmd_create_cse_region(void) { - size_t file_size = get_cse_region_end_offset(); + size_t file_size = get_cse_region_end_offset() + 1; struct buffer cse_buff, layout_buff; if (fill_layout_buffer(&layout_buff)) -- To view, visit https://review.coreboot.org/c/coreboot/+/79977?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Gerrit-Change-Number: 79977 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Re-factor the Memory Setting
by Daniel Peng (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Ivan Chen, Karthik Ramasubramanian. Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79976?usp=email ) Change subject: mb/google/dedede/var/galtic: Re-factor the Memory Setting ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79976/comment/66d6a652_c04dd21b : PS1, Line 15: BRANCH=firmware-dedede-13606.B > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/79976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Gerrit-Change-Number: 79976 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 06:32:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Re-factor the Memory Setting
by Daniel Peng (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Ivan Chen, Karthik Ramasubramanian. Hello Ivan Chen, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79976?usp=email to look at the new patch set (#2). Change subject: mb/google/dedede/var/galtic: Re-factor the Memory Setting ...................................................................... mb/google/dedede/var/galtic: Re-factor the Memory Setting Repo sync code recently, run command as memtion in TEST and found the changed for the auto-gen files. Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR, and no new for the used hex file. BUG=b:320181366 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc M src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79976/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Gerrit-Change-Number: 79976 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Re-factor the Memory Setting
by Daniel Peng (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Ivan Chen, Karthik Ramasubramanian. Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79976?usp=email ) Change subject: mb/google/dedede/var/galtic: Re-factor the Memory Setting ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Gerrit-Change-Number: 79976 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 06:22:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Re-factor the Memory Setting
by Daniel Peng (Code Review) 15 Jan '24

15 Jan '24

Daniel Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79976?usp=email ) Change subject: mb/google/dedede/var/galtic: Re-factor the Memory Setting ...................................................................... mb/google/dedede/var/galtic: Re-factor the Memory Setting Repo sync code recently, run command as memtion in TEST and found the changed for the auto-gen files. Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR, and no new for the used hex file. BUG=b:320181366 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc M src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79976/1 diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc index 7b9f433..b4a4e64 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +# /tmp/go-build591443712/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt index 8d15cd9..73b84c1 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +# /tmp/go-build591443712/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory/ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D2NP-046 WT:E 0 (0000) -K4UBE3D4AA-MGCR 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt index 03c8be0..52d4018 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -6,6 +6,6 @@ # Part Name H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E -K4UBE3D4AA-MGCR +K4U6E3S4AA-MGCR MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE -- To view, visit https://review.coreboot.org/c/coreboot/+/79976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Gerrit-Change-Number: 79976 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: ec/dell/mec5035: Hook up radio enables to option API
by Nicholas Chin (Code Review) 15 Jan '24

15 Jan '24

Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79011?usp=email ) Change subject: ec/dell/mec5035: Hook up radio enables to option API ...................................................................... Patch Set 3: (1 comment) This change is ready for review. Patchset: PS3: Original commit was merged out of order and reverted. This one restores it. -- To view, visit https://review.coreboot.org/c/coreboot/+/79011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfa17ca83ca178c942d9c41533152235384e0cdf Gerrit-Change-Number: 79011 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Jan 2024 05:32:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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