coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER
by Arthur Heymans (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Felix Held, Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79931?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79931/comment/fbc915d4_efa2d110 : PS1, Line 9: CN82xx cn81xx ? -- To view, visit https://review.coreboot.org/c/coreboot/+/79931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Gerrit-Change-Number: 79931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Jan 2024 09:42:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/sata: Enable SATA clock gating
by Lean Sheng Tan (Code Review) 15 Jan '24

15 Jan '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79146?usp=email ) Change subject: sb/intel/bd82x6x/sata: Enable SATA clock gating ...................................................................... sb/intel/bd82x6x/sata: Enable SATA clock gating Program SATA IOBP and enable clock gating after port enable bits have been written. The same registers are already set for DMI and PCIe. TEST: Lenovo X220 still boots over SATA. Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 9dc58fd..a30c01a 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -219,6 +219,10 @@ ~(1 << 16 | 0x3f << 7 | 3 << 5 | 3 << 3), 1 << 24 | 1 << 22 | 1 << 20 | 1 << 19 | 1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3); + + /* SATA clock gating. Must be done after writing register 0x94. */ + pch_iobp_update(0xEA007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEA004000, ~0U, (1 << 7)); } static void sata_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/79146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Gerrit-Change-Number: 79146 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains
by Lean Sheng Tan (Code Review) 15 Jan '24

15 Jan '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78829?usp=email ) Change subject: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains ...................................................................... sb/intel/bd82x6x/early_usb: Add USB TX/RX gains Describe the USB 'current' settings based on MRC.bin that converts the USB trace length to a predefined register value. MRC.bin decides which setting to use based on the PC type, mobile or desktop, and the trace length. Tested: Lenovo X220 still boots. Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 19 insertions(+), 6 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 974c190..35bfeca 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -16,26 +16,27 @@ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, - 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, - 0x20000353 }; + const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, + USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, + USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 }; int i; /* Unlock registers. */ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) { - if (portmap[i].enabled && !pch_is_mobile() && portmap[i].current == 0) { + if (portmap[i].enabled && !pch_is_mobile() && + currents[portmap[i].current] == USBIR_TXRX_GAIN_MOBILE_LOW) { /* * Note for developers: You can fix this by re-running autoport on * vendor firmware and then updating portmap currents accordingly. * If that is not possible, another option is to choose a non-zero * current setting. In either case, please test all the USB ports. */ - printk(BIOS_ERR, "%s: USB%02d: current setting of 0 is an invalid setting for desktop!\n", + printk(BIOS_ERR, "%s: USB%02d: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!\n", __func__, i); - RCBA32(USBIR0 + 4 * i) = currents[1]; + RCBA32(USBIR0 + 4 * i) = USBIR_TXRX_GAIN_DEFAULT; } else { RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 88c8df5c..040b477 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -382,6 +382,18 @@ #define USBIR12 0x3530 /* 32bit */ #define USBIR13 0x3534 /* 32bit */ +/* Up to 5" onboard trace length */ +#define USBIR_TXRX_GAIN_MOBILE_LOW 0x20000153 + +/* Up to 6" onboard trace length */ +#define USBIR_TXRX_GAIN_DESKTOP_LOW 0x20000F53 + +/* Up to 14" onboard trace length, up to 8" on wires */ +#define USBIR_TXRX_GAIN_DEFAULT 0x20000f57 + +/* Up to 10" onboard trace length, up to 15" on wires */ +#define USBIR_TXRX_GAIN_HIGH 0x2000055B + /* Miscellaneous Control Register */ #define MISCCTL 0x3590 /* 32bit */ /* USB Port Disable Override */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Gerrit-Change-Number: 78829 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: util/autoport: Improve USB code
by Lean Sheng Tan (Code Review) 15 Jan '24

15 Jan '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78828?usp=email ) Change subject: util/autoport: Improve USB code ...................................................................... util/autoport: Improve USB code Currently autoport fills in USB current '0' if the detected setting isn't one of the known settings. This works as 0 is a valid setting from C point of view, but it's not supported on desktop PCs and on mobile platform results in the lowest possible USB PHY gain. Thus this might cause instabilities as the original firmware had stronger USB drive currents and gain settings. Add more known USB current fields to the map and generate a FIXME as comment when the detected current isn't one of the known entries instead of defaulting to 0. Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78828 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/autoport/bd82x6x.go 1 file changed, 13 insertions(+), 3 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, but someone else must approve diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 6ce15a2..76411e7 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -309,6 +309,10 @@ 0x2000055b: 2, 0x20000f51: 3, 0x2000094a: 4, + 0x2000035f: 5, + 0x20000f53: 6, + 0x20000357: 7, + 0x20000353: 8, } for port := uint(0); port < 14; port++ { @@ -327,10 +331,16 @@ } } } - fmt.Fprintf(sb, "\t{ %d, %d, %d },\n", + current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]] + comment := "" + if !ok { + comment = fmt.Sprintf("// FIXME: Unknown current: RCBA(0x%x)=0x%x", 0x3500+4*port, uint16(0x3500+4*port)) + } + fmt.Fprintf(sb, "\t{ %d, %d, %d }, %s\n", ((inteltool.RCBA[0x359c]>>port)&1)^1, - currentMap[inteltool.RCBA[uint16(0x3500+4*port)]], - OCPin) + current, + OCPin, + comment) } sb.WriteString("};\n") -- To view, visit https://review.coreboot.org/c/coreboot/+/78828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080 Gerrit-Change-Number: 78828 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting
by Lean Sheng Tan (Code Review) 15 Jan '24

15 Jan '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78827?usp=email ) Change subject: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting ...................................................................... sb/intel/bd82x6x/early_usb: Print error for invalid USB setting According to BWG the USB current setting 0 should not be used for desktop boards. As autoport defaults to 0 if the USB current doesn't match one of the lookup table entries most of the desktop boards in tree have such a setting. Print an error to alert users of such boards to update the USB current settings. Tested: Lenovo X220 still boots. Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78827 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 17 insertions(+), 2 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 654d44b..974c190 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -23,8 +24,22 @@ /* Unlock registers. */ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); - for (i = 0; i < 14; i++) - RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; + for (i = 0; i < 14; i++) { + if (portmap[i].enabled && !pch_is_mobile() && portmap[i].current == 0) { + /* + * Note for developers: You can fix this by re-running autoport on + * vendor firmware and then updating portmap currents accordingly. + * If that is not possible, another option is to choose a non-zero + * current setting. In either case, please test all the USB ports. + */ + printk(BIOS_ERR, "%s: USB%02d: current setting of 0 is an invalid setting for desktop!\n", + __func__, i); + + RCBA32(USBIR0 + 4 * i) = currents[1]; + } else { + RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; + } + } for (i = 0; i < 10; i++) RCBA32(0x3538 + 4 * i) = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/78827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Gerrit-Change-Number: 78827 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Dtrain Hsu, Eric Lai, Ian Feng, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79978?usp=email ) Change subject: mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79978/comment/22e947c9_9b1645af : PS2, Line 7: Modify ELAN touchscreen enable delay Please be more specific: Increase … from to … -- To view, visit https://review.coreboot.org/c/coreboot/+/79978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Gerrit-Change-Number: 79978 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 09:32:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Lean Sheng Tan (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 20: Code-Review+2 (1 comment) Patchset: PS20: give my +2 because it has been reviewed by Nico and reviewed & tested by Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 09:31:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay
by Rex Chou (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Dtrain Hsu, Eric Lai, Ian Feng, Kenny Pan, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Rex Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79978?usp=email ) Change subject: mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79978/comment/22a81149_75dee1a1 : PS1, Line 7: Modify touchscreen enable delay to meet spec > nit: Modify ELAN touchscreen enable delay Done https://review.coreboot.org/c/coreboot/+/79978/comment/6f7b6555_4d98df6b : PS1, Line 9: Modify touchscreen enable_delay to 6ms to meet with spec. > please also mention ELAN spec version here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Gerrit-Change-Number: 79978 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 08:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay
by Rex Chou (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Dtrain Hsu, Ian Feng, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Hello Dtrain Hsu, Eric Lai, Ian Feng, Kenny Pan, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79978?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay ...................................................................... mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay Modify touchscreen enable_delay to 6ms to meet with spec. eKTH3915N_Product Spec_V1.3_20221028_IPM.pdf BUG=b:318443640 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79978/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Gerrit-Change-Number: 79978 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: tree: Refactor region_end() to return last used address of a region
by Werner Zeh (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Jakub Czapiga, Jérémy Compostella, Maximilian Brune, Nico Huber, Tim Crawford. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79977?usp=email ) Change subject: tree: Refactor region_end() to return last used address of a region ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Nico Huber already prepared such patch. […] Oh, I wasn't aware, thanks for the pointer. Seems like we ded it similar, I am happy with either way. -- To view, visit https://review.coreboot.org/c/coreboot/+/79977?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Gerrit-Change-Number: 79977 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 08:10:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <czapiga(a)google.com> Gerrit-MessageType: comment

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