coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: device/device.h: Fix outdated comment
by Arthur Heymans (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78329?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: device/device.h: Fix outdated comment ...................................................................... device/device.h: Fix outdated comment LAPIC devices in devicetree is not possible any longer since commit 3eba665 "util/sconfig: Remove lapic devices from devicetree parsers". Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 --- M src/include/device/device.h 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/78329/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Gerrit-Change-Number: 78329 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Arthur Heymans (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier. Hello Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78328?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/device.h: Drop multiple links ...................................................................... device/device.h: Drop multiple links Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b --- M src/arch/x86/mpspec.c M src/device/device.c M src/device/device_util.c M src/device/pci_device.c M src/device/root_device.c M src/include/device/device.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/common/block/lpc/lpc.c M src/southbridge/amd/pi/hudson/lpc.c M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.y 16 files changed, 184 insertions(+), 373 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78328/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: intel skl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michał Żygowski, Nicholas Sudsgaard, Nico Huber, Piotr Król. Hello Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michał Żygowski, Nicholas Sudsgaard, Nico Huber, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79958?usp=email to look at the new patch set (#2). Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries ...................................................................... intel skl mainboards: Move PcieRpEnable option below dt entries There is work being done on better integrating the root port entries from the devicetree by hooking up the FSP option PcieRpEnable to them, which supersedes the devicetree option. Move the PcieRpEnable option below their related devicetree entries in order to make the review easier when the option is removed. Create devicetree entries in case of they don't exist yet. Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 17 files changed, 202 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79958/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Gerrit-Change-Number: 79958 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: intel skl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michał Żygowski, Nicholas Sudsgaard, Nico Huber, Piotr Król. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79958?usp=email ) Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Missing google/poppy. Waiting for CB:79439 to get finished. -- To view, visit https://review.coreboot.org/c/coreboot/+/79958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Gerrit-Change-Number: 79958 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 14:29:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: intel skl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79958?usp=email ) Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries ...................................................................... intel skl mainboards: Move PcieRpEnable option below dt entries There is work being done on better integrating the root port entries from the devicetree by hooking up the FSP option PcieRpEnable to them, which supersedes the devicetree option. Move the PcieRpEnable option below their related devicetree entries in order to make the review easier when the option is removed. Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 17 files changed, 202 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79958/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 2695451..1bc6948 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -56,21 +56,18 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enable Root Ports 3, 4 and 9 - register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpLtrEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" # Wireless controller register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" # NVMe controller register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" @@ -108,9 +105,18 @@ device ref thermal on end device ref heci1 on end device ref sata on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp9 on end + device ref pcie_rp3 on + # Ethernet controller + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + # Wireless controller + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp9 on + # NVMe controller + register "PcieRpEnable[8]" = "1" + end device ref lpc_espi on chip ec/51nb/npce985la0dx device pnp 0c09.0 on end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 3f71ca9..e469049 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -136,7 +136,6 @@ # PCIE Port 2 disabled # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard - register "PcieRpEnable[2]" = "1" # Disable CLKREQ# register "PcieRpClkReqSupport[2]" = "0" # Set MaxPayload to 256 bytes @@ -152,7 +151,6 @@ # PCIE Port 5 x1 -> MODULE i219 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "0" # Set MaxPayload to 256 bytes register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" @@ -167,7 +165,6 @@ # PCIE Port 8 Disabled # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA - register "PcieRpEnable[8]" = "1" # Disable CLKREQ# register "PcieRpClkReqSupport[8]" = "0" # Use Hot Plug subsystem @@ -224,9 +221,18 @@ device ref thermal on end device ref heci1 on end device ref sata on end - device ref pcie_rp3 on end # x1 baseboard WWAN - device ref pcie_rp6 on end # x1 baseboard i210 - device ref pcie_rp9 on end # x4 FPGA + device ref pcie_rp3 on + # x1 baseboard WWAN + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp6 on + # x1 baseboard i210 + register "PcieRpEnable[5]" = "1" + end + device ref pcie_rp9 on + # x4 FPGA + register "PcieRpEnable[8]" = "1" + end device ref uart0 on end device ref emmc on end device ref lpc_espi on diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index dfa7a6e..d2ffac0 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -126,7 +126,6 @@ }" # Enable Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -136,7 +135,6 @@ register "PcieRpClkSrcNumber[0]" = "1" # Enable Root port 5 with SRCCLKREQ4# - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -362,12 +360,15 @@ end end # I2C #4 device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end end - device ref pcie_rp5 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end device ref uart0 on end device ref gspi0 on chip drivers/spi/acpi diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 44fc014..b0e2b13 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -159,7 +159,6 @@ }" # Enable Root port 3(x1) for LAN. - register "PcieRpEnable[2]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[2]" = "1" # RP 3 uses SRCCLKREQ0# @@ -172,7 +171,6 @@ register "PcieRpClkSrcNumber[2]" = "0" # Enable Root port 4(x1) for WLAN. - register "PcieRpEnable[3]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[3]" = "1" # RP 4 uses SRCCLKREQ5# @@ -185,7 +183,6 @@ register "PcieRpClkSrcNumber[3]" = "5" # Enable Root port 5(x4) for NVMe. - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[4]" = "1" # RP 5 uses SRCCLKREQ1# @@ -198,7 +195,6 @@ register "PcieRpClkSrcNumber[4]" = "1" # Enable Root port 9 for BtoB. - register "PcieRpEnable[8]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[8]" = "1" # RP 9 uses SRCCLKREQ2# @@ -211,7 +207,6 @@ register "PcieRpClkSrcNumber[8]" = "2" # Enable Root port 11 for BtoB. - register "PcieRpEnable[10]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[10]" = "1" # RP 11 uses SRCCLKREQ2# @@ -224,7 +219,6 @@ register "PcieRpClkSrcNumber[10]" = "2" # Enable Root port 12 for BtoB. - register "PcieRpEnable[11]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[11]" = "1" # RP 12 uses SRCCLKREQ2# @@ -372,6 +366,7 @@ device ref pcie_rp1 on end device ref pcie_rp3 on # LAN, will be swapped to port 1 by FSP + register "PcieRpEnable[2]" = "1" chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" @@ -381,22 +376,31 @@ end device ref pcie_rp4 on # WLAN + register "PcieRpEnable[3]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end end - device ref pcie_rp5 on end # NVMe + device ref pcie_rp5 on + # NVMe + register "PcieRpEnable[4]" = "1" + end device ref pcie_rp9 on # 2nd LAN + register "PcieRpEnable[8]" = "1" chip drivers/net register "customized_leds" = "0x0fa5" register "device_index" = "1" device pci 00.0 on end end end - device ref pcie_rp11 on end - device ref pcie_rp12 on end + device ref pcie_rp11 on + register "PcieRpEnable[10]" = "1" + end + device ref pcie_rp12 on + register "PcieRpEnable[11]" = "1" + end device ref uart0 on end device ref gspi0 on chip drivers/spi/acpi diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 989b2406..685f2fc 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake # Enable Root port 7(x1) for TPU1 - register "PcieRpEnable[6]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[6]" = "1" # RP 7 uses SRCCLKREQ4# @@ -14,7 +13,6 @@ register "PcieRpClkSrcNumber[6]" = "4" # Enable Root port 8(x1) for TPU0 - register "PcieRpEnable[7]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[7]" = "1" # RP 8 uses SRCCLKREQ2# @@ -27,7 +25,6 @@ register "PcieRpClkSrcNumber[7]" = "2" # Enable Root port 9(x4) for i350 LAN - register "PcieRpEnable[8]" = "1" # Disable CLKREQ# register "PcieRpClkReqSupport[8]" = "0" # RP 9, Enable Advanced Error Reporting @@ -37,11 +34,6 @@ # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" - # These are part of Root port 9(x4) - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear @@ -156,11 +148,17 @@ device i2c 13 on end end end - device ref pcie_rp7 on end # TPU1 - device ref pcie_rp8 on end # TPU0 - device ref pcie_rp9 on end # POE LAN - device ref pcie_rp10 off end - device ref pcie_rp11 off end - device ref pcie_rp12 off end + device ref pcie_rp7 on + # TPU1 + register "PcieRpEnable[6]" = "1" + end + device ref pcie_rp8 on + # TPU0 + register "PcieRpEnable[7]" = "1" + end + device ref pcie_rp9 on + # POE LAN + register "PcieRpEnable[8]" = "1" + end end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 58b421c..b254fe8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -49,7 +49,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s # Enable Root port 1 - register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# @@ -93,6 +92,7 @@ device ref uart2 on end device ref i2c4 on end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b580e76..04024cb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -6,38 +6,31 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable PCIE slot - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" - register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2" - register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3" - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4" - register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5" - register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 # RP17, uses CLK SRC 7 @@ -116,5 +109,23 @@ device ref sdxc off end device ref hda on end device ref gbe on end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + end + device ref pcie_rp7 on + register "PcieRpEnable[6]" = "1" + end + device ref pcie_rp8 on + register "PcieRpEnable[7]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end + device ref pcie_rp14 on + register "PcieRpEnable[13]" = "1" + end + device ref pcie_rp17 on + register "PcieRpEnable[16]" = "1" + end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b7c4395..b3668b9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -38,21 +38,18 @@ # Enable Root ports. # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" # RP6, uses CLK SRC 1 @@ -61,14 +58,12 @@ # PCIE Port 7 Disabled # PCIE Port 8 Disabled # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" # RP10, uses CLK SRC 4 @@ -115,11 +110,26 @@ device domain 0 on device ref imgu on end device ref cio on end - device ref pcie_rp1 on end # x4 SLOT1 - device ref pcie_rp5 on end # x1 SLOT2/LAN - device ref pcie_rp6 on end # x1 SLOT3 - device ref pcie_rp9 on end # x1 WLAN - device ref pcie_rp10 on end # x1 WIGIG + device ref pcie_rp1 on + # x4 SLOT1 + register "PcieRpEnable[0]" = "1" + end + device ref pcie_rp5 on + # x1 SLOT2/LAN + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp6 on + # x1 SLOT3 + register "PcieRpEnable[5]" = "1" + end + device ref pcie_rp9 on + # x1 WLAN + register "PcieRpEnable[8]" = "1" + end + device ref pcie_rp10 on + # x1 WIGIG + register "PcieRpEnable[9]" = "1" + end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index c5b7e94..1d32850 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -81,13 +81,6 @@ .voltage_limit = 0 }" - # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqSupport[3]" = "1" @@ -158,10 +151,21 @@ device ref i2c2 off end device ref i2c3 off end device ref sata on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 2291c63..df5e62e 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -77,11 +77,6 @@ .voltage_limit = 0 }" - # Enable Root port. - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[16]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[3]" = "1" @@ -166,8 +161,18 @@ device ref i2c4 off end device ref pcie_rp1 off end device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end + device ref pcie_rp17 on + register "PcieRpEnable[16]" = "1" + end device ref emmc off end device ref sdxc off end device ref lpc_espi on diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 0d9331b..71576b7 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -108,8 +108,6 @@ }" # Enable Root port 1 and 5. - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqSupport[4]" = "1" @@ -225,12 +223,15 @@ end end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end - device ref pcie_rp5 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end device ref uart0 on end device ref emmc on end device ref sdxc on end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index f2234a6..bba3ce8 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -102,19 +102,13 @@ }" # Enable x1 slot - register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 # Enable x4 slot - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqSupport[12]" = "1" @@ -211,6 +205,18 @@ device ref i2c5 on end device ref i2c4 on end device ref pcie_rp1 on end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + end + device ref pcie_rp8 on + register "PcieRpEnable[7]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end + device ref pcie_rp13 on + register "PcieRpEnable[12]" = "1" + end device ref uart0 on end device ref uart1 on end device ref gspi0 on end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index ecfcd6f..89c86d4 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake - # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3) - register "PcieRpEnable[ 0]" = "1" - register "PcieRpEnable[ 1]" = "1" - register "PcieRpEnable[ 2]" = "1" - register "PcieRpEnable[ 3]" = "1" - register "PcieRpEnable[11]" = "1" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" @@ -21,11 +14,21 @@ register "SataPortsEnable[3]" = "1" device domain 0 on - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp12 on end + device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + end + device ref pcie_rp2 on + register "PcieRpEnable[1]" = "1" + end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp12 on + register "PcieRpEnable[11]" = "1" + end device ref smbus on chip drivers/i2c/nct7802y register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index cdddf3d..ef3ec23 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -117,13 +117,6 @@ .voltage_limit = 1520, }" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" register "PcieRpClkSrcNumber[0]" = "0" register "PcieRpClkSrcNumber[3]" = "1" @@ -168,19 +161,32 @@ device ref thermal on end device ref heci1 on end device ref sata on end - device ref pcie_rp3 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + end device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" end device ref pcie_rp6 on end device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "SSD_M.2 2242/2280" "SlotDataBusWidth4X" end - device ref pcie_rp10 on end - device ref pcie_rp11 on end - device ref pcie_rp12 on end + device ref pcie_rp10 on + register "PcieRpEnable[9]" = "1" + end + device ref pcie_rp11 on + register "PcieRpEnable[10]" = "1" + end + device ref pcie_rp12 on + register "PcieRpEnable[11]" = "1" + end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 092115c..7d95eaa 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -116,15 +116,6 @@ register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" - # Enable Root ports. 1-6 for LAN and Root Port 9 - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" # mPCIe WiFi - # Enable Advanced Error Reporting for RP 1-6, 9 register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpAdvancedErrorReporting[1]" = "1" @@ -158,7 +149,6 @@ # RP 9 shares CLKSRC5# with RP 6 register "PcieRpClkSrcNumber[8]" = "5" - # USB 2.0 enable ports 1-8, disable ports 9-12 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port @@ -195,14 +185,27 @@ device ref south_xhci on end device ref heci1 on end device ref sata on end - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end + device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + end + device ref pcie_rp2 on + register "PcieRpEnable[1]" = "1" + end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + end device ref pcie_rp9 on - # WIFI + # mPCIe WIFI + register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 1928d15..7cfa675 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -137,10 +137,6 @@ .dc_loadline = 420, }" - # Enable Root Ports 5 and 9 - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - # PL2 override 25W register "power_limits_config" = "{ .tdp_pl2_override = 25, @@ -158,7 +154,12 @@ device ref thermal on end device ref sata on end device ref pcie_rp1 on end - device ref pcie_rp9 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 1323164..2545dc5 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -115,11 +115,6 @@ .dc_loadline = 310, }" - # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[2]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpLtrEnable[8]" = "1" @@ -188,8 +183,15 @@ device ref heci1 on end device ref uart2 on end device ref pcie_rp1 on end - device ref pcie_rp5 on end - device ref pcie_rp9 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/79958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Gerrit-Change-Number: 79958 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: tree: Refactor region_end() to return last used address of a region
by Werner Zeh (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Jakub Czapiga, Jérémy Compostella, Maximilian Brune, Nico Huber, Tim Crawford. Hello Jakub Czapiga, Jérémy Compostella, Maximilian Brune, Nico Huber, Tim Crawford, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79977?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tree: Refactor region_end() to return last used address of a region ...................................................................... tree: Refactor region_end() to return last used address of a region Currently, function region_end() does return the next address after the end of a given region. This is not only confusing (as the next address after a region is not part of this region anymore) but can lead to integer overflow if the region's end reaches SIZE_MAX. This possible overflow can then lead to not catching a region overlap as reported in a bug in [1]. This patch changes now the behavior of region_end() and makes it return the last valid address of a region. In addition, the integer overflow is checked and if it would happen, SIZE_MAX is returned (which truncates the region's end to SIZE_MAX for this corner case). And since region_end() now returns a different address, some unit-tests need adjustments. [1]: https://ticket.coreboot.org/issues/522 Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/spi/winbond.c M src/include/cpu/x86/smm.h M tests/commonlib/region-test.c M util/cbfstool/cse_serger.c 7 files changed, 32 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79977/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79977?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide7a39af1609fed63d08832a6dcc4679a85c5027 Gerrit-Change-Number: 79977 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Jakub Czapiga (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Marek Maślanka. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/apollolake/include/soc/smbus.h: -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 1 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 14:12:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/gothrax: Tune eMMC DLL values
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Eric Lai, Jamie Chen, Kyle Lin, Nick Vaccaro, Simon Yang, Subrata Banik, Yunlong Jia. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79220?usp=email ) Change subject: mb/google/nissa/var/gothrax: Tune eMMC DLL values ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79220/comment/b2617498_7a3192bd : PS3, Line 9: and with a https://review.coreboot.org/c/coreboot/+/79220/comment/793b7206_65fea534 : PS3, Line 13: success successful https://review.coreboot.org/c/coreboot/+/79220/comment/e9266457_5190ab8c : PS3, Line 14: - Collecting every eMMC that use for the project Sorry, I do not understand this. https://review.coreboot.org/c/coreboot/+/79220/comment/e28d9d15_97b09222 : PS3, Line 15: a fine tune fine tuned https://review.coreboot.org/c/coreboot/+/79220/comment/51302c41_b418c9a4 : PS3, Line 16: What do the new values do? -- To view, visit https://review.coreboot.org/c/coreboot/+/79220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79 Gerrit-Change-Number: 79220 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 13:55:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: ec/dell/mec5035: Add command to control radio state
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Daniel Maslowski, Felix Singer, Iru Cai, Martin L Roth, Nicholas Chin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77534?usp=email ) Change subject: ec/dell/mec5035: Add command to control radio state ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b Gerrit-Change-Number: 77534 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 13:52:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Angel Pons, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79784?usp=email ) Change subject: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/c/coreboot/+/79784/comment/8fe739b2_0479ec30 : PS1, Line 787: srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; As the assignment is the same, use only one if branch? -- To view, visit https://review.coreboot.org/c/coreboot/+/79784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af Gerrit-Change-Number: 79784 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 13:52:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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