coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Reto Buerki (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Paul Menzel. Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79957?usp=email ) Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79957/comment/6c41db88_13c60d53 : PS1, Line 10: appollolake > Appollo Lake Done https://review.coreboot.org/c/coreboot/+/79957/comment/1469d470_ee755ce9 : PS1, Line 12: leading to the following error messages on Linux > Please mention the device and the Linux kernel version. Done https://review.coreboot.org/c/coreboot/+/79957/comment/aa13a9c0_a922ab91 : PS1, Line 14: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] : pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] : pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] : pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window : pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window : pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] : pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] > Maybe indent by four spaces? Done Patchset: PS2: Thanks for the review, I adjusted the commit message as suggested. -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 15 Jan 2024 15:13:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Reto Buerki (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Reto Buerki. Hello Arthur Heymans, Matt DeVillier, Paul Menzel, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79957?usp=email to look at the new patch set (#2). Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... soc/intel/apollolake: Fix PCI memory resource alloc There is a mismatch in how PCI memory resources are allocated on Appollo Lake with the current configuration. While the ACPI code expects resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code allocates them above, leading to the following error messages on Linux: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] Tested on up/squared with Linux kernel version 6.1.0. Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS, and by moving the UART base address into the expected range. Thanks to Nico Huber for the help in writing this patch. Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Signed-off-by: Reto Buerki <reet(a)codelabs.ch> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/79957/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/google/poppy: Use chipset dt reference names
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Martin L Roth, Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79439?usp=email ) Change subject: mb/google/poppy: Use chipset dt reference names ...................................................................... Patch Set 7: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Gerrit-Change-Number: 79439 Gerrit-PatchSet: 7 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 15:08:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/poppy: Use chipset dt reference names
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Martin L Roth, Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79439?usp=email ) Change subject: mb/google/poppy: Use chipset dt reference names ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Gerrit-Change-Number: 79439 Gerrit-PatchSet: 7 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 15:08:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device/device.h: Fix outdated comment
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78329?usp=email ) Change subject: device/device.h: Fix outdated comment ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Gerrit-Change-Number: 78329 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Jan 2024 15:04:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device/device.h: Drop acpi_inject_dsdt
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Cliff Huang, Jincheng Li, Lance Zhao, Shuo Liu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78334?usp=email ) Change subject: device/device.h: Drop acpi_inject_dsdt ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 Gerrit-Change-Number: 78334 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 15 Jan 2024 15:03:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Reto Buerki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79957?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79957/comment/b35b778f_526f0cdc : PS1, Line 10: appollolake Appollo Lake https://review.coreboot.org/c/coreboot/+/79957/comment/f3df5ed1_9436a5b2 : PS1, Line 12: leading to the following error messages on Linux Please mention the device and the Linux kernel version. https://review.coreboot.org/c/coreboot/+/79957/comment/a6987848_1e957d8f : PS1, Line 14: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] : pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] : pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] : pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window : pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window : pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] : pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] Maybe indent by four spaces? -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 1 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 15:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Arthur Heymans (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Reto Buerki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79957?usp=email ) Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 1 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 14:59:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Arthur Heymans (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh. Hello Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78330?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/device.h: Rename busses for clarity ...................................................................... device/device.h: Rename busses for clarity This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/x86/mpspec.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/device/cardbus_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/i2c_bus.c M src/device/mdio.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/interrupt.c M src/device/pci_device.c M src/device/pci_rom.c M src/device/pciexp_device.c M src/device/pcix_device.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/device/root_device.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pcie/generic/generic.c M src/drivers/spi/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/smbios.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/google/chromeec/ec_acpi.c M src/include/device/device.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/brox/mainboard.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/kahlee/variants/careena/mainboard.c M src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/roda/rk9/ti_pci7xx1.c M src/mainboard/siemens/fa_ehl/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/xhci.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/xhci.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/intel/apollolake/chip.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/pcie.c M src/superio/common/generic.c M src/superio/common/ssdt.c M util/sconfig/main.c 101 files changed, 311 insertions(+), 316 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/78330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Gerrit-Change-Number: 78330 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu 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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Sean Rhodes (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Reto Buerki. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79957?usp=email ) Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I don't have any boards I can verify on - do you? -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 1 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 14:53:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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