coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: [RFC] region: Turn region_end() into an inclusive region_last()
by Nico Huber (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Jakub Czapiga, Jérémy Compostella, Werner Zeh. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79946?usp=email ) Change subject: [RFC] region: Turn region_end() into an inclusive region_last() ...................................................................... Patch Set 5: (1 comment) File src/drivers/spi/winbond.c: https://review.coreboot.org/c/coreboot/+/79946/comment/755e9a54_8c3fbe1a : PS5, Line 505: region_last(region) + 1 > Could this possibly lead to an overflow again? Yes, it would be better to use `flash->size - 1`. I guess we shouldn't expect regions bigger than a flash, but better safe than sorry. OTOH, (just read the code again), it would need a 4GiB flash to make a difference :) -- To view, visit https://review.coreboot.org/c/coreboot/+/79946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Gerrit-Change-Number: 79946 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 17:25:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/galtic: Correct the Memory Part Name
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Daniel Peng, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79976?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/dedede/var/galtic: Correct the Memory Part Name ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79976/comment/00f9a9bd_8f89f1d0 : PS4, Line 7: Correct the Memory Part Name Correct name for mem-part K4U6E3S4AA-MGCR https://review.coreboot.org/c/coreboot/+/79976/comment/cfa1ebca_6c0ddacf : PS4, Line 9: memtion mentioned? https://review.coreboot.org/c/coreboot/+/79976/comment/a606c8f8_74983a8a : PS4, Line 11: Please only one space. https://review.coreboot.org/c/coreboot/+/79976/comment/4221de7c_6ff4a08e : PS4, Line 13: How could this mistake happen? Was there a bug in the script? -- To view, visit https://review.coreboot.org/c/coreboot/+/79976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Gerrit-Change-Number: 79976 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 17:19:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi_gic: Add helper for platform gicc
by Paul Menzel (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Cliff Huang, Lance Zhao, Naresh Solanki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79973?usp=email ) Change subject: acpi_gic: Add helper for platform gicc ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79973/comment/832a9a09_c754a9e3 : PS1, Line 8: Please elaborate. -- To view, visit https://review.coreboot.org/c/coreboot/+/79973?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd4c52a5482707fae8aa1b8b21fdc6bb5f4b45c2 Gerrit-Change-Number: 79973 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 17:17:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi_gic: Add helper for platform gicc
by Tim Wawrzynczak (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Cliff Huang, Lance Zhao, Naresh Solanki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79973?usp=email ) Change subject: acpi_gic: Add helper for platform gicc ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79973?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd4c52a5482707fae8aa1b8b21fdc6bb5f4b45c2 Gerrit-Change-Number: 79973 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 16:47:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Reto Buerki (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Paul Menzel. Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79957?usp=email ) Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79957/comment/63c2c649_237987d5 : PS2, Line 9: Appollo > Apollo Done Patchset: PS2: Doh! Fixed, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 15 Jan 2024 16:43:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/apollolake: Fix PCI memory resource alloc
by Reto Buerki (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Paul Menzel, Reto Buerki. Hello Arthur Heymans, Matt DeVillier, Paul Menzel, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79957?usp=email to look at the new patch set (#3). Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ...................................................................... soc/intel/apollolake: Fix PCI memory resource alloc There is a mismatch in how PCI memory resources are allocated on Apollo Lake with the current configuration. While the ACPI code expects resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code allocates them above, leading to the following error messages on Linux: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] Tested on up/squared with Linux kernel version 6.1.0. Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS, and by moving the UART base address into the expected range. Thanks to Nico Huber for the help in writing this patch. Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Signed-off-by: Reto Buerki <reet(a)codelabs.ch> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/79957/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Gerrit-Change-Number: 79957 Gerrit-PatchSet: 3 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mainboard: Add MSI MS-7788
by Name of user not set (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Angel Pons, Name of user not set #1005283. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79979?usp=email to look at the new patch set (#2). Change subject: mainboard: Add MSI MS-7788 ...................................................................... mainboard: Add MSI MS-7788 NOTES: * This is the product of a beginner running `autoport` please forgive any gaps in my knowledge about the project * There are still some ugly hacks in this commit that I would like to test and eventually fix * I still probably need to properly fill in documentation * I also probably should understand everything in this commit! (not just let autoport to the heavy lifting) * And I need to look over the `FIXME`s * MSI h61m-p31/w8 * Winbond 25Q64FVSIG * Fintek F71868AD Working: * PCIe graphics * Integrated graphics * USB (all ports) * Ethernet Yet-to-be-thoroughly-tested: * All SATA ports * All PCIe ports (as in the x1 lane) * Super/IO (is my chip supported?) * Suspend states * Integrated graphics (libgfxinit) * ME (and neutering it?) Untested: * PS/2 Signed-off-by: mrhh69 <122405954+mrhh69(a)users.noreply.github.com> Change-Id: Ia7830fcc7552e9734ec7c57e508a6a77f689e5b0 --- M src/device/device.c A src/mainboard/msi/ms7788/Kconfig A src/mainboard/msi/ms7788/Kconfig.name A src/mainboard/msi/ms7788/Makefile.inc A src/mainboard/msi/ms7788/acpi/ec.asl A src/mainboard/msi/ms7788/acpi/platform.asl A src/mainboard/msi/ms7788/acpi/superio.asl A src/mainboard/msi/ms7788/acpi_tables.c A src/mainboard/msi/ms7788/board_info.txt A src/mainboard/msi/ms7788/devicetree.cb A src/mainboard/msi/ms7788/dsdt.asl A src/mainboard/msi/ms7788/early_init.c A src/mainboard/msi/ms7788/gma-mainboard.ads A src/mainboard/msi/ms7788/gpio.c A src/mainboard/msi/ms7788/hda_verb.c A src/mainboard/msi/ms7788/mainboard.c M src/northbridge/intel/sandybridge/romstage.c 17 files changed, 467 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79979/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7830fcc7552e9734ec7c57e508a6a77f689e5b0 Gerrit-Change-Number: 79979 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1005283 Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Name of user not set #1005283 Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: intel ehl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Werner Zeh. Hello Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79961?usp=email to look at the new patch set (#2). Change subject: intel ehl mainboards: Move PcieRpEnable option below dt entries ...................................................................... intel ehl mainboards: Move PcieRpEnable option below dt entries There is work being done on better integrating the root port entries from the devicetree by hooking up the FSP option PcieRpEnable to them, which supersedes the devicetree option. Move the PcieRpEnable option below their related devicetree entries in order to make the review easier when the option is removed. Change-Id: I3b14704916bb8105837257c271576f30cf62138b Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb 5 files changed, 51 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79961/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b14704916bb8105837257c271576f30cf62138b Gerrit-Change-Number: 79961 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Angel Pons, Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nicholas Sudsgaard, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email ) Change subject: soc/intel/skylake: Drop redundant PcieRpEnable ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > The important part is that we carefully look into the cases where FSP and coreboot […] I would like to move the PcieRpEnable settings below their related devicetree entries first. This way we can verify that both settings match and it's also easier to review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Gerrit-Change-Number: 79917 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 16:32:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: intel ehl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79961?usp=email ) Change subject: intel ehl mainboards: Move PcieRpEnable option below dt entries ...................................................................... intel ehl mainboards: Move PcieRpEnable option below dt entries There is work being done on better integrating the root port entries from the devicetree by hooking up the FSP option PcieRpEnable to them, which supersedes the devicetree option. Change-Id: I3b14704916bb8105837257c271576f30cf62138b Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb 5 files changed, 51 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79961/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 6994e8c..c34907f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -40,11 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -157,11 +152,21 @@ device pci 1a.0 on end # eMMC - device pci 1c.0 on end # RP1 (pcie0 single VC) - device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.2 on end # RP3 (pcie0 single VC) - device pci 1c.3 on end # RP4 (pcie0 single VC) - device pci 1c.6 on end # RP7 (pcie3 multi VC) + device pci 1c.0 on # RP1 (pcie0 single VC) + register "PcieRpEnable[0]" = "1" + end + device pci 1c.1 on # RP2 (pcie0 single VC) + register "PcieRpEnable[1]" = "1" + end + device pci 1c.2 on # RP3 (pcie0 single VC) + register "PcieRpEnable[2]" = "1" + end + device pci 1c.3 on # RP4 (pcie0 single VC) + register "PcieRpEnable[3]" = "1" + end + device pci 1c.6 on # RP7 (pcie3 multi VC) + register "PcieRpEnable[6]" = "1" + end device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index f14c225..a36ea16 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -40,8 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -176,8 +174,12 @@ device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.6 on end # RP7 (pcie3 multi VC) + device pci 1c.1 on # RP2 (pcie0 single VC) + register "PcieRpEnable[1]" = "1" + end + device pci 1c.6 on # RP7 (pcie3 multi VC) + register "PcieRpEnable[6]" = "1" + end device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 9a0142c..d35bcdd 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -40,9 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -183,9 +180,15 @@ device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1c.1 on end # RP2 - device pci 1c.2 on end # RP3 - device pci 1c.4 on end # RP5 + device pci 1c.1 on # RP2 + register "PcieRpEnable[1]" = "1" + end + device pci 1c.2 on # RP3 + register "PcieRpEnable[2]" = "1" + end + device pci 1c.4 on # RP5 + register "PcieRpEnable[4]" = "1" + end device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index e99dd48..0f1650a4 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -40,11 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -178,11 +173,21 @@ device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1c.0 on end # RP1 (pcie0 single VC) - device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.2 on end # RP3 (pcie0 single VC) - device pci 1c.3 on end # RP4 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) + device pci 1c.0 on # RP1 (pcie0 single VC) + register "PcieRpEnable[0]" = "1" + end + device pci 1c.1 on # RP2 (pcie0 single VC) + register "PcieRpEnable[1]" = "1" + end + device pci 1c.2 on # RP3 (pcie0 single VC) + register "PcieRpEnable[2]" = "1" + end + device pci 1c.3 on # RP4 (pcie0 single VC) + register "PcieRpEnable[3]" = "1" + end + device pci 1c.4 on # RP5 (pcie1 multi VC) + register "PcieRpEnable[4]" = "1" + end device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 53ea1f6..6c1cf8b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -40,8 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -183,8 +181,12 @@ device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.6 on end # RP7 (pcie3 multi VC) + device pci 1c.1 on # RP2 (pcie0 single VC) + register "PcieRpEnable[1]" = "1" + end + device pci 1c.6 on # RP7 (pcie3 multi VC) + register "PcieRpEnable[6]" = "1" + end device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/79961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b14704916bb8105837257c271576f30cf62138b Gerrit-Change-Number: 79961 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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