coreboot-gerrit January 2024

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Felix Held (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 11: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/79927/comment/a3701113_1b84c6cd : PS11, Line 98: depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 > wasn't sure how to properly handle the other cases and haven't looked if there's some spec for the l […] ah, there's should_run_oprom, so i won't have to mess with the yabel or the realmode oprom code -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 21:45:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Nico Huber (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 11: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/79927/comment/07832e02_22affe21 : PS11, Line 98: depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 > could still be looked into and added later Absolutely. I'm just talking, please go on :) -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 21:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Felix Held (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 11: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/79927/comment/d4ce49c1_76d2d81e : PS11, Line 98: depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 > I guess a workaround would be to only run ROMs of devices in the first segment group? wasn't sure how to properly handle the other cases and haven't looked if there's some spec for the legacy option roms that might cover multiple segment groups. also not sure how much this would increase the scope of this patch. i'd say the support for running option roms on the first segment group could still be looked into and added later -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 21:35:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/device/pci_mmio_cfg: assert CONFIG_ECAM_MMCONF_BUS_NUMBER != 0
by Felix Held (Code Review) 15 Jan '24

15 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79933?usp=email ) Change subject: include/device/pci_mmio_cfg: assert CONFIG_ECAM_MMCONF_BUS_NUMBER != 0 ...................................................................... include/device/pci_mmio_cfg: assert CONFIG_ECAM_MMCONF_BUS_NUMBER != 0 Make sure that CONFIG_ECAM_MMCONF_BUS_NUMBER is non-zero when the ECAM_MMCONF_SUPPORT Kconfig option is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic102b7dca9ffebb2d384a068a1fb1f4b6fb6c5f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79933 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/device/pci_mmio_cfg.h 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 89c9906..4164441 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -31,6 +31,10 @@ #error "CONFIG_ECAM_MMCONF_BASE_ADDRESS undefined!" #endif +#if CONFIG_ECAM_MMCONF_BUS_NUMBER == 0 +#error "CONFIG_ECAM_MMCONF_BUS_NUMBER is undefined!" +#endif + #if CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB != CONFIG_ECAM_MMCONF_LENGTH #error "CONFIG_ECAM_MMCONF_LENGTH does not correspond with CONFIG_ECAM_MMCONF_BUS_NUMBER!" #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic102b7dca9ffebb2d384a068a1fb1f4b6fb6c5f8 Gerrit-Change-Number: 79933 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER
by Felix Held (Code Review) 15 Jan '24

15 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79931?usp=email ) Change subject: soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER ...................................................................... soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER The Cavium CN81xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0 which is wrong. Both the Cavium CN8100 SFF EVB and the OpenCellular Elgon (GBCv2) mainboard specify 32 PCI buses in their Linux devicetree files, so set the SoC's ECAM_MMCONF_BUS_NUMBER Kconfig option to 32 to match this. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79931 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 368581f..5593685 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -39,4 +39,7 @@ config ECAM_MMCONF_BASE_ADDRESS default 0x848000000000 +config ECAM_MMCONF_BUS_NUMBER + default 32 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Gerrit-Change-Number: 79931 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: device/Kconfig: handle ECAM_MMCONF_BUS_NUMBER being 32
by Felix Held (Code Review) 15 Jan '24

15 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79974?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device/Kconfig: handle ECAM_MMCONF_BUS_NUMBER being 32 ...................................................................... device/Kconfig: handle ECAM_MMCONF_BUS_NUMBER being 32 Provide a default for the ECAM_MMCONF_LENGTH Kconfig option for the ECAM_MMCONF_BUS_NUMBER option being set to 32. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I01e7da5d49f296dde2de41e23e86e3f49fe78193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79974 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/device/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/device/Kconfig b/src/device/Kconfig index 374427a..5202c18 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -593,6 +593,7 @@ config ECAM_MMCONF_LENGTH hex depends on ECAM_MMCONF_SUPPORT + default 0x02000000 if ECAM_MMCONF_BUS_NUMBER = 32 default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64 default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128 default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256 -- To view, visit https://review.coreboot.org/c/coreboot/+/79974?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01e7da5d49f296dde2de41e23e86e3f49fe78193 Gerrit-Change-Number: 79974 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: intel tgl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Matt DeVillier, Nick Vaccaro. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79960?usp=email ) Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/volteer/variants/voema/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79960/comment/d51c7521_21ef22a8 : PS1, Line 108: probe DB_SD SD_GL9755S : probe DB_SD SD_RTS5261 : probe DB_SD SD_RTS5227S : probe DB_SD SD_GL9750 : probe DB_SD SD_OZ711LV2LN > it shouldn't, especially when disabling a previously-enabled device. […] Removed the entries but it broke the build. I'm unsure if they need to be added though, but it's my guess. -- To view, visit https://review.coreboot.org/c/coreboot/+/79960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e Gerrit-Change-Number: 79960 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 15 Jan 2024 20:50:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard: Add MSI MS-7788
by Name of user not set (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Angel Pons, Name of user not set #1005283. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79979?usp=email to look at the new patch set (#3). Change subject: mainboard: Add MSI MS-7788 ...................................................................... mainboard: Add MSI MS-7788 NOTES: * This is the product of a beginner running `autoport` please forgive any gaps in my knowledge about the project * There are still some ugly hacks in this commit that I would like to test and eventually fix * I still probably need to properly fill in documentation * I also probably should understand everything in this commit! (not just let autoport to the heavy lifting) * And I need to look over the `FIXME`s * MSI h61m-p31/w8 * Winbond 25Q64FVSIG * Fintek F71868AD Working: * PCIe graphics * Integrated graphics * USB (all ports) * Ethernet Yet-to-be-thoroughly-tested: * All SATA ports * All PCIe ports (as in the x1 lane) * Super/IO (is my chip supported?) * Suspend states * Integrated graphics (libgfxinit) * ME (and neutering it?) Untested: * PS/2 Signed-off-by: mrhh69 <122405954+mrhh69(a)users.noreply.github.com> Change-Id: Ia7830fcc7552e9734ec7c57e508a6a77f689e5b0 --- M src/device/device.c A src/mainboard/msi/ms7788/Kconfig A src/mainboard/msi/ms7788/Kconfig.name A src/mainboard/msi/ms7788/Makefile.inc A src/mainboard/msi/ms7788/acpi/ec.asl A src/mainboard/msi/ms7788/acpi/platform.asl A src/mainboard/msi/ms7788/acpi/superio.asl A src/mainboard/msi/ms7788/acpi_tables.c A src/mainboard/msi/ms7788/board_info.txt A src/mainboard/msi/ms7788/devicetree.cb A src/mainboard/msi/ms7788/dsdt.asl A src/mainboard/msi/ms7788/early_init.c A src/mainboard/msi/ms7788/gma-mainboard.ads A src/mainboard/msi/ms7788/gpio.c A src/mainboard/msi/ms7788/hda_verb.c A src/mainboard/msi/ms7788/mainboard.c M src/northbridge/intel/sandybridge/romstage.c 17 files changed, 467 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79979/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7830fcc7552e9734ec7c57e508a6a77f689e5b0 Gerrit-Change-Number: 79979 Gerrit-PatchSet: 3 Gerrit-Owner: Name of user not set #1005283 Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Name of user not set #1005283 Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Nico Huber (Code Review) 15 Jan '24

15 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 11: Code-Review+1 (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/79927/comment/ad3f0757_001ab327 : PS11, Line 98: depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 I guess a workaround would be to only run ROMs of devices in the first segment group? -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 15 Jan 2024 20:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/inteltool: Add support for RPL-H CPU
by Matt DeVillier (Code Review) 15 Jan '24

15 Jan '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79962?usp=email ) Change subject: util/inteltool: Add support for RPL-H CPU ...................................................................... util/inteltool: Add support for RPL-H CPU Add PCI IDs and descriptor strings to support the integrated north/south bridges and GPU for the i9-13900H CPU. --- CPU: ID 0xb06a2, Processor Type 0x0, Family 0x6, Model 0xba, Stepping 0x2 Northbridge: 8086:a706 (13th generation (Raptor Lake H family) Core Processor) Southbridge: 8086:519d (Raptor Lake) IGD: 8086:a7a0 (Intel(R) Iris Xe Graphics [RPL-P]) SBREG_BAR = 0xfd000000 (MEM) --- TEST=build/run inteltool on Erying SRMJ4 mainboard, verify PCI IDs not unknown, GPIOs dumped. Change-Id: I4cf3f419f103a1a7d4c6850f2257b7e7d45f3b18 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/79962/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 97e64e2..6491a94 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -180,6 +180,8 @@ "12th generation (Alder Lake P family) Core Processor"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8, "12th generation (Alder Lake P family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6, + "13th generation (Raptor Lake H family) Core Processor"}, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, @@ -414,6 +416,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C266, "C266" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_P, "Raptor Lake" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, @@ -572,6 +575,8 @@ "Intel(R) AlderLake-S GT1" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS, "Intel(R) UHD Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE, + "Intel(R) Iris Xe Graphics [RPL-P]" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 02ee147..07b9a72 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -388,6 +388,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6 0xa706 /* Raptorlake H 8+6 */ /* Intel GPUs */ #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 @@ -468,6 +469,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_4 0x4692 +#define PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE 0xa7a0 #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/79962?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cf3f419f103a1a7d4c6850f2257b7e7d45f3b18 Gerrit-Change-Number: 79962 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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