Attention is currently required from: Marek Maślanka.
Hello Jakub Czapiga,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79909?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/common/block: Add support for watchdog
......................................................................
soc/intel/common/block: Add support for watchdog
Implement watchdog for intel based platform by filling ACPI Watchdog
Action Table (WDAT) table.
The WDAT ACPI table encompasses essential watchdog functions, including:
- Setting and retrieving countdown/timeout values
- Starting and stopping the watchdog
- Pinging the watchdog
- Retrieving the cause of the last reboot, whether it was triggered by
the watchdog or another reason
The general purpose register TCO_MESSAGE1 stores the reason for the most
recent reboot rather than the original register TCO2_STS. This is
because the firmware must clear TCO2_STS, and it can't be reused for
storing this information for the operating system.
The watchdog is designed for use by the OS through certain defined
actions in the WDAT table. It relies on the ACPI Power Management Timer,
which may result in an increase in power consumption.
BUG=b:314260167
TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the
config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy
both firmware and kernel to the device. Trigger the watchdog by
performing the command: “cat > /dev/watchdog”. Wait approximately 30
seconds for the watchdog to reset the device.
Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1
Signed-off-by: Marek Maslanka <mmaslanka(a)google.com>
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/tco.h
M src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/pch/include/intelpch/smbus.h
4 files changed, 133 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79909/2
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Hello Fred Reitberger, Jason Glenesk, Matt DeVillier,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79984?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.c
......................................................................
soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.c
fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so
only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is
selected. Other files have FSP-specific parts too, but those will be
reworked in future patches.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373
---
M src/soc/amd/phoenix/Makefile.inc
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79984/2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email )
Change subject: device: Add support for multiple PCI segment groups
......................................................................
Patch Set 12: Code-Review+1
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Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79984?usp=email )
Change subject: soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.c
......................................................................
soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.c
fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so
only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is
selected. Other files have FSP-specific parts too, but those will be
reworked in in future patches.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373
---
M src/soc/amd/phoenix/Makefile.inc
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79984/1
diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc
index 03a38ad..0301cdc 100644
--- a/src/soc/amd/phoenix/Makefile.inc
+++ b/src/soc/amd/phoenix/Makefile.inc
@@ -21,7 +21,7 @@
verstage-y += espi_util.c
-romstage-y += fsp_m_params.c
+romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c
romstage-y += romstage.c
romstage-y += soc_util.c
@@ -30,7 +30,7 @@
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += fch.c
-ramstage-y += fsp_s_params.c
+ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += root_complex.c
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email )
Change subject: device: Add support for multiple PCI segment groups
......................................................................
Patch Set 12:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/79927/comment/c4d4ebee_1b7c2464 :
PS11, Line 98: depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256
> ah, there's should_run_oprom, so i won't have to mess with the yabel or the realmode oprom code
done
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Hello Arthur Heymans, Christian Walter, Cliff Huang, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: device: Add support for multiple PCI segment groups
......................................................................
device: Add support for multiple PCI segment groups
Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
---
M src/acpi/acpi.c
M src/arch/x86/mpspec.c
M src/device/Kconfig
M src/device/device.c
M src/device/device_const.c
M src/device/device_util.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pcix_device.c
M src/include/device/device.h
M src/include/device/pci_def.h
M src/include/device/pci_ops.h
M src/lib/smbios.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/genoa_poc/domain.c
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
19 files changed, 96 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/79927/12
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Change subject: device: Add support for multiple PCI segment groups
......................................................................
Patch Set 11:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/79927/comment/a3701113_1b84c6cd :
PS11, Line 98: depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256
> wasn't sure how to properly handle the other cases and haven't looked if there's some spec for the l […]
ah, there's should_run_oprom, so i won't have to mess with the yabel or the realmode oprom code
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