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Change subject: tree: More use accessor functions for struct region fields
......................................................................
Patch Set 2: Code-Review+1
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Hello Christian Walter, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Jason Glenesk, Julius Werner, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, Yu-Ping Wu, build bot (Jenkins),
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Change subject: security/tpm: resolve conflicts in TSS implementations
......................................................................
security/tpm: resolve conflicts in TSS implementations
No functional changes. Refactor code such that there won't be any
compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled
in. One might want to support both TPM families for example if TPM
is pluggable, in which case currently one has to update firmware along
with switching TPM device.
Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/tis.c
M src/security/tpm/Makefile.inc
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/tpm/tss/tcg-1.2/tss.c
M src/security/tpm/tss/tcg-2.0/tss.c
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
A src/security/tpm/tss/tss.c
M src/security/tpm/tss/vendor/cr50/cr50.c
A src/security/tpm/tss1.h
A src/security/tpm/tss2.h
M src/security/vboot/secdata_tpm.c
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/vendorcode/eltan/security/mboot/mboot.c
M src/vendorcode/google/chromeos/tpm2.c
15 files changed, 408 insertions(+), 295 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69160/28
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Hello Matt DeVillier, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries
......................................................................
intel tgl mainboards: Move PcieRpEnable option below dt entries
There is work being done on better integrating the root port entries
from the devicetree by hooking up the FSP option PcieRpEnable to them,
which supersedes the devicetree option.
Move the PcieRpEnable option below their related devicetree entries in
order to make the review easier when the option is removed. Create
devicetree entries in case of they don't exist yet.
Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
6 files changed, 46 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/79960/2
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Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/volteer/variants/voema/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79960/comment/1056b2fb_e89d7ae1 :
PS1, Line 103: device ref pcie_rp7 off
: register "PcieRpEnable[6]" = "0"
: end
> Right. The settings are mainly moved in order to make the review easier.
Acknowledged
https://review.coreboot.org/c/coreboot/+/79960/comment/c7069023_9cc6e248 :
PS1, Line 108: probe DB_SD SD_GL9755S
: probe DB_SD SD_RTS5261
: probe DB_SD SD_RTS5227S
: probe DB_SD SD_GL9750
: probe DB_SD SD_OZ711LV2LN
> Afaik it's only the same device for sconfig if it contains the exact same configuration as the one f […]
it shouldn't, especially when disabling a previously-enabled device. I'm not even sure it's valid as written
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Attention is currently required from: Balázs Vinarz, Mike Banon.
Hello Balázs Vinarz, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
......................................................................
util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
restore_agesa.sh reverts the opensource AGESA AMD boards removal
that happened after 5e8e911b7caee021faff96c4e82a77a42544ea62
commit (0 point of history, or 0 PoH) - by git-reverting:
1) the "bad commits" (marked as "CBF" = coreboot build failure)
- that either remove or break a code needed for our boards
2) the "unlucky commits" (marked as "GRF" = git revert failure)
- that are a roadblock for git-reverting the "bad commits"
Right now at 8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 (5464 PoH),
it takes 45 CBF git reverts - just 1% of 5464 commits since the
OSS AGESA removal! - making this removal look questionable and
the idea of opensource AGESA AMD boards restoration viable.
SUCCESSFUL BOOT TESTS for the opensource AGESA boards which I own
(Lenovo G505S - fam15 laptop, ASUS A88XM-E - fam15 desktop,
ASUS AM1I-A - fam16 desktop) :
8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 (5464 PoH) for Lenovo G505S
69ffebf5ccf123bc0b3fb28b485985af0597761d (3698 PoH) for ASUS A88XM-E
Change-Id: Ia97e80ffaad9459e54ff5cb01f20d9129241433c
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A util/scripts/restore_agesa.sh
1 file changed, 264 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/79838/2
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Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/volteer/variants/voema/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79960/comment/fd1265c4_c0018782 :
PS1, Line 103: device ref pcie_rp7 off
: register "PcieRpEnable[6]" = "0"
: end
> I assume this entry will go away once the PcieRpEnable is tied to the dt device status?
Right. The settings are mainly moved in order to make the review easier.
https://review.coreboot.org/c/coreboot/+/79960/comment/c20472cf_9590b684 :
PS1, Line 108: probe DB_SD SD_GL9755S
: probe DB_SD SD_RTS5261
: probe DB_SD SD_RTS5227S
: probe DB_SD SD_GL9750
: probe DB_SD SD_OZ711LV2LN
> why are you adding probe entries to a device that is off?
Afaik it's only the same device for sconfig if it contains the exact same configuration as the one from the upper levels. Otherwise it will conflict.
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Change subject: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
I can't submit this patch since I modified it. So either someone else gives +2 (which allows me to submit) or someone else submits it.
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Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/volteer/variants/voema/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79960/comment/ae431560_42d301ec :
PS1, Line 103: device ref pcie_rp7 off
: register "PcieRpEnable[6]" = "0"
: end
I assume this entry will go away once the PcieRpEnable is tied to the dt device status?
https://review.coreboot.org/c/coreboot/+/79960/comment/c3e608e5_2e0a85c0 :
PS1, Line 108: probe DB_SD SD_GL9755S
: probe DB_SD SD_RTS5261
: probe DB_SD SD_RTS5227S
: probe DB_SD SD_GL9750
: probe DB_SD SD_OZ711LV2LN
why are you adding probe entries to a device that is off?
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Change subject: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate
......................................................................
Patch Set 13: Code-Review+2
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Change subject: [RFC] region: Turn region_end() into an inclusive region_last()
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/spi/winbond.c:
https://review.coreboot.org/c/coreboot/+/79946/comment/755e9a54_8c3fbe1a :
PS5, Line 505: region_last(region) + 1
> Could this possibly lead to an overflow again?
Yes, it would be better to use `flash->size - 1`. I guess we shouldn't
expect regions bigger than a flash, but better safe than sorry.
OTOH, (just read the code again), it would need a 4GiB flash to make
a difference :)
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Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>
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