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Change subject: mb/arm/rdn2: Add support for Arm Neoverse N2
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/arm/rdn2/acpi.c:
https://review.coreboot.org/c/coreboot/+/79103/comment/baac55ce_60e65ca9 :
PS5, Line 29: platform_get_gicd_base
Why does it use GICv2 compatibility mode?
https://review.coreboot.org/c/coreboot/+/79103/comment/3a688efa_77195f6d :
PS5, Line 30: gicv
only needed on GICv2
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Change subject: mb/google/dedede/var/galtic: Correct the Memory Part Name
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Patch Set 4: Code-Review+2
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Change subject: mb/google/dedede/var/galtic: Correct the Memory Part Name
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79976/comment/5ddca145_251744a9 :
PS2, Line 7: Re-factor the Memory Setting
> Please make it in one line, probably `Correct the memory part name`
Done
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Hello Derek Huang, Ivan Chen, Karthik Ramasubramanian, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/dedede/var/galtic: Correct the Memory Part Name
......................................................................
mb/google/dedede/var/galtic: Correct the Memory Part Name
Repo sync code recently, run command as memtion in TEST and
found the changed for the auto-gen files.
Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR,
and no new for the used hex file.
BUG=b:320181366
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go JSL lp4x \
src/mainboard/google/dedede/variants/galtic/memory/ \
src/mainboard/google/dedede/variants/galtic/memory/\
mem_parts_used.txt"
Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc
M src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt
3 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79976/4
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Change subject: arch/riscv/Makefile.inc: Fix OpenSBI compilation
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Patch Set 1: Code-Review+2
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Change subject: drivers/uart/sifive.c: Fix divisor calculation
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/drivers/uart/sifive.c:
https://review.coreboot.org/c/coreboot/+/79951/comment/857919a4_59f37e2b :
PS1, Line 50: // according to FU740 manual:
please use C style comments `/*`
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Change subject: mb/google/dedede/var/galtic: Re-name the Memory Part Name K4U6E3S4AA-MGCR
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79976/comment/8d53d07f_e2a02594 :
PS2, Line 7: Re-factor the Memory Setting
> Done
Please make it in one line, probably `Correct the memory part name`
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Change subject: arch/riscv/boot.c: Add comment for clarity
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/arch/riscv/boot.c:
https://review.coreboot.org/c/coreboot/+/79949/comment/44b0f049_d1563ad7 :
PS1, Line 35: // tell OpenSBI to switch to Supervisor mode before jumping to payload
please use C style comments `/* `
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Change subject: arch/riscv: Add OPENSBI_FW_DYNAMIC_BOOT_HART option
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Patch Set 1: Code-Review+2
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Change subject: include/bootmem.h: Add comment
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Patch Set 1: Code-Review+2
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