coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

1 participants
3824 discussions

[XS] Change in coreboot[master]: LinuxBoot/Makefile: Add check if initramfs needs to be built
by Frans Hendriks (Code Review) 01 Sep '23

01 Sep '23

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77607?usp=email ) Change subject: LinuxBoot/Makefile: Add check if initramfs needs to be built ...................................................................... LinuxBoot/Makefile: Add check if initramfs needs to be built initramfs is built always, ignoring CONFIG_LINUXBOOT_BUILD_INITRAMFS Built initramfs only is CONFIG_LINUXBOOT_BUILD_INITRAMFS is set BUG = N/A TEST = Built and boot facebook monolith Change-Id: I0d575ff7528fceb06b5394642527713bb071c8b3 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/77607/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 397ffdc..29339f14 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -21,7 +21,11 @@ include targets/u-root.mk endif +ifeq ($(CONFIG_LINUXBOOT_BUILD_INITRAMFS),y) build/initramfs: $(CONFIG_LINUXBOOT_INITRAMFS_PATH) | build +else +build/initramfs: +endif ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y) xz --keep --force --check=crc32 --lzma2=dict=1MiB $(CONFIG_LINUXBOOT_INITRAMFS_PATH) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/77607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d575ff7528fceb06b5394642527713bb071c8b3 Gerrit-Change-Number: 77607 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: LinuxBoot/Makefile: initramfs not build for bzImage
by Frans Hendriks (Code Review) 01 Sep '23

01 Sep '23

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77606?usp=email ) Change subject: LinuxBoot/Makefile: initramfs not build for bzImage ...................................................................... LinuxBoot/Makefile: initramfs not build for bzImage initramfs is not build when bzImage is selected Add build/initramfs dependency to build/bzImage BUG = N/A TEST = Built and boot facebook monolith Change-Id: I002202a0340347e78ce22024761d997605bd3f72 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/77606/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 397ffdc..1362c28 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -29,7 +29,7 @@ ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y) -build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build +build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage build/initramfs | build cp $< $@ else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/77606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002202a0340347e78ce22024761d997605bd3f72 Gerrit-Change-Number: 77606 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH
by Frans Hendriks (Code Review) 01 Sep '23

01 Sep '23

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77605?usp=email ) Change subject: LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH ...................................................................... LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH The using config string for amd64 as UROOT_ARCH contains typo Correct using CONFIG_LINUXBOOT_X86_64 BUG = N/A TEST = Build boot facebook monolith Change-Id: I6cfefb3f8e4e61bd56ca0fe3239000db8c07b088 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M payloads/external/LinuxBoot/targets/u-root.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77605/1 diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index fff79df..90b48ea 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -3,7 +3,7 @@ uroot_package = github.com/u-root/u-root uroot_build = build/go/src/$(uroot_package) -UROOT_ARCH-$(CONFIG_LIBUXBOOT_X86_64) = amd64 +UROOT_ARCH-$(CONFIG_LINUXBOOT_X86_64) = amd64 UROOT_ARCH-$(CONFIG_LINUXBOOT_X86) = 386 UROOT_ARCH-$(CONFIG_LINUXBOOT_ARM64) = arm64 UROOT_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv64 -- To view, visit https://review.coreboot.org/c/coreboot/+/77605?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfefb3f8e4e61bd56ca0fe3239000db8c07b088 Gerrit-Change-Number: 77605 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69825?usp=email ) Change subject: mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig ...................................................................... mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig Add support for FSP ASPM and Clock PM configuration based on Kconfig options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some use cases it may be desirable to disable ASPM and Clock PM to achieve more deterministic and higher performance of PCIe devices. TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all PCIe devices are still working and ASPM and Clock PM capabilities are not present on the PCIe Root Ports. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825 Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/gpio.h M src/mainboard/msi/ms7d25/mainboard.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c 4 files changed, 188 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index c76b01b..f0c8d2d 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -99,8 +99,6 @@ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" "PCI_E1" "SlotDataBusWidth16X" @@ -112,8 +110,6 @@ .clk_src = 9, .clk_req = 9, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" @@ -142,8 +138,6 @@ .clk_src = 10, .clk_req = 10, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "PCI_E2" "SlotDataBusWidth1X" @@ -153,8 +147,6 @@ .clk_src = 17, .clk_req = 17, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E4" "SlotDataBusWidth1X" @@ -164,8 +156,6 @@ register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 12, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" end device ref pcie_rp4 off end @@ -175,8 +165,6 @@ .clk_src = 15, .clk_req = 15, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E3" "SlotDataBusWidth4X" @@ -187,8 +175,6 @@ .clk_src = 13, .clk_req = 13, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_3" "SlotDataBusWidth4X" @@ -211,8 +197,6 @@ .clk_src = 14, .clk_req = 14, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_4" "SlotDataBusWidth4X" @@ -223,8 +207,6 @@ .clk_src = 8, .clk_req = 8, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_2" "SlotDataBusWidth4X" diff --git a/src/mainboard/msi/ms7d25/gpio.h b/src/mainboard/msi/ms7d25/gpio.h index 210c43d..62625c0 100644 --- a/src/mainboard/msi/ms7d25/gpio.h +++ b/src/mainboard/msi/ms7d25/gpio.h @@ -699,3 +699,110 @@ /* GPP_D23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), }; + +/* PCIe CLK REQs as per devicetree.cb */ +static const struct pad_config clkreq_disabled_table[] = { + /* GPP_J9 - SRCCLKREQ17# */ + PAD_NC(GPP_J9, NONE), + /* GPP_H2 - SRCCLKREQ8# */ + PAD_NC(GPP_H2, NONE), + /* GPP_H3 - SRCCLKREQ9# */ + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - SRCCLKREQ10# */ + PAD_NC(GPP_H4, NONE), + /* GPP_H6 - SRCCLKREQ12# */ + PAD_NC(GPP_H6, NONE), + /* GPP_H7 - SRCCLKREQ13# */ + PAD_NC(GPP_H7, NONE), + /* GPP_H8 - SRCCLKREQ14# */ + PAD_NC(GPP_H8, NONE), + /* GPP_H9 - SRCCLKREQ15# */ + PAD_NC(GPP_H9, NONE), + /* GPP_D0 - SRCCLKREQ0# */ + PAD_NC(GPP_D0, NONE), + + /* CPU PCIe CLKREQ virtual wire message buses */ + _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + + _PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), + _PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), +}; diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index 7e86533..f124449 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -66,6 +66,21 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + uint8_t aspm, aspm_l1; + + /* ASPM L1 sub-states require CLKREQ, so CLK_PM should be enabled as well */ + if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM)) + aspm_l1 = 2; // 2 - L1.1 and L1.2 + else + aspm_l1 = 0; + + if (CONFIG(PCIEXP_ASPM)) { + aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s + } else { + aspm = 0; + aspm_l1 = 0; + } + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm)); memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating)); @@ -91,13 +106,13 @@ params->PcieRpPmSci[20] = 1; // M2_4 params->PcieRpPmSci[24] = 1; // M2_2 - params->PcieRpMaxPayload[0] = 1; // PCI_E2 - params->PcieRpMaxPayload[1] = 1; // PCI_E4 - params->PcieRpMaxPayload[2] = 1; // Ethernet - params->PcieRpMaxPayload[4] = 1; // PCI_E3 - params->PcieRpMaxPayload[8] = 1; // M2_3 - params->PcieRpMaxPayload[20] = 1; // M2_4 - params->PcieRpMaxPayload[24] = 1; // M2_2 + params->PcieRpMaxPayload[0] = 1; // PCI_E2 + params->PcieRpMaxPayload[1] = 1; // PCI_E4 + params->PcieRpMaxPayload[2] = 1; // Ethernet + params->PcieRpMaxPayload[4] = 1; // PCI_E3 + params->PcieRpMaxPayload[8] = 1; // M2_3 + params->PcieRpMaxPayload[20] = 1; // M2_4 + params->PcieRpMaxPayload[24] = 1; // M2_2 params->CpuPcieRpTransmitterHalfSwing[0] = 1; // M2_1 params->CpuPcieRpTransmitterHalfSwing[1] = 1; // PCI_E1 @@ -109,12 +124,32 @@ params->PcieRpTransmitterHalfSwing[20] = 1; // M2_4 params->PcieRpTransmitterHalfSwing[24] = 1; // M2_2 - params->PcieRpEnableCpm[0] = 1; // PCI_E2 - params->PcieRpEnableCpm[1] = 1; // PCI_E4 - params->PcieRpEnableCpm[4] = 1; // PCI_E3 - params->PcieRpEnableCpm[8] = 1; // M2_3 - params->PcieRpEnableCpm[20] = 1; // M2_4 - params->PcieRpEnableCpm[24] = 1; // M2_2 + params->CpuPcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // M2_1 + params->CpuPcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E1 + params->PcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // PCI_E2 + params->PcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E4 + params->PcieRpEnableCpm[4] = CONFIG(PCIEXP_CLK_PM); // PCI_E3 + params->PcieRpEnableCpm[8] = CONFIG(PCIEXP_CLK_PM); // M2_3 + params->PcieRpEnableCpm[20] = CONFIG(PCIEXP_CLK_PM); // M2_4 + params->PcieRpEnableCpm[24] = CONFIG(PCIEXP_CLK_PM); // M2_2 + + params->CpuPcieRpL1Substates[0] = aspm_l1; // M2_1 + params->CpuPcieRpL1Substates[1] = aspm_l1; // PCI_E1 + params->PcieRpL1Substates[0] = aspm_l1; // PCI_E2 + params->PcieRpL1Substates[1] = aspm_l1; // PCI_E4 + params->PcieRpL1Substates[4] = aspm_l1; // PCI_E3 + params->PcieRpL1Substates[8] = aspm_l1; // M2_3 + params->PcieRpL1Substates[20] = aspm_l1; // M2_4 + params->PcieRpL1Substates[24] = aspm_l1; // M2_2 + + params->CpuPcieRpAspm[0] = aspm; // M2_1 + params->CpuPcieRpAspm[1] = aspm; // PCI_E1 + params->PcieRpAspm[0] = aspm; // PCI_E2 + params->PcieRpAspm[1] = aspm; // PCI_E4 + params->PcieRpAspm[4] = aspm; // PCI_E3 + params->PcieRpAspm[8] = aspm; // M2_3 + params->PcieRpAspm[20] = aspm; // M2_4 + params->PcieRpAspm[24] = aspm; // M2_2 params->PcieRpAcsEnabled[0] = 1; // PCI_E2 params->PcieRpAcsEnabled[1] = 1; // PCI_E4 @@ -124,17 +159,15 @@ params->PcieRpAcsEnabled[20] = 1; // M2_4 params->PcieRpAcsEnabled[24] = 1; // M2_2 - params->CpuPcieRpEnableCpm[0] = 1; // M2_1 - params->CpuPcieClockGating[0] = 1; - params->CpuPciePowerGating[0] = 1; + params->CpuPcieClockGating[0] = CONFIG(PCIEXP_CLK_PM); + params->CpuPciePowerGating[0] = CONFIG(PCIEXP_CLK_PM); params->CpuPcieRpMultiVcEnabled[0] = 1; params->CpuPcieRpPeerToPeerMode[0] = 1; params->CpuPcieRpMaxPayload[0] = 2; // 512B params->CpuPcieRpAcsEnabled[0] = 1; - params->CpuPcieRpEnableCpm[1] = 1; // PCI_E1 - params->CpuPcieClockGating[1] = 1; - params->CpuPciePowerGating[1] = 1; + params->CpuPcieClockGating[1] = CONFIG(PCIEXP_CLK_PM); + params->CpuPciePowerGating[1] = CONFIG(PCIEXP_CLK_PM); params->CpuPcieRpPeerToPeerMode[1] = 1; params->CpuPcieRpMaxPayload[1] = 2; // 512B params->CpuPcieRpAcsEnabled[1] = 1; diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 833ff1a..3ced7f8 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -5,9 +5,13 @@ #include <fsp/api.h> #include <soc/romstage.h> #include <soc/meminit.h> +#include <string.h> #include "gpio.h" +#define FSP_CLK_NOTUSED 0xFF +#define FSP_CLK_FREE_RUNNING 0x80 + static const struct mb_cfg ddr4_mem_config = { .type = MEM_TYPE_DDR4, /* According to DOC #573387 rcomp values no longer have to be provided */ @@ -49,11 +53,30 @@ }, }; +static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg) +{ + memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage)); + memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq)); + + /* PCIe CLK SRCes as per devicetree.cb */ + m_cfg->PcieClkSrcUsage[0] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[8] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[9] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[10] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[13] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[14] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[15] = FSP_CLK_FREE_RUNNING; + m_cfg->PcieClkSrcUsage[17] = FSP_CLK_FREE_RUNNING; + + gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table)); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { - memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1; - memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 1; - memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM); + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM); + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM); memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented memupd->FspmConfig.DmiAspm = 0; memupd->FspmConfig.DmiAspmCtrl = 0; @@ -67,4 +90,7 @@ memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + if (!CONFIG(PCIEXP_CLK_PM)) + disable_pcie_clock_requests(&memupd->FspmConfig); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Gerrit-Change-Number: 69825 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: Fix OpenSBI loading with working payload
by Daniel Maslowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Ayan Agrawal, Paul Menzel, Philipp Hug, ron minnich. Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76572?usp=email ) Change subject: Fix OpenSBI loading with working payload ...................................................................... Patch Set 9: Code-Review+1 (2 comments) Patchset: PS9: I'm not too great an expert with this whole linker and build setup stuff. Added Arthur to take another look. =) File src/mainboard/emulation/qemu-riscv/memlayout.ld: https://review.coreboot.org/c/coreboot/+/76572/comment/f283f1c9_7735a946 : PS9, Line 23: #if ENV_RAMSTAGE > Why remove the condition here? If coreboot is configured not to build a RAM stage, the pieces below […] Huh... I realize that this part had always been before RAM stage. It's weird. Sorry! -- To view, visit https://review.coreboot.org/c/coreboot/+/76572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie810c2d8f739697b17a7e707bd9ee858e3ebc8f2 Gerrit-Change-Number: 76572 Gerrit-PatchSet: 9 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 13:09:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: Fix OpenSBI loading with working payload
by Daniel Maslowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Ayan Agrawal, Paul Menzel, Philipp Hug, ron minnich. Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76572?usp=email ) Change subject: Fix OpenSBI loading with working payload ...................................................................... Patch Set 9: (1 comment) File src/mainboard/emulation/qemu-riscv/memlayout.ld: https://review.coreboot.org/c/coreboot/+/76572/comment/bbc48d9a_c3d7f972 : PS9, Line 23: #if ENV_RAMSTAGE Why remove the condition here? If coreboot is configured not to build a RAM stage, the pieces below must not be applied. -- To view, visit https://review.coreboot.org/c/coreboot/+/76572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie810c2d8f739697b17a7e707bd9ee858e3ebc8f2 Gerrit-Change-Number: 76572 Gerrit-PatchSet: 9 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 12:52:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: amdfwtool: Add FW type FUSE_CHAIN in the config file
by Felix Held (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Bao Zheng, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Varshit Pandya, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77506?usp=email ) Change subject: amdfwtool: Add FW type FUSE_CHAIN in the config file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Gerrit-Change-Number: 77506 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 11:49:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: amd/soc/common: Use relative offset for AMDFW
by Felix Held (Code Review) 01 Sep '23

01 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72961?usp=email ) Change subject: amd/soc/common: Use relative offset for AMDFW ...................................................................... amd/soc/common: Use relative offset for AMDFW The amdfw.rom is mostly in region COREBOOT. Calculate the relative address as the CBFS module address. That is for future 32M flash size support. TEST=binary identical test on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst This commit is part of a series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72961 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/Makefile.inc 1 file changed, 9 insertions(+), 3 deletions(-) Approvals: Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index e388305..78ab4ff 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -41,13 +41,19 @@ amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) -$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom +$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h cp $< $@ +amdfw_region_start=$(subst $(spc),,FMAP_SECTION_$(call regions-for-file,apu/amdfw)_START) +amdfw_offset=$(call int-subtract, \ + $(CONFIG_AMD_FWM_POSITION) \ + $(call int-subtract, \ + $(call get_fmap_value,$(amdfw_region_start)) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START))) + add_bootblock = \ $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ - -b $(call int-add, \ - $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) + -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/72961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be Gerrit-Change-Number: 72961 Gerrit-PatchSet: 19 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: amd/soc/common: Use relative offset for AMDFW
by Felix Held (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72961?usp=email ) Change subject: amd/soc/common: Use relative offset for AMDFW ...................................................................... Patch Set 18: (1 comment) Patchset: PS15: > https://review.coreboot.org/c/coreboot/+/72939 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be Gerrit-Change-Number: 72961 Gerrit-PatchSet: 18 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 01 Sep 2023 11:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Felix Held (Code Review) 01 Sep '23

01 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72939?usp=email ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... util/amdfwtool: Deal with psp position in flash offset directly It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/chausie/Kconfig M src/mainboard/amd/majolica/Kconfig M src/mainboard/amd/mandolin/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/zork/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/Makefile.inc M src/soc/amd/common/block/include/amdblocks/psp_efs.h M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/fch.c 23 files changed, 94 insertions(+), 287 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index 052d5d7..86e18f5 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -15,6 +15,8 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select AMD_FWM_POSITION_C20000_DEFAULT if CHROMEOS + select AMD_FWM_POSITION_820000_DEFAULT if !CHROMEOS select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED config FMDFILE @@ -27,13 +29,6 @@ config MAINBOARD_PART_NUMBER default "CHAUSIE" -config AMD_FWM_POSITION_INDEX - int - default 3 if CHROMEOS - default 4 - help - TODO: might need to be adapted for better placement of files in cbfs - config CHAUSIE_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index 937d0ba..a167dff 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -10,6 +10,8 @@ select AMD_SOC_CONSOLE_UART select PSP_INIT_ESPI select MAINBOARD_HAS_CHROMEOS + select AMD_FWM_POSITION_C20000_DEFAULT if CHROMEOS + select AMD_FWM_POSITION_820000_DEFAULT if !CHROMEOS config FMDFILE default "src/mainboard/amd/majolica/chromeos.fmd" if CHROMEOS @@ -21,13 +23,6 @@ config MAINBOARD_PART_NUMBER default "MAJOLICA" -config AMD_FWM_POSITION_INDEX - int - default 3 if CHROMEOS - default 4 - help - TODO: might need to be adapted for better placement of files in cbfs - config MAJOLICA_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 50b3e5d..20ff1c6 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -12,6 +12,8 @@ select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD + select AMD_FWM_POSITION_420000_DEFAULT if BOARD_AMD_MANDOLIN + select AMD_FWM_POSITION_820000_DEFAULT if BOARD_AMD_CEREME config FMDFILE default "src/mainboard/amd/mandolin/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" @@ -67,13 +69,6 @@ bool default y -config AMD_FWM_POSITION_INDEX - int - default 3 if BOARD_AMD_MANDOLIN - default 4 if BOARD_AMD_CEREME - help - TODO: might need to be adapted for better placement of files in cbfs - config MANDOLIN_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 8ddd3b1..e66419b 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 + select AMD_FWM_POSITION_C20000_DEFAULT config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -81,12 +82,6 @@ default "Nipperkin" if BOARD_GOOGLE_NIPPERKIN default "Dewatt" if BOARD_GOOGLE_DEWATT -config AMD_FWM_POSITION_INDEX - int - default 3 - help - TODO: might need to be adapted for better placement of files in cbfs - config DRIVER_TPM_I2C_BUS hex default 0x03 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 92896e9..a4a7742 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -35,6 +35,7 @@ select HAVE_EM100_SUPPORT select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 + select AMD_FWM_POSITION_F20000_DEFAULT if BOARD_GOOGLE_BASEBOARD_KAHLEE @@ -104,10 +105,6 @@ config CHROMEOS select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE -config AMD_FWM_POSITION_INDEX - int - default 1 - config DRIVER_TPM_I2C_BUS hex default 0x01 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index dc681e8..44ecfc4 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -5,10 +5,6 @@ if BOARD_GOOGLE_BASEBOARD_SKYRIM -config AMD_FWM_POSITION_INDEX - int - default 3 - config BOARD_SPECIFIC_OPTIONS def_bool y select ACPI_S1_NOT_SUPPORTED @@ -49,6 +45,7 @@ select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE + select AMD_FWM_POSITION_C20000_DEFAULT config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index d01b023..1abefb1 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -51,6 +51,7 @@ select DRIVERS_USB_ACPI select DRIVERS_UART_ACPI select DRIVERS_GENERIC_BAYHUB_LV2 + select AMD_FWM_POSITION_E20000_DEFAULT config ELOG_BOOT_COUNT_CMOS_OFFSET int @@ -126,10 +127,6 @@ # Use default libpayload config select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE -config AMD_FWM_POSITION_INDEX - int - default 2 - config DRIVER_TPM_I2C_BUS hex default 0x03 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2c6e949..d10d857 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -322,39 +322,6 @@ menu "PSP Configuration Options" -config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string default "src/soc/amd/cezanne/fw.cfg" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 70170ef..7b6c998 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -40,21 +40,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+ -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -CEZANNE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -222,7 +213,7 @@ $(OPT_APOB_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ - --location $(call _tohex,$(CEZANNE_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --multilevel \ --output $@ diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index c5d952f..e388305 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -47,9 +47,8 @@ add_bootblock = \ $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ -b $(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) + endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) ifeq ($(CONFIG_VBOOT_GSCVD),y) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index a930bc9..02f027c 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -6,7 +6,7 @@ #include <types.h> -#define EFS_OFFSET (CONFIG_ROM_SIZE - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000) +#define EFS_OFFSET CONFIG_AMD_FWM_POSITION #define EMBEDDED_FW_SIGNATURE 0x55aa55aa diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index d59e6fc..68d6861 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -55,3 +55,71 @@ default n help Select this config to indicate SoC includes Hardware Security Processor(HSP). + +config AMD_FWM_POSITION_20000_DEFAULT + bool "0x20000" + +config AMD_FWM_POSITION_420000_DEFAULT + bool "0x420000" + +config AMD_FWM_POSITION_820000_DEFAULT + bool "0x820000" + +config AMD_FWM_POSITION_C20000_DEFAULT + bool "0xC20000" + +config AMD_FWM_POSITION_E20000_DEFAULT + bool "0xE20000" + +config AMD_FWM_POSITION_F20000_DEFAULT + bool "0xF20000" + +config AMD_FWM_POSITION_FA0000_DEFAULT + bool "0xFA0000" + +choice AMD_FWM_POSITION_CHOICE + prompt "AMD FW position" + default AMD_FWM_POSITION_420000 if AMD_FWM_POSITION_420000_DEFAULT + default AMD_FWM_POSITION_820000 if AMD_FWM_POSITION_820000_DEFAULT + default AMD_FWM_POSITION_C20000 if AMD_FWM_POSITION_C20000_DEFAULT + default AMD_FWM_POSITION_E20000 if AMD_FWM_POSITION_E20000_DEFAULT + default AMD_FWM_POSITION_F20000 if AMD_FWM_POSITION_F20000_DEFAULT + default AMD_FWM_POSITION_FA0000 if AMD_FWM_POSITION_FA0000_DEFAULT + default AMD_FWM_POSITION_20000 + help + Set the position on flash offset where the AMD FW needs to be. + This position is relative to a 16MB flash window. If the flash + size is smaller than 16MB it gets mapped at the top of that window. + +config AMD_FWM_POSITION_20000 + bool "0x20000" + +config AMD_FWM_POSITION_420000 + bool "0x420000" + +config AMD_FWM_POSITION_820000 + bool "0x820000" + +config AMD_FWM_POSITION_C20000 + bool "0xC20000" + +config AMD_FWM_POSITION_E20000 + bool "0xE20000" + +config AMD_FWM_POSITION_F20000 + bool "0xF20000" + +config AMD_FWM_POSITION_FA0000 + bool "0xFA0000" + +endchoice + +config AMD_FWM_POSITION + hex + default 0x20000 if AMD_FWM_POSITION_20000 + default 0x420000 if AMD_FWM_POSITION_420000 + default 0x820000 if AMD_FWM_POSITION_820000 + default 0xc20000 if AMD_FWM_POSITION_C20000 + default 0xe20000 if AMD_FWM_POSITION_E20000 + default 0xf20000 if AMD_FWM_POSITION_F20000 + default 0xfa0000 if AMD_FWM_POSITION_FA0000 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index b51cff3..98761a8 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -300,39 +300,6 @@ menu "PSP Configuration Options" -config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/glinda/fw.cfg" diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 7d37e6b..e079c4b 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -44,19 +44,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+ -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -# Fixed EFS location -GLINDA_FWM_POSITION=0xff020000 - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -240,7 +233,7 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ - --location $(call _tohex,$(GLINDA_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 189c6b9..7497ced 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -342,39 +342,6 @@ menu "PSP Configuration Options" -config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/mendocino/fw.cfg" diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index fb58278..41ac61b 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -43,21 +43,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+ -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -MENDOCINO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - # 0x80 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x80 @@ -265,7 +256,7 @@ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ $(OPT_MANIFEST) \ - --location $(call _tohex,$(MENDOCINO_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_CBFS_VERIFICATION)$(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),yy) diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 6bed749..7f6f879 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -312,23 +312,6 @@ menu "PSP Configuration Options" -config AMD_FWM_POSITION_INDEX - int - default 5 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/phoenix/fw.cfg" diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 852934f..344ece4 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -47,19 +47,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+ -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -# Fixed EFS location -PHOENIX_FWM_POSITION=0xff020000 - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -269,7 +262,7 @@ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ $(OPT_MANIFEST) \ - --location $(call _tohex,$(PHOENIX_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_AMDFW_SPLIT),y) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9051b43..f4b356c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -347,39 +347,6 @@ menu "PSP Configuration Options" -config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string default "src/soc/amd/picasso/fw.cfg" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6a44c6a..4085274 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -46,21 +46,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+ -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -PICASSO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -240,7 +231,7 @@ $(OPT_APOB0_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ - --location $(call _tohex,$(PICASSO_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 6091dce..9af7455 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -322,39 +322,6 @@ option to manually attach the generated amdfw.rom outside of cbfs. The location is selected by the FWM position. -config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config DIMM_SPD_SIZE default 512 # DDR4 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 5c0a312..47bdf0f 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -64,7 +64,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi # ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | # +-----------+---------------+----------------+------------+ @@ -72,11 +71,6 @@ # +-----------+ # # EC ROM should be 64K aligned. -STONEYRIDGE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - ### 0 FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') @@ -138,26 +132,24 @@ $(OPT_DEBUG_AMDFWTOOL) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(call _tohex,$(STONEYRIDGE_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -# Calculate firmware position inside the ROM -STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ - $(call int-subtract, $(CONFIG_ROM_SIZE) \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) - $(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(STONEYRIDGE_FWM_ROM_POSITION)" + "$(CONFIG_AMD_FWM_POSITION)" dd if=$(obj)/amdfw.rom \ of=$< conv=notrunc bs=1 \ - seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + seek=$(CONFIG_AMD_FWM_POSITION) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +STONEYRIDGE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + 1 \ + $(CONFIG_AMD_FWM_POSITION)) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c index 9680fb2..176c263 100644 --- a/src/soc/amd/stoneyridge/fch.c +++ b/src/soc/amd/stoneyridge/fch.c @@ -151,7 +151,7 @@ uintptr_t fwaddr; size_t fwsize; - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + amdfw_rom = 4ull * GiB - CONFIG_ROM_SIZE + CONFIG_AMD_FWM_POSITION; xhci_fw = read32p(amdfw_rom + XHCI_FW_SIG_OFFSET); fwaddr = 2 + read16p(xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE); -- To view, visit https://review.coreboot.org/c/coreboot/+/72939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Gerrit-Change-Number: 72939 Gerrit-PatchSet: 29 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2023