coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[master]: mb/google/rex: Enable uGOP early graphics support
by Jérémy Compostella (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Hello Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77522?usp=email to look at the new patch set (#2). Change subject: mb/google/rex: Enable uGOP early graphics support ...................................................................... mb/google/rex: Enable uGOP early graphics support It enables the use of the uGOP PEIM driver to display text information during pre-memory boot long time operations such as memory training or CSME update. Since Write-Protected Read-Only region is almost full, this feature cannot be currently included WP_RO (aka. COREBOOT) region. BUG=b:279173035 TEST=Memory training and CSME update use-cases display an on-screen message with the exclusion of the recovery flow. Change-Id: I992ab2c1ff2f9e9d4bc0bd1f2f076da6ad1c3a84 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/77522/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992ab2c1ff2f9e9d4bc0bd1f2f076da6ad1c3a84 Gerrit-Change-Number: 77522 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: Inform user of memory training and CSME update
by Jérémy Compostella (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Pratikkumar V Prajapati, Subrata Banik, Tarun, Tarun Tuli. Hello Anil Kumar K, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Pratikkumar V Prajapati, Subrata Banik, Tarun, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77232?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake: Inform user of memory training and CSME update ...................................................................... soc/intel/meteorlake: Inform user of memory training and CSME update This patch introduces sign-of-life support for the following two use-cases: 1. Memory Training in FSP-M 2. CSME update BUG=b:279173035 TEST=If `CONFIG_UGOP_EARLY_GRAPHICS' is set to y, we observe a text message on screen during Memory training and CSME update. Change-Id: I358b54c71533f3b905b68d7ac0710d2337ce451d Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/romstage/Makefile.inc M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/romstage/romstage.c A src/soc/intel/meteorlake/romstage/ux.c A src/soc/intel/meteorlake/romstage/ux.h 6 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/77232/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/77232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I358b54c71533f3b905b68d7ac0710d2337ce451d Gerrit-Change-Number: 77232 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: vendorcode/intel: Add uGOP support
by Jérémy Compostella (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Jérémy Compostella. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77231?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vendorcode/intel: Add uGOP support ...................................................................... vendorcode/intel: Add uGOP support This patch introduces code to load and execute uGOP (microGOP). uGOP is a pre-memory Pre-EFI Initialization Module (PEIM) capable of bringing graphics in VGA legacy mode. This a version of the Intel Graphics PEIM driver usually included in FSP silicon and generally referred as the GOP (Graphics Output Protocol) driver. Compared to GOP, uGOP is designed to run in pre-memory environment and therefor can be use to provide on screen information in pre-memory coreboot stages. uGOP dependency to the PEI environment is limited to: 1. InstallPpi() to install uGOP interfaces 2. LocatePpi() to find optional protocols 3. AllocatePool() to perform some dynamic memory allocation 4. CreateHob() and GetHobList() to handle global variables 5. ReportStatusCode() to report debug information These services are implemented in a very simple fashion in pei.c. pei.c also installs the PEI services pointer in the architecture size word immediately preceding the Interrupt Descriptor Table (IDT) to comply with Platform Initialization (PI) specification 5.4 PEI Services Table Retrieval. This patch introduces the `MAINBOARD_USE_UGOP' choice option for to enable this feature along with the following additional settings: - CONFIG_UGOP_FILE: uGOP PEIM binary path and filename - CONFIG_UGOP_CBFS: The filename of the uGOP PEIM binary in CBFS. - CONFIG_UGOP_ALIGNMENT: uGOP binary alignment in CBFS - CONFIG_UGOP_LIMIT_TO_REGIONS: To restrict uGOP to certain regions. This options can be used to restrict the regions in which the uGOP PEIM binary is included. For instance, it can be used to exclude uGOP support in WP_RO region. - CONFIG_UGOP_REGIONS: This options specifies in which region(s) the uGOP PEIM binary should be included. Example: FW_MAIN_A,FW_MAIN_B BUG=b:279173035 TEST=If MAINBOARD_HAS_UGOP is set to y, ugop.c and pei.c are compiled and the ugop.efi is included in CBFS. Change-Id: I66ae5f1948474330bfa41c42cda7cc0738f7b9cd Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- A Documentation/soc/intel/ugop/code-flow.svg A Documentation/soc/intel/ugop/ugop.md M src/arch/x86/car.ld M src/device/Kconfig M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc M src/soc/intel/common/block/graphics/early_graphics.c M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.inc A src/vendorcode/intel/ugop/Kconfig A src/vendorcode/intel/ugop/Makefile.inc A src/vendorcode/intel/ugop/pei.c A src/vendorcode/intel/ugop/pei.h A src/vendorcode/intel/ugop/ugop.c 14 files changed, 759 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/77231/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/77231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66ae5f1948474330bfa41c42cda7cc0738f7b9cd Gerrit-Change-Number: 77231 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Makefile.inc: Support FILENAME-REGION-compression CBFS flag
by Jérémy Compostella (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77230?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Makefile.inc: Support FILENAME-REGION-compression CBFS flag ...................................................................... Makefile.inc: Support FILENAME-REGION-compression CBFS flag The `FILENAME-REGION-compression' CBFS flag allows to specify a compression algorithm per REGION. Similarly, to `-align' or `-position', it overrides the `FILENAME-compression' flag for a particular `REGION'. It can be use to set the compression to `none' for a particular region in which the file is going to be used in pre-memory stages without alterating the more desired compressed version for other regions. BUG=b:279173035 TEST=Verified that with `vtb.bin-COREBOOT-compression := none' the vbt.bin in the COREBOOT region is not compressed. Change-Id: I4e3b827407aeca60f27270ee5d3fa606047a80d5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M Documentation/getting_started/build_system.md M Makefile.inc 2 files changed, 17 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/77230/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/77230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3b827407aeca60f27270ee5d3fa606047a80d5 Gerrit-Change-Number: 77230 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/crossgcc: Update binutils from 2.40 to 2.41
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76852?usp=email ) Change subject: util/crossgcc: Update binutils from 2.40 to 2.41 ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182493 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182491 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182490 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182489 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182488 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182487 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182486 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182485 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/182484 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182483 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/182482 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182481 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182480 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182479 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182478 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182477 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c985974e2eeea1329b2dbb232711c72b0bd99bc Gerrit-Change-Number: 76852 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 01 Sep 2023 18:20:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77375?usp=email ) Change subject: crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1 ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182510 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182508 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182507 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182506 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182505 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182504 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182503 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182502 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182500 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/182499 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182498 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182497 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182496 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182495 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182494 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/77375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb3630bf5e8a56ddcf6102faffde568134accc9 Gerrit-Change-Number: 77375 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 18:06:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/x11-lga1151-series: Add x11ssw-f
by Kieran Kunhya (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Kieran Kunhya, Michael Niewöhner. Hello Michael Niewöhner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77610?usp=email to look at the new patch set (#2). Change subject: mb/x11-lga1151-series: Add x11ssw-f ...................................................................... mb/x11-lga1151-series: Add x11ssw-f Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 Signed-off-by: Kieran Kunhya <kieran(a)kunhya.com> --- M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio_early.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 8 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/77610/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 Gerrit-Change-Number: 77610 Gerrit-PatchSet: 2 Gerrit-Owner: Kieran Kunhya <kieran(a)kunhya.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kieran Kunhya <kieran(a)kunhya.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/x11-lga1151-series: Add x11ssw-f
by Kieran Kunhya (Code Review) 01 Sep '23

01 Sep '23

Kieran Kunhya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77610?usp=email ) Change subject: mb/x11-lga1151-series: Add x11ssw-f ...................................................................... mb/x11-lga1151-series: Add x11ssw-f Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 --- M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md A Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/board_info.txt A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio_early.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 8 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/77610/1 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 394e0a98..109885c 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -9,6 +9,7 @@ - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) - [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md) - [X11SSM-F](x11ssm-f/x11ssm-f.md) +- [X11SSW-F](x11ssw-f/x11ssw-f.md) ## Required proprietary blobs diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md new file mode 100644 index 0000000..81182e5 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md @@ -0,0 +1,76 @@ +# Supermicro X11SSW-F + +This section details how to run coreboot on the [Supermicro X11SSW-F]. + +## Flashing coreboot + +Flashing was performed through the BMC web interface, when a valid license was entered. + +## Tested and working + +- SeaBIOS Payload loading Ubuntu 22.04 +- ECC ram (Linux' ie31200 driver works) +- USB ports +- Ethernet +- SATA ports +- RS232 external +- Left PCIe slot +- BMC (IPMI) +- VGA on Aspeed + +## Untested +- Right PCIe slot +- NVMe +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- LNXTHERM missing +- S3 resume not working + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x16 (Left Riser) | +| | 1x 3.0 x4 (Right Riser in x16) | +| | 1x 3.0 x4 (NVMe) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 6x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 6x PWM Fan connector | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSW-F] +- [Board manual] + +[Supermicro X11SSW-F]: https://www.supermicro.com/en/products/motherboard/x11ssw-f +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1784.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md \ No newline at end of file diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index d618342..958071c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -29,6 +29,7 @@ default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F default "X11SSH-F/LN4F" if BOARD_SUPERMICRO_X11SSH_F + default "X11SSW" if BOARD_SUPERMICRO_X11SSW_F config MAINBOARD_DIR default "supermicro/x11-lga1151-series" @@ -37,6 +38,7 @@ default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F default "x11ssh-f" if BOARD_SUPERMICRO_X11SSH_F + default "x11ssw-f" if BOARD_SUPERMICRO_X11SSW_F config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -85,5 +87,6 @@ default "0896" if BOARD_SUPERMICRO_X11SSM_F default "089C" if BOARD_SUPERMICRO_X11SSH_TF default "0884" if BOARD_SUPERMICRO_X11SSH_F + default "089B" if BOARD_SUPERMICRO_X11SSW_F endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name index 0f488a9..cdefa73 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -9,3 +9,7 @@ config BOARD_SUPERMICRO_X11SSH_F bool "X11SSH-F/LN4F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config BOARD_SUPERMICRO_X11SSW_F + bool "X11SSW-F" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/board_info.txt new file mode 100644 index 0000000..006c2ec --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSW-F +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSW-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio.c new file mode 100644 index 0000000..e37e008 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_NC(GPP_F9, NONE), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_NC(GPP_G12, NONE), + PAD_NC(GPP_G13, NONE), + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + PAD_NC(GPP_G16, NONE), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_NC(GPP_H4, NONE), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio_early.c new file mode 100644 index 0000000..3ea21e0 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb new file mode 100644 index 0000000..6984b83 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -0,0 +1,127 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + + # Additional FSP Configuration + # This board has an IGD with no output. + register "PrimaryDisplay" = "Display_Auto" + + # USB configuration + # NB: Overcurrent OCx values untested + # USB2/3 + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" + + # USB6/7 (USB3.0) + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" + + # USB8 (USB3.0) + register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB9/10 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" + + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" + end # CPU PCIE Slot JSXB1B + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.1 on # PCI Express Port 2 + register "PcieRpEnable[1]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" + end + device pci 1d.0 on # PCI Express Port 9 (Slot JSXB2) + register "PcieRpEnable[8]" = "1" + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1d.4 on # PCI Express Port 13 + register "PcieRpEnable[12]" = "1" + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + drq 0xf0 = 0x00 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + drq 0xf0 = 0x00 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/77610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 Gerrit-Change-Number: 77610 Gerrit-PatchSet: 1 Gerrit-Owner: Kieran Kunhya <kieran(a)kunhya.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/dell: Add OptiPlex 7020/9020 port
by Máté Kukri (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Angel Pons, Michael Büchler, Michał Żygowski, Stefan Reinauer. Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 25: (1 comment) Patchset: PS25: > Thank you for your work on this port! I tested this on a 9020 mini tower (MT). […] I am glad it works in the mini tower too, I'll hope you'll get some use out of it. I only own the SFF board so never had the opportunity to test that. As for the `overridetree.cb`s, it is definitely the right approach. My original plan was exactly that, to have 3 variants from the USFF, SFF, and MT. However I don't really use the port anymore, so it probably needs a new maintainer to be completed and merged at this point. -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 25 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Fri, 01 Sep 2023 16:38:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device/device.h: Rename pci_domain_scan_bus
by Nico Huber (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Raul Rangel, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Vanessa Eusebio, Werner Zeh, Yidi Lin, Yu-Ping Wu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77593?usp=email ) Change subject: device/device.h: Rename pci_domain_scan_bus ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I252343788001e277ec5a125cdd31cf95f2505185 Gerrit-Change-Number: 77593 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 16:16:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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